<s>
Random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
;	O
)	O
is	O
a	O
form	O
of	O
computer	B-General_Concept
memory	I-General_Concept
that	O
can	O
be	O
read	B-General_Concept
and	O
changed	O
in	O
any	O
order	O
,	O
typically	O
used	O
to	O
store	O
working	O
data	B-General_Concept
and	O
machine	B-Language
code	I-Language
.	O
</s>
<s>
A	O
random-access	B-Architecture
memory	I-Architecture
device	O
allows	O
data	B-General_Concept
items	O
to	O
be	O
read	B-General_Concept
or	O
written	O
in	O
almost	O
the	O
same	O
amount	O
of	O
time	O
irrespective	O
of	O
the	O
physical	O
location	O
of	O
data	B-General_Concept
inside	O
the	O
memory	O
,	O
in	O
contrast	O
with	O
other	O
direct-access	O
data	B-General_Concept
storage	I-General_Concept
media	I-General_Concept
(	O
such	O
as	O
hard	B-Device
disks	I-Device
,	O
CD-RWs	O
,	O
DVD-RWs	O
and	O
the	O
older	O
magnetic	B-Architecture
tapes	I-Architecture
and	O
drum	B-General_Concept
memory	I-General_Concept
)	O
,	O
where	O
the	O
time	O
required	O
to	O
read	B-General_Concept
and	O
write	O
data	B-General_Concept
items	O
varies	O
significantly	O
depending	O
on	O
their	O
physical	O
locations	O
on	O
the	O
recording	O
medium	O
,	O
due	O
to	O
mechanical	O
limitations	O
such	O
as	O
media	O
rotation	O
speeds	O
and	O
arm	O
movement	O
.	O
</s>
<s>
RAM	B-Architecture
contains	O
multiplexing	B-Architecture
and	O
demultiplexing	B-Architecture
circuitry	O
,	O
to	O
connect	O
the	O
data	B-General_Concept
lines	O
to	O
the	O
addressed	O
storage	O
for	O
reading	O
or	O
writing	O
the	O
entry	O
.	O
</s>
<s>
Usually	O
more	O
than	O
one	O
bit	O
of	O
storage	O
is	O
accessed	O
by	O
the	O
same	O
address	O
,	O
and	O
RAM	B-Architecture
devices	O
often	O
have	O
multiple	O
data	B-General_Concept
lines	O
and	O
are	O
said	O
to	O
be	O
"	O
8-bit	O
"	O
or	O
"	O
16-bit	B-Device
"	O
,	O
etc	O
.	O
</s>
<s>
In	O
today	O
's	O
technology	O
,	O
random-access	B-Architecture
memory	I-Architecture
takes	O
the	O
form	O
of	O
integrated	O
circuit	O
(	O
IC	O
)	O
chips	O
with	O
MOS	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
)	O
memory	B-Algorithm
cells	I-Algorithm
.	O
</s>
<s>
RAM	B-Architecture
is	O
normally	O
associated	O
with	O
volatile	B-General_Concept
types	O
of	O
memory	O
where	O
stored	O
information	O
is	O
lost	O
if	O
power	O
is	O
removed	O
.	O
</s>
<s>
The	O
two	O
main	O
types	O
of	O
volatile	B-General_Concept
random-access	B-General_Concept
semiconductor	B-Architecture
memory	I-Architecture
are	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	B-Architecture
)	O
and	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
.	O
</s>
<s>
and	O
other	O
types	O
of	O
non-volatile	B-General_Concept
memories	I-General_Concept
allow	O
random	B-General_Concept
access	I-General_Concept
for	O
read	B-General_Concept
operations	O
,	O
but	O
either	O
do	O
not	O
allow	O
write	O
operations	O
or	O
have	O
other	O
kinds	O
of	O
limitations	O
on	O
them	O
.	O
</s>
<s>
These	O
include	O
most	O
types	O
of	O
ROM	B-Device
and	O
a	O
type	O
of	O
flash	B-Device
memory	I-Device
called	O
NOR-Flash	O
.	O
</s>
<s>
Use	O
of	O
semiconductor	O
RAM	B-Architecture
dated	O
back	O
to	O
1965	O
,	O
when	O
IBM	O
introduced	O
the	O
monolithic	O
(	O
single-chip	O
)	O
16-bit	B-Device
SP95	O
SRAM	B-Architecture
chip	O
for	O
their	O
System/360	B-Application
Model	I-Application
95	I-Application
computer	O
,	O
and	O
Toshiba	O
used	O
discrete	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
for	O
its	O
180-bit	O
Toscal	O
BC-1411	O
electronic	O
calculator	O
,	O
both	O
based	O
on	O
bipolar	O
transistors	B-Application
.	O
</s>
<s>
While	O
it	O
offered	O
higher	O
speeds	O
than	O
magnetic-core	O
memory	O
,	O
bipolar	O
DRAM	O
could	O
not	O
compete	O
with	O
the	O
lower	O
price	O
of	O
the	O
then-dominant	O
magnetic-core	O
memory	O
.	O
</s>
<s>
MOS	B-Architecture
memory	I-Architecture
,	O
based	O
on	O
MOS	B-Architecture
transistors	I-Architecture
,	O
was	O
developed	O
in	O
the	O
late	O
1960s	O
,	O
and	O
was	O
the	O
basis	O
for	O
all	O
early	O
commercial	O
semiconductor	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
The	O
first	O
commercial	O
DRAM	O
IC	O
chip	O
,	O
the	O
1K	O
Intel	B-General_Concept
1103	I-General_Concept
,	O
was	O
introduced	O
in	O
October	O
1970	O
.	O
</s>
<s>
Synchronous	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
SDRAM	O
)	O
later	O
debuted	O
with	O
the	O
Samsung	B-Application
KM48SL2000	O
chip	O
in	O
1992	O
.	O
</s>
<s>
Early	O
computers	O
used	O
relays	O
,	O
mechanical	B-Device
counters	I-Device
or	O
delay	O
lines	O
for	O
main	O
memory	O
functions	O
.	O
</s>
<s>
Ultrasonic	O
delay	O
lines	O
were	O
serial	O
devices	O
which	O
could	O
only	O
reproduce	O
data	B-General_Concept
in	O
the	O
order	O
it	O
was	O
written	O
.	O
</s>
<s>
Drum	B-General_Concept
memory	I-General_Concept
could	O
be	O
expanded	O
at	O
relatively	O
low	O
cost	O
but	O
efficient	O
retrieval	O
of	O
memory	O
items	O
required	O
knowledge	O
of	O
the	O
physical	O
layout	O
of	O
the	O
drum	O
to	O
optimize	O
speed	O
.	O
</s>
<s>
Latches	B-General_Concept
built	O
out	O
of	O
vacuum	O
tube	O
triodes	O
,	O
and	O
later	O
,	O
out	O
of	O
discrete	O
transistors	B-Application
,	O
were	O
used	O
for	O
smaller	O
and	O
faster	O
memories	O
such	O
as	O
registers	O
.	O
</s>
<s>
Such	O
registers	O
were	O
relatively	O
large	O
and	O
too	O
costly	O
to	O
use	O
for	O
large	O
amounts	O
of	O
data	B-General_Concept
;	O
generally	O
only	O
a	O
few	O
dozen	O
or	O
few	O
hundred	O
bits	O
of	O
such	O
memory	O
could	O
be	O
provided	O
.	O
</s>
<s>
The	O
first	O
practical	O
form	O
of	O
random-access	B-Architecture
memory	I-Architecture
was	O
the	O
Williams	B-General_Concept
tube	I-General_Concept
starting	O
in	O
1947	O
.	O
</s>
<s>
It	O
stored	B-General_Concept
data	I-General_Concept
as	O
electrically	O
charged	O
spots	O
on	O
the	O
face	O
of	O
a	O
cathode-ray	B-Device
tube	I-Device
.	O
</s>
<s>
Since	O
the	O
electron	O
beam	O
of	O
the	O
CRT	O
could	O
read	B-General_Concept
and	O
write	O
the	O
spots	O
on	O
the	O
tube	O
in	O
any	O
order	O
,	O
memory	O
was	O
random	B-General_Concept
access	I-General_Concept
.	O
</s>
<s>
The	O
capacity	O
of	O
the	O
Williams	B-General_Concept
tube	I-General_Concept
was	O
a	O
few	O
hundred	O
to	O
around	O
a	O
thousand	O
bits	O
,	O
but	O
it	O
was	O
much	O
smaller	O
,	O
faster	O
,	O
and	O
more	O
power-efficient	O
than	O
using	O
individual	O
vacuum	O
tube	O
latches	B-General_Concept
.	O
</s>
<s>
Developed	O
at	O
the	O
University	O
of	O
Manchester	O
in	O
England	O
,	O
the	O
Williams	B-General_Concept
tube	I-General_Concept
provided	O
the	O
medium	O
on	O
which	O
the	O
first	O
electronically	O
stored	O
program	O
was	O
implemented	O
in	O
the	O
Manchester	B-Device
Baby	I-Device
computer	O
,	O
which	O
first	O
successfully	O
ran	O
a	O
program	O
on	O
21	O
June	O
1948	O
.	O
</s>
<s>
In	O
fact	O
,	O
rather	O
than	O
the	O
Williams	B-General_Concept
tube	I-General_Concept
memory	O
being	O
designed	O
for	O
the	O
Baby	O
,	O
the	O
Baby	O
was	O
a	O
testbed	O
to	O
demonstrate	O
the	O
reliability	O
of	O
the	O
memory	O
.	O
</s>
<s>
Magnetic-core	O
memory	O
was	O
invented	O
in	O
1947	O
and	O
developed	O
up	O
until	O
the	O
mid-1970s	O
.	O
</s>
<s>
It	O
became	O
a	O
widespread	O
form	O
of	O
random-access	B-Architecture
memory	I-Architecture
,	O
relying	O
on	O
an	O
array	O
of	O
magnetized	O
rings	O
.	O
</s>
<s>
By	O
changing	O
the	O
sense	O
of	O
each	O
ring	O
's	O
magnetization	O
,	O
data	B-General_Concept
could	O
be	O
stored	O
with	O
one	O
bit	O
stored	O
per	O
ring	O
.	O
</s>
<s>
Since	O
every	O
ring	O
had	O
a	O
combination	O
of	O
address	O
wires	O
to	O
select	O
and	O
read	B-General_Concept
or	O
write	O
it	O
,	O
access	O
to	O
any	O
memory	O
location	O
in	O
any	O
sequence	O
was	O
possible	O
.	O
</s>
<s>
Magnetic	O
core	B-Algorithm
memory	O
was	O
the	O
standard	O
form	O
of	O
computer	B-General_Concept
memory	I-General_Concept
system	O
until	O
displaced	O
by	O
solid-state	O
MOS	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
silicon	I-Architecture
)	O
semiconductor	B-Architecture
memory	I-Architecture
in	O
integrated	O
circuits	O
(	O
ICs	O
)	O
during	O
the	O
early	O
1970s	O
.	O
</s>
<s>
Prior	O
to	O
the	O
development	O
of	O
integrated	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
circuits	O
,	O
permanent	O
(	O
or	O
read-only	O
)	O
random-access	B-Architecture
memory	I-Architecture
was	O
often	O
constructed	O
using	O
diode	B-General_Concept
matrices	I-General_Concept
driven	O
by	O
address	B-Device
decoders	I-Device
,	O
or	O
specially	O
wound	O
core	B-General_Concept
rope	I-General_Concept
memory	I-General_Concept
planes	O
.	O
</s>
<s>
Semiconductor	B-Architecture
memory	I-Architecture
began	O
in	O
the	O
1960s	O
with	O
bipolar	O
memory	O
,	O
which	O
used	O
bipolar	O
transistors	B-Application
.	O
</s>
<s>
Although	O
it	O
was	O
faster	O
,	O
it	O
could	O
not	O
compete	O
with	O
the	O
lower	O
price	O
of	O
magnetic	O
core	B-Algorithm
memory	O
.	O
</s>
<s>
The	O
invention	O
of	O
the	O
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
,	O
also	O
known	O
as	O
the	O
MOS	B-Architecture
transistor	I-Architecture
,	O
by	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
led	O
to	O
the	O
development	O
of	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	B-Architecture
)	O
memory	O
by	O
John	O
Schmidt	O
at	O
Fairchild	O
Semiconductor	O
in	O
1964	O
.	O
</s>
<s>
In	O
addition	O
to	O
higher	O
speeds	O
,	O
MOS	B-Architecture
semiconductor	B-Architecture
memory	I-Architecture
was	O
cheaper	O
and	O
consumed	O
less	O
power	O
than	O
magnetic	O
core	B-Algorithm
memory	O
.	O
</s>
<s>
The	O
development	O
of	O
silicon-gate	O
MOS	B-Architecture
integrated	O
circuit	O
(	O
MOS	B-Architecture
IC	O
)	O
technology	O
by	O
Federico	O
Faggin	O
at	O
Fairchild	O
in	O
1968	O
enabled	O
the	O
production	O
of	O
MOS	B-Architecture
memory	I-Architecture
chips	O
.	O
</s>
<s>
MOS	B-Architecture
memory	I-Architecture
overtook	O
magnetic	O
core	B-Algorithm
memory	O
as	O
the	O
dominant	O
memory	O
technology	O
in	O
the	O
early	O
1970s	O
.	O
</s>
<s>
An	O
integrated	O
bipolar	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	B-Architecture
)	O
was	O
invented	O
by	O
Robert	O
H	O
.	O
Norman	O
at	O
Fairchild	O
Semiconductor	O
in	O
1963	O
.	O
</s>
<s>
It	O
was	O
followed	O
by	O
the	O
development	O
of	O
MOS	B-Architecture
SRAM	B-Architecture
by	O
John	O
Schmidt	O
at	O
Fairchild	O
in	O
1964	O
.	O
</s>
<s>
SRAM	B-Architecture
became	O
an	O
alternative	O
to	O
magnetic-core	O
memory	O
,	O
but	O
required	O
six	O
MOS	B-Architecture
transistors	I-Architecture
for	O
each	O
bit	O
of	O
data	B-General_Concept
.	O
</s>
<s>
Commercial	O
use	O
of	O
SRAM	B-Architecture
began	O
in	O
1965	O
,	O
when	O
IBM	O
introduced	O
the	O
SP95	O
memory	B-Architecture
chip	I-Architecture
for	O
the	O
System/360	B-Application
Model	I-Application
95	I-Application
.	O
</s>
<s>
Dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
allowed	O
replacement	O
of	O
a	O
4	O
or	O
6-transistor	O
latch	B-General_Concept
circuit	O
by	O
a	O
single	O
transistor	B-Application
for	O
each	O
memory	O
bit	O
,	O
greatly	O
increasing	O
memory	O
density	O
at	O
the	O
cost	O
of	O
volatility	O
.	O
</s>
<s>
Data	B-General_Concept
was	O
stored	O
in	O
the	O
tiny	O
capacitance	O
of	O
each	O
transistor	B-Application
,	O
and	O
had	O
to	O
be	O
periodically	O
refreshed	O
every	O
few	O
milliseconds	O
before	O
the	O
charge	O
could	O
leak	O
away	O
.	O
</s>
<s>
Toshiba	O
's	O
Toscal	O
BC-1411	O
electronic	O
calculator	O
,	O
which	O
was	O
introduced	O
in	O
1965	O
,	O
used	O
a	O
form	O
of	O
capacitive	O
bipolar	O
DRAM	O
,	O
storing	O
180-bit	O
data	B-General_Concept
on	O
discrete	O
memory	B-Algorithm
cells	I-Algorithm
,	O
consisting	O
of	O
germanium	O
bipolar	O
transistors	B-Application
and	O
capacitors	O
.	O
</s>
<s>
While	O
it	O
offered	O
higher	O
speeds	O
than	O
magnetic-core	O
memory	O
,	O
bipolar	O
DRAM	O
could	O
not	O
compete	O
with	O
the	O
lower	O
price	O
of	O
the	O
then	O
dominant	O
magnetic-core	O
memory	O
.	O
</s>
<s>
MOS	B-Architecture
technology	I-Architecture
is	O
the	O
basis	O
for	O
modern	O
DRAM	O
.	O
</s>
<s>
In	O
1966	O
,	O
Dr.	O
Robert	O
H	O
.	O
Dennard	O
at	O
the	O
IBM	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
was	O
working	O
on	O
MOS	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
While	O
examining	O
the	O
characteristics	O
of	O
MOS	B-Architecture
technology	I-Architecture
,	O
he	O
found	O
it	O
was	O
capable	O
of	O
building	O
capacitors	O
,	O
and	O
that	O
storing	O
a	O
charge	O
or	O
no	O
charge	O
on	O
the	O
MOS	B-Architecture
capacitor	O
could	O
represent	O
the	O
1	O
and	O
0	O
of	O
a	O
bit	O
,	O
while	O
the	O
MOS	B-Architecture
transistor	I-Architecture
could	O
control	O
writing	O
the	O
charge	O
to	O
the	O
capacitor	O
.	O
</s>
<s>
This	O
led	O
to	O
his	O
development	O
of	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
In	O
1967	O
,	O
Dennard	O
filed	O
a	O
patent	O
under	O
IBM	O
for	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
,	O
based	O
on	O
MOS	B-Architecture
technology	I-Architecture
.	O
</s>
<s>
The	O
first	O
commercial	O
DRAM	O
IC	O
chip	O
was	O
the	O
Intel	B-General_Concept
1103	I-General_Concept
,	O
which	O
was	O
manufactured	B-Architecture
on	O
an	O
8µm	O
MOS	B-Architecture
process	B-Architecture
with	O
a	O
capacity	O
of	O
1kbit	O
,	O
and	O
was	O
released	O
in	O
1970	O
.	O
</s>
<s>
Synchronous	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
SDRAM	O
)	O
was	O
developed	O
by	O
Samsung	B-Application
Electronics	O
.	O
</s>
<s>
The	O
first	O
commercial	O
SDRAM	O
chip	O
was	O
the	O
Samsung	B-Application
KM48SL2000	O
,	O
which	O
had	O
a	O
capacity	O
of	O
16Mbit	O
.	O
</s>
<s>
It	O
was	O
introduced	O
by	O
Samsung	B-Application
in	O
1992	O
,	O
and	O
mass-produced	O
in	O
1993	O
.	O
</s>
<s>
The	O
first	O
commercial	O
DDR	O
SDRAM	O
(	O
double	O
data	B-General_Concept
rate	O
SDRAM	O
)	O
memory	B-Architecture
chip	I-Architecture
was	O
Samsung	B-Application
's	O
64Mbit	O
DDR	O
SDRAM	O
chip	O
,	O
released	O
in	O
June	O
1998	O
.	O
</s>
<s>
GDDR	B-Device
(	O
graphics	O
DDR	O
)	O
is	O
a	O
form	O
of	O
DDR	O
SGRAM	O
(	O
synchronous	O
graphics	O
RAM	B-Architecture
)	O
,	O
which	O
was	O
first	O
released	O
by	O
Samsung	B-Application
as	O
a	O
16Mbit	O
memory	B-Architecture
chip	I-Architecture
in	O
1998	O
.	O
</s>
<s>
The	O
two	O
widely	O
used	O
forms	O
of	O
modern	O
RAM	B-Architecture
are	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	B-Architecture
)	O
and	O
dynamic	O
RAM	B-Architecture
(	O
DRAM	O
)	O
.	O
</s>
<s>
In	O
SRAM	B-Architecture
,	O
a	O
bit	O
of	O
data	B-General_Concept
is	O
stored	O
using	O
the	O
state	O
of	O
a	O
six-transistor	O
memory	B-Algorithm
cell	I-Algorithm
,	O
typically	O
using	O
six	O
MOSFETs	B-Architecture
.	O
</s>
<s>
This	O
form	O
of	O
RAM	B-Architecture
is	O
more	O
expensive	O
to	O
produce	O
,	O
but	O
is	O
generally	O
faster	O
and	O
requires	O
less	O
dynamic	O
power	O
than	O
DRAM	O
.	O
</s>
<s>
In	O
modern	O
computers	O
,	O
SRAM	B-Architecture
is	O
often	O
used	O
as	O
cache	B-General_Concept
memory	I-General_Concept
for	I-General_Concept
the	I-General_Concept
CPU	I-General_Concept
.	O
</s>
<s>
DRAM	O
stores	O
a	O
bit	O
of	O
data	B-General_Concept
using	O
a	O
transistor	B-Application
and	O
capacitor	O
pair	O
(	O
typically	O
a	O
MOSFET	B-Architecture
and	O
MOS	B-Architecture
capacitor	O
,	O
respectively	O
)	O
,	O
which	O
together	O
comprise	O
a	O
DRAM	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
The	O
capacitor	O
holds	O
a	O
high	O
or	O
low	O
charge	O
(	O
1	O
or	O
0	O
,	O
respectively	O
)	O
,	O
and	O
the	O
transistor	B-Application
acts	O
as	O
a	O
switch	O
that	O
lets	O
the	O
control	O
circuitry	O
on	O
the	O
chip	O
read	B-General_Concept
the	O
capacitor	O
's	O
state	O
of	O
charge	O
or	O
change	O
it	O
.	O
</s>
<s>
As	O
this	O
form	O
of	O
memory	O
is	O
less	O
expensive	O
to	O
produce	O
than	O
static	B-Architecture
RAM	I-Architecture
,	O
it	O
is	O
the	O
predominant	O
form	O
of	O
computer	B-General_Concept
memory	I-General_Concept
used	O
in	O
modern	O
computers	O
.	O
</s>
<s>
Both	O
static	O
and	O
dynamic	O
RAM	B-Architecture
are	O
considered	O
volatile	B-General_Concept
,	O
as	O
their	O
state	O
is	O
lost	O
or	O
reset	O
when	O
power	O
is	O
removed	O
from	O
the	O
system	O
.	O
</s>
<s>
By	O
contrast	O
,	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
stores	O
data	B-General_Concept
by	O
permanently	O
enabling	O
or	O
disabling	O
selected	O
transistors	B-Application
,	O
such	O
that	O
the	O
memory	O
cannot	O
be	O
altered	O
.	O
</s>
<s>
Writeable	O
variants	O
of	O
ROM	B-Device
(	O
such	O
as	O
EEPROM	B-General_Concept
and	O
NOR	O
flash	O
)	O
share	O
properties	O
of	O
both	O
ROM	B-Device
and	O
RAM	B-Architecture
,	O
enabling	O
data	B-General_Concept
to	O
persist	B-Application
without	O
power	O
and	O
to	O
be	O
updated	O
without	O
requiring	O
special	O
equipment	O
.	O
</s>
<s>
ECC	B-General_Concept
memory	I-General_Concept
(	O
which	O
can	O
be	O
either	O
SRAM	B-Architecture
or	O
DRAM	O
)	O
includes	O
special	O
circuitry	O
to	O
detect	O
and/or	O
correct	O
random	O
faults	O
(	O
memory	O
errors	O
)	O
in	O
the	O
stored	B-General_Concept
data	I-General_Concept
,	O
using	O
parity	B-Error_Name
bits	I-Error_Name
or	O
error	O
correction	O
codes	O
.	O
</s>
<s>
In	O
general	O
,	O
the	O
term	O
RAM	B-Architecture
refers	O
solely	O
to	O
solid-state	O
memory	B-General_Concept
devices	I-General_Concept
(	O
either	O
DRAM	O
or	O
SRAM	B-Architecture
)	O
,	O
and	O
more	O
specifically	O
the	O
main	O
memory	O
in	O
most	O
computers	O
.	O
</s>
<s>
In	O
optical	O
storage	O
,	O
the	O
term	O
DVD-RAM	O
is	O
somewhat	O
of	O
a	O
misnomer	O
since	O
,	O
unlike	O
CD-RW	O
or	O
DVD-RW	O
it	O
does	O
not	O
need	O
to	O
be	O
erased	O
before	O
reuse	O
.	O
</s>
<s>
Nevertheless	O
,	O
a	O
DVD-RAM	O
behaves	O
much	O
like	O
a	O
hard	B-Device
disc	I-Device
drive	I-Device
if	O
somewhat	O
slower	O
.	O
</s>
<s>
The	O
memory	B-Algorithm
cell	I-Algorithm
is	O
the	O
fundamental	O
building	O
block	O
of	O
computer	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
memory	B-Algorithm
cell	I-Algorithm
is	O
an	O
electronic	O
circuit	O
that	O
stores	O
one	O
bit	O
of	O
binary	O
information	O
and	O
it	O
must	O
be	O
set	O
to	O
store	O
a	O
logic	O
1	O
(	O
high	O
voltage	O
level	O
)	O
and	O
reset	O
to	O
store	O
a	O
logic	O
0	O
(	O
low	O
voltage	O
level	O
)	O
.	O
</s>
<s>
Its	O
value	O
is	O
maintained/stored	O
until	O
it	O
is	O
changed	O
by	O
the	O
set/reset	O
process	B-Architecture
.	O
</s>
<s>
The	O
value	O
in	O
the	O
memory	B-Algorithm
cell	I-Algorithm
can	O
be	O
accessed	O
by	O
reading	O
it	O
.	O
</s>
<s>
In	O
SRAM	B-Architecture
,	O
the	O
memory	B-Algorithm
cell	I-Algorithm
is	O
a	O
type	O
of	O
flip-flop	B-General_Concept
circuit	O
,	O
usually	O
implemented	O
using	O
FETs	O
.	O
</s>
<s>
This	O
means	O
that	O
SRAM	B-Architecture
requires	O
very	O
low	O
power	O
when	O
not	O
being	O
accessed	O
,	O
but	O
it	O
is	O
expensive	O
and	O
has	O
low	O
storage	O
density	O
.	O
</s>
<s>
Charging	O
and	O
discharging	O
this	O
capacitor	O
can	O
store	O
a	O
"	O
1	O
"	O
or	O
a	O
"	O
0	O
"	O
in	O
the	O
cell	B-Algorithm
.	O
</s>
<s>
Because	O
of	O
this	O
refresh	O
process	B-Architecture
,	O
DRAM	O
uses	O
more	O
power	O
,	O
but	O
it	O
can	O
achieve	O
greater	O
storage	O
densities	O
and	O
lower	O
unit	O
costs	O
compared	O
to	O
SRAM	B-Architecture
.	O
</s>
<s>
To	O
be	O
useful	O
,	O
memory	B-Algorithm
cells	I-Algorithm
must	O
be	O
readable	O
and	O
writeable	O
.	O
</s>
<s>
Within	O
the	O
RAM	B-Architecture
device	O
,	O
multiplexing	B-Architecture
and	O
demultiplexing	B-Architecture
circuitry	O
is	O
used	O
to	O
select	O
memory	B-Algorithm
cells	I-Algorithm
.	O
</s>
<s>
Typically	O
,	O
a	O
RAM	B-Architecture
device	O
has	O
a	O
set	O
of	O
address	O
lines	O
,	O
and	O
for	O
each	O
combination	O
of	O
bits	O
that	O
may	O
be	O
applied	O
to	O
these	O
lines	O
,	O
a	O
set	O
of	O
memory	B-Algorithm
cells	I-Algorithm
are	O
activated	O
.	O
</s>
<s>
Due	O
to	O
this	O
addressing	O
,	O
RAM	B-Architecture
devices	O
virtually	O
always	O
have	O
a	O
memory	O
capacity	O
that	O
is	O
a	O
power	O
of	O
two	O
.	O
</s>
<s>
Usually	O
several	O
memory	B-Algorithm
cells	I-Algorithm
share	O
the	O
same	O
address	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
4	O
bit	O
'	O
wide	O
 '	O
RAM	B-Architecture
chip	I-Architecture
has	O
4	O
memory	B-Algorithm
cells	I-Algorithm
for	O
each	O
address	O
.	O
</s>
<s>
Often	O
the	O
width	O
of	O
the	O
memory	O
and	O
that	O
of	O
the	O
microprocessor	O
are	O
different	O
,	O
for	O
a	O
32	O
bit	O
microprocessor	O
,	O
eight	O
4	O
bit	O
RAM	B-Architecture
chips	I-Architecture
would	O
be	O
needed	O
.	O
</s>
<s>
In	O
that	O
case	O
,	O
external	O
multiplexors	B-Protocol
to	O
the	O
device	O
are	O
used	O
to	O
activate	O
the	O
correct	O
device	O
that	O
is	O
being	O
accessed	O
.	O
</s>
<s>
One	O
can	O
read	B-General_Concept
and	O
over-write	O
data	B-General_Concept
in	O
RAM	B-Architecture
.	O
</s>
<s>
Many	O
computer	O
systems	O
have	O
a	O
memory	O
hierarchy	O
consisting	O
of	O
processor	B-General_Concept
registers	I-General_Concept
,	O
on-die	O
SRAM	B-Architecture
caches	B-General_Concept
,	O
external	O
caches	B-General_Concept
,	O
DRAM	O
,	O
paging	B-Architecture
systems	O
and	O
virtual	B-Architecture
memory	I-Architecture
or	O
swap	B-Architecture
space	O
on	O
a	O
hard	B-Device
drive	I-Device
.	O
</s>
<s>
This	O
entire	O
pool	O
of	O
memory	O
may	O
be	O
referred	O
to	O
as	O
"	O
RAM	B-Architecture
"	O
by	O
many	O
developers	O
,	O
even	O
though	O
the	O
various	O
subsystems	O
can	O
have	O
very	O
different	O
access	B-General_Concept
times	I-General_Concept
,	O
violating	O
the	O
original	O
concept	O
behind	O
the	O
random	B-General_Concept
access	I-General_Concept
term	O
in	O
RAM	B-Architecture
.	O
</s>
<s>
Even	O
within	O
a	O
hierarchy	O
level	O
such	O
as	O
DRAM	O
,	O
the	O
specific	O
row	O
,	O
column	O
,	O
bank	O
,	O
rank	B-General_Concept
,	O
channel	O
,	O
or	O
interleave	B-General_Concept
organization	O
of	O
the	O
components	O
make	O
the	O
access	B-General_Concept
time	I-General_Concept
variable	O
,	O
although	O
not	O
to	O
the	O
extent	O
that	O
access	B-General_Concept
time	I-General_Concept
to	O
rotating	O
storage	B-General_Concept
media	I-General_Concept
or	O
a	O
tape	O
is	O
variable	O
.	O
</s>
<s>
The	O
overall	O
goal	O
of	O
using	O
a	O
memory	O
hierarchy	O
is	O
to	O
obtain	O
the	O
fastest	O
possible	O
average	O
access	B-General_Concept
time	I-General_Concept
while	O
minimizing	O
the	O
total	O
cost	O
of	O
the	O
entire	O
memory	O
system	O
(	O
generally	O
,	O
the	O
memory	O
hierarchy	O
follows	O
the	O
access	B-General_Concept
time	I-General_Concept
with	O
the	O
fast	O
CPU	B-General_Concept
registers	I-General_Concept
at	O
the	O
top	O
and	O
the	O
slow	O
hard	B-Device
drive	I-Device
at	O
the	O
bottom	O
)	O
.	O
</s>
<s>
In	O
many	O
modern	O
personal	B-Device
computers	I-Device
,	O
the	O
RAM	B-Architecture
comes	O
in	O
an	O
easily	O
upgraded	O
form	O
of	O
modules	B-General_Concept
called	O
memory	B-General_Concept
modules	I-General_Concept
or	O
DRAM	O
modules	B-General_Concept
about	O
the	O
size	O
of	O
a	O
few	O
sticks	O
of	O
chewing	O
gum	O
.	O
</s>
<s>
As	O
suggested	O
above	O
,	O
smaller	O
amounts	O
of	O
RAM	B-Architecture
(	O
mostly	O
SRAM	B-Architecture
)	O
are	O
also	O
integrated	O
in	O
the	O
CPU	B-General_Concept
and	O
other	O
ICs	O
on	O
the	O
motherboard	B-Device
,	O
as	O
well	O
as	O
in	O
hard-drives	B-Device
,	O
CD-ROMs	B-Device
,	O
and	O
several	O
other	O
parts	O
of	O
the	O
computer	O
system	O
.	O
</s>
<s>
In	O
addition	O
to	O
serving	O
as	O
temporary	O
storage	O
and	O
working	O
space	O
for	O
the	O
operating	B-General_Concept
system	I-General_Concept
and	O
applications	O
,	O
RAM	B-Architecture
is	O
used	O
in	O
numerous	O
other	O
ways	O
.	O
</s>
<s>
Most	O
modern	O
operating	B-General_Concept
systems	I-General_Concept
employ	O
a	O
method	O
of	O
extending	O
RAM	B-Architecture
capacity	O
,	O
known	O
as	O
"	O
virtual	B-Architecture
memory	I-Architecture
"	O
.	O
</s>
<s>
A	O
portion	O
of	O
the	O
computer	O
's	O
hard	B-Device
drive	I-Device
is	O
set	O
aside	O
for	O
a	O
paging	B-Architecture
file	I-Architecture
or	O
a	O
scratch	O
partition	O
,	O
and	O
the	O
combination	O
of	O
physical	O
RAM	B-Architecture
and	O
the	O
paging	B-Architecture
file	I-Architecture
form	O
the	O
system	O
's	O
total	O
memory	O
.	O
</s>
<s>
(	O
For	O
example	O
,	O
if	O
a	O
computer	O
has	O
2	O
GB	O
(	O
10243	O
B	O
)	O
of	O
RAM	B-Architecture
and	O
a	O
1	O
GB	O
page	B-Architecture
file	I-Architecture
,	O
the	O
operating	B-General_Concept
system	I-General_Concept
has	O
3	O
GB	O
total	O
memory	O
available	O
to	O
it	O
.	O
)	O
</s>
<s>
When	O
the	O
system	O
runs	O
low	O
on	O
physical	O
memory	O
,	O
it	O
can	O
"	O
swap	B-Architecture
"	O
portions	O
of	O
RAM	B-Architecture
to	O
the	O
paging	B-Architecture
file	I-Architecture
to	O
make	O
room	O
for	O
new	O
data	B-General_Concept
,	O
as	O
well	O
as	O
to	O
read	B-General_Concept
previously	O
swapped	O
information	O
back	O
into	O
RAM	B-Architecture
.	O
</s>
<s>
Excessive	O
use	O
of	O
this	O
mechanism	O
results	O
in	O
thrashing	B-General_Concept
and	O
generally	O
hampers	O
overall	O
system	O
performance	O
,	O
mainly	O
because	O
hard	B-Device
drives	I-Device
are	O
far	O
slower	O
than	O
RAM	B-Architecture
.	O
</s>
<s>
Software	O
can	O
"	O
partition	O
"	O
a	O
portion	O
of	O
a	O
computer	O
's	O
RAM	B-Architecture
,	O
allowing	O
it	O
to	O
act	O
as	O
a	O
much	O
faster	O
hard	B-Device
drive	I-Device
that	O
is	O
called	O
a	O
RAM	B-Application
disk	I-Application
.	O
</s>
<s>
A	O
RAM	B-Application
disk	I-Application
loses	O
the	O
stored	B-General_Concept
data	I-General_Concept
when	O
the	O
computer	O
is	O
shut	O
down	O
,	O
unless	O
memory	O
is	O
arranged	O
to	O
have	O
a	O
standby	O
battery	O
source	O
,	O
or	O
changes	O
to	O
the	O
RAM	B-Application
disk	I-Application
are	O
written	O
out	O
to	O
a	O
nonvolatile	O
disk	O
.	O
</s>
<s>
The	O
RAM	B-Application
disk	I-Application
is	O
reloaded	O
from	O
the	O
physical	O
disk	O
upon	O
RAM	B-Application
disk	I-Application
initialization	O
.	O
</s>
<s>
Sometimes	O
,	O
the	O
contents	O
of	O
a	O
relatively	O
slow	O
ROM	B-Device
chip	I-Device
are	O
copied	O
to	O
read/write	B-General_Concept
memory	I-General_Concept
to	O
allow	O
for	O
shorter	O
access	B-General_Concept
times	I-General_Concept
.	O
</s>
<s>
The	O
ROM	B-Device
chip	I-Device
is	O
then	O
disabled	O
while	O
the	O
initialized	O
memory	O
locations	O
are	O
switched	O
in	O
on	O
the	O
same	O
block	O
of	O
addresses	O
(	O
often	O
write-protected	O
)	O
.	O
</s>
<s>
This	O
process	B-Architecture
,	O
sometimes	O
called	O
shadowing	O
,	O
is	O
fairly	O
common	O
in	O
both	O
computers	O
and	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
As	O
a	O
common	O
example	O
,	O
the	O
BIOS	B-Operating_System
in	O
typical	O
personal	B-Device
computers	I-Device
often	O
has	O
an	O
option	O
called	O
"	O
use	O
shadow	O
BIOS	B-Operating_System
"	O
or	O
similar	O
.	O
</s>
<s>
When	O
enabled	O
,	O
functions	O
that	O
rely	O
on	O
data	B-General_Concept
from	O
the	O
BIOS	B-Operating_System
's	O
ROM	B-Device
instead	O
use	O
DRAM	O
locations	O
(	O
most	O
can	O
also	O
toggle	O
shadowing	O
of	O
video	O
card	O
ROM	B-Device
or	O
other	O
ROM	B-Device
sections	O
)	O
.	O
</s>
<s>
For	O
example	O
,	O
some	O
hardware	O
may	O
be	O
inaccessible	O
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
if	O
shadow	O
RAM	B-Architecture
is	O
used	O
.	O
</s>
<s>
On	O
some	O
systems	O
the	O
benefit	O
may	O
be	O
hypothetical	O
because	O
the	O
BIOS	B-Operating_System
is	O
not	O
used	O
after	O
booting	O
in	O
favor	O
of	O
direct	O
hardware	O
access	O
.	O
</s>
<s>
Several	O
new	O
types	O
of	O
non-volatile	B-General_Concept
RAM	I-General_Concept
,	O
which	O
preserve	O
data	B-General_Concept
while	O
powered	O
down	O
,	O
are	O
under	O
development	O
.	O
</s>
<s>
Amongst	O
the	O
1st	O
generation	O
MRAM	B-General_Concept
,	O
a	O
128	O
kbit	O
(	O
bytes	O
)	O
chip	O
was	O
manufactured	B-Architecture
with	O
0.18	O
µm	O
technology	O
in	O
the	O
summer	O
of	O
2003	O
.	O
</s>
<s>
In	O
June	O
2004	O
,	O
Infineon	O
Technologies	O
unveiled	O
a	O
16	B-Device
MB	O
(	O
16	B-Device
×	O
220	O
bytes	O
)	O
prototype	O
again	O
based	O
on	O
0.18	O
µm	O
technology	O
.	O
</s>
<s>
There	O
are	O
two	O
2nd	O
generation	O
techniques	O
currently	O
in	O
development	O
:	O
thermal-assisted	B-General_Concept
switching	I-General_Concept
(	O
TAS	O
)	O
The	O
Emergence	O
of	O
Practical	O
MRAM	B-General_Concept
which	O
is	O
being	O
developed	O
by	O
Crocus	O
Technology	O
,	O
and	O
spin-transfer	B-General_Concept
torque	I-General_Concept
(	O
STT	O
)	O
on	O
which	O
Crocus	O
,	O
Hynix	O
,	O
IBM	O
,	O
and	O
several	O
other	O
companies	O
are	O
working	O
.	O
</s>
<s>
Whether	O
some	O
of	O
these	O
technologies	O
can	O
eventually	O
take	O
significant	O
market	O
share	O
from	O
either	O
DRAM	O
,	O
SRAM	B-Architecture
,	O
or	O
flash-memory	O
technology	O
,	O
however	O
,	O
remains	O
to	O
be	O
seen	O
.	O
</s>
<s>
Since	O
2006	O
,	O
"	O
solid-state	B-Device
drives	I-Device
"	O
(	O
based	O
on	O
flash	B-Device
memory	I-Device
)	O
with	O
capacities	O
exceeding	O
256	O
gigabytes	O
and	O
speeds	O
far	O
exceeding	O
traditional	O
disks	O
have	O
become	O
available	O
.	O
</s>
<s>
This	O
development	O
has	O
started	O
to	O
blur	O
the	O
definition	O
between	O
traditional	O
random-access	B-Architecture
memory	I-Architecture
and	O
"	O
disks	O
"	O
,	O
dramatically	O
reducing	O
the	O
difference	O
in	O
speed	O
.	O
</s>
<s>
Some	O
kinds	O
of	O
random-access	B-Architecture
memory	I-Architecture
,	O
such	O
as	O
"	O
EcoRAM	O
"	O
,	O
are	O
specifically	O
designed	O
for	O
server	B-Operating_System
farms	I-Operating_System
,	O
where	O
low	O
power	O
consumption	O
is	O
more	O
important	O
than	O
speed	O
.	O
</s>
<s>
The	O
"	O
memory	O
wall	O
"	O
is	O
the	O
growing	O
disparity	O
of	O
speed	O
between	O
CPU	B-General_Concept
and	O
memory	O
outside	O
the	O
CPU	B-General_Concept
chip	O
.	O
</s>
<s>
From	O
1986	O
to	O
2000	O
,	O
CPU	B-General_Concept
speed	O
improved	O
at	O
an	O
annual	O
rate	O
of	O
55%	O
while	O
memory	O
speed	O
only	O
improved	O
at	O
10%	O
.	O
</s>
<s>
Given	O
these	O
trends	O
,	O
it	O
was	O
expected	O
that	O
memory	B-General_Concept
latency	I-General_Concept
would	O
become	O
an	O
overwhelming	O
bottleneck	O
in	O
computer	O
performance	O
.	O
</s>
<s>
CPU	B-General_Concept
speed	O
improvements	O
slowed	O
significantly	O
partly	O
due	O
to	O
major	O
physical	O
barriers	O
and	O
partly	O
because	O
current	O
CPU	B-General_Concept
designs	O
have	O
already	O
hit	O
the	O
memory	O
wall	O
in	O
some	O
sense	O
.	O
</s>
<s>
First	O
of	O
all	O
,	O
as	O
chip	O
geometries	O
shrink	O
and	O
clock	O
frequencies	O
rise	O
,	O
the	O
transistor	B-Application
leakage	O
current	O
increases	O
,	O
leading	O
to	O
excess	O
power	O
consumption	O
and	O
heat	O
...	O
Secondly	O
,	O
the	O
advantages	O
of	O
higher	O
clock	O
speeds	O
are	O
in	O
part	O
negated	O
by	O
memory	B-General_Concept
latency	I-General_Concept
,	O
since	O
memory	B-Architecture
access	I-Architecture
times	I-Architecture
have	O
not	O
been	O
able	O
to	O
keep	O
pace	O
with	O
increasing	O
clock	O
frequencies	O
.	O
</s>
<s>
The	O
RC	O
delays	O
in	O
signal	O
transmission	O
were	O
also	O
noted	O
in	O
"	O
Clock	O
Rate	O
versus	O
IPC	O
:	O
The	O
End	O
of	O
the	O
Road	O
for	O
Conventional	O
Microarchitectures	O
"	O
which	O
projected	O
a	O
maximum	O
of	O
12.5	O
%	O
average	O
annual	O
CPU	B-General_Concept
performance	O
improvement	O
between	O
2000	O
and	O
2014	O
.	O
</s>
<s>
A	O
different	O
concept	O
is	O
the	O
processor-memory	O
performance	O
gap	O
,	O
which	O
can	O
be	O
addressed	O
by	O
3D	B-Architecture
integrated	I-Architecture
circuits	I-Architecture
that	O
reduce	O
the	O
distance	O
between	O
the	O
logic	O
and	O
memory	O
aspects	O
that	O
are	O
further	O
apart	O
in	O
a	O
2D	O
chip	O
.	O
</s>
<s>
The	O
main	O
method	O
of	O
bridging	O
the	O
gap	O
is	O
the	O
use	O
of	O
caches	B-General_Concept
;	O
small	O
amounts	O
of	O
high-speed	O
memory	O
that	O
houses	O
recent	O
operations	O
and	O
instructions	O
nearby	O
the	O
processor	O
,	O
speeding	O
up	O
the	O
execution	O
of	O
those	O
operations	O
or	O
instructions	O
in	O
cases	O
where	O
they	O
are	O
called	O
upon	O
frequently	O
.	O
</s>
<s>
Multiple	O
levels	O
of	O
caching	B-General_Concept
have	O
been	O
developed	O
to	O
deal	O
with	O
the	O
widening	O
gap	O
,	O
and	O
the	O
performance	O
of	O
high-speed	O
modern	O
computers	O
relies	O
on	O
evolving	O
caching	B-General_Concept
techniques	O
.	O
</s>
<s>
Solid-state	B-Device
hard	I-Device
drives	I-Device
have	O
continued	O
to	O
increase	O
in	O
speed	O
,	O
from	O
~	O
400	O
Mbit/s	O
via	O
SATA3	O
in	O
2012	O
up	O
to	O
~	O
3	O
GB/s	O
via	O
NVMe/PCIe	O
in	O
2018	O
,	O
closing	O
the	O
gap	O
between	O
RAM	B-Architecture
and	O
hard	B-Device
disk	I-Device
speeds	O
,	O
although	O
RAM	B-Architecture
continues	O
to	O
be	O
an	O
order	O
of	O
magnitude	O
faster	O
,	O
with	O
single-lane	O
DDR4	O
3200	O
capable	O
of	O
25	O
GB/s	O
,	O
and	O
modern	O
GDDR	B-Device
even	O
faster	O
.	O
</s>
<s>
Fast	O
,	O
cheap	O
,	O
non-volatile	B-General_Concept
solid	B-Device
state	I-Device
drives	I-Device
have	O
replaced	O
some	O
functions	O
formerly	O
performed	O
by	O
RAM	B-Architecture
,	O
such	O
as	O
holding	O
certain	O
data	B-General_Concept
for	O
immediate	O
availability	O
in	O
server	B-Operating_System
farms	I-Operating_System
-	O
1	O
terabyte	O
of	O
SSD	B-Device
storage	O
can	O
be	O
had	O
for	O
$200	O
,	O
while	O
1	O
TB	O
of	O
RAM	B-Architecture
would	O
cost	O
thousands	O
of	O
dollars	O
.	O
</s>
<s>
+	O
Dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
Date	O
of	O
introduction	O
Chip	O
name	O
Capacity	O
(	O
bits	O
)	O
DRAM	O
type	O
Manufacturer(s )	O
ProcessMOSFET	O
Area	O
19651	O
bitDRAM	O
(	O
cell	B-Algorithm
)	O
ToshibaToshiba	O
"	O
Toscal	O
"	O
BC-1411	O
Desktop	O
Calculator	O
19671	O
bitDRAM	O
(	O
cell	B-Algorithm
)	O
IBMMOS1968256	O
bitDRAM	O
(	O
IC	O
)	O
FairchildPMOS19691	O
bitDRAM	O
(	O
cell	B-Algorithm
)	O
IntelPMOS197011021	O
kbitDRAM	O
(	O
IC	O
)	O
Intel	O
,	O
HoneywellPMOS11031	O
kbitDRAMIntel	O
8,000	O
nmPMOS10	O
mm²The	O
DRAM	O
memory	O
of	O
Robert	O
Dennard	O
history-computer.com1971μPD4031	O
kbitDRAMNECNMOS2	O
kbitDRAMGeneral	O
InstrumentPMOS13	O
mm²197221074	O
kbitDRAMIntelNMOS19738	O
kbitDRAMIBMPMOS19	O
mm²1975211616	O
kbitDRAMIntelNMOS197764	O
kbitDRAMNTTNMOS35	O
mm²1979MK481616	O
kbitPSRAMMostekNMOS64	O
kbitDRAMSiemensVMOS25	O
mm²1980256	O
kbitDRAMNEC	O
,	O
NTT1	O
,	O
0001	O
,	O
500	O
nmNMOS3442	O
mm²1981288	O
kbitDRAMIBMMOS25	O
mm²	O
1983	O
64	B-Device
kbitDRAMIntel	O
1,500	O
nmCMOS20	O
mm²	O
256	O
kbitDRAMNTTCMOS31	O
mm²8	O
MbitDRAMHitachiMOS1	O
MbitDRAMHitachi	O
,	O
NEC	O
1,000	O
nmNMOS7476	O
mm²NTT800	O
nmCMOS53	O
mm²1984TMS416164	O
kbitDPRAM	O
(	O
VRAM	O
)	O
Texas	O
InstrumentsNMOSμPD41264256	O
kbitDPRAM	O
(	O
VRAM	O
)	O
NECNMOS1	O
MbitPSRAMToshibaCMOS	O
1986	O
4	O
Mbit	O
DRAMNEC800	O
nmNMOS99	O
mm²	O
Texas	O
Instruments	O
,	O
Toshiba	O
1,000	O
nmCMOS100137	O
mm²198716	O
MbitDRAMNTT700	O
nmCMOS148	O
mm²512	O
kbitHSDRAMIBM	O
1,000	O
nmCMOS78	O
mm²199164	O
MbitDRAMMatsushita	O
,	O
Mitsubishi	O
,	O
Fujitsu	O
,	O
Toshiba400	O
nmCMOS1993256	O
MbitDRAMHitachi	O
,	O
NEC250	O
nmCMOS19954	O
MbitDPRAM	O
(	O
VRAM	O
)	O
HitachiCMOS1	O
GbitDRAMNEC250	O
nmCMOSBreaking	O
the	O
gigabit	O
barrier	O
,	O
DRAMs	O
at	O
ISSCC	O
portend	O
major	O
system-design	O
impact	O
.	O
</s>
