<s>
Racetrack	B-General_Concept
memory	I-General_Concept
or	O
domain-wall	B-General_Concept
memory	I-General_Concept
(	O
DWM	O
)	O
is	O
an	O
experimental	O
non-volatile	B-General_Concept
memory	I-General_Concept
device	O
under	O
development	O
at	O
IBM	O
's	O
Almaden	O
Research	O
Center	O
by	O
a	O
team	O
led	O
by	O
physicist	O
Stuart	O
Parkin	O
.	O
</s>
<s>
If	O
it	O
were	O
to	O
be	O
developed	O
successfully	O
,	O
racetrack	B-General_Concept
memory	I-General_Concept
would	O
offer	O
storage	B-Device
density	I-Device
higher	O
than	O
comparable	O
solid-state	O
memory	O
devices	O
like	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Racetrack	B-General_Concept
memory	I-General_Concept
uses	O
a	O
spin-coherent	O
electric	O
current	O
to	O
move	O
magnetic	O
domains	O
along	O
a	O
nanoscopic	O
permalloy	O
wire	O
about	O
200nm	O
across	O
and	O
100nm	O
thick	O
.	O
</s>
<s>
As	O
current	O
is	O
passed	O
through	O
the	O
wire	O
,	O
the	O
domains	O
pass	O
by	O
magnetic	O
read/write	B-Device
heads	I-Device
positioned	O
near	O
the	O
wire	O
,	O
which	O
alter	O
the	O
domains	O
to	O
record	O
patterns	O
of	O
bits	O
.	O
</s>
<s>
A	O
racetrack	B-General_Concept
memory	I-General_Concept
device	O
is	O
made	O
up	O
of	O
many	O
such	O
wires	O
and	O
read/write	O
elements	O
.	O
</s>
<s>
In	O
general	O
operational	O
concept	O
,	O
racetrack	B-General_Concept
memory	I-General_Concept
is	O
similar	O
to	O
the	O
earlier	O
bubble	B-General_Concept
memory	I-General_Concept
of	O
the	O
1960s	O
and	O
1970s	O
.	O
</s>
<s>
Delay-line	O
memory	O
,	O
such	O
as	O
mercury	O
delay	O
lines	O
of	O
the	O
1940s	O
and	O
1950s	O
,	O
are	O
a	O
still-earlier	O
form	O
of	O
similar	O
technology	O
,	O
as	O
used	O
in	O
the	O
UNIVAC	O
and	O
EDSAC	B-Device
computers	O
.	O
</s>
<s>
Like	O
bubble	B-General_Concept
memory	I-General_Concept
,	O
racetrack	B-General_Concept
memory	I-General_Concept
uses	O
electrical	O
currents	O
to	O
"	O
push	O
"	O
a	O
sequence	O
of	O
magnetic	O
domains	O
through	O
a	O
substrate	O
and	O
past	O
read/write	O
elements	O
.	O
</s>
<s>
Improvements	O
in	O
magnetic	O
detection	O
capabilities	O
,	O
based	O
on	O
the	O
development	O
of	O
spintronic	O
magnetoresistive	O
sensors	O
,	O
allow	O
the	O
use	O
of	O
much	O
smaller	O
magnetic	O
domains	O
to	O
provide	O
far	O
higher	O
bit	B-Device
densities	I-Device
.	O
</s>
<s>
There	O
were	O
two	O
arrangements	O
considered	O
for	O
racetrack	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
A	O
more	O
widely	O
studied	O
arrangement	O
used	O
U-shaped	O
wires	O
arranged	O
vertically	O
over	O
a	O
grid	O
of	O
read/write	B-Device
heads	I-Device
on	O
an	O
underlying	O
substrate	O
.	O
</s>
<s>
This	O
would	O
allow	O
the	O
wires	O
to	O
be	O
much	O
longer	O
without	O
increasing	O
its	O
2D	O
area	O
,	O
although	O
the	O
need	O
to	O
move	O
individual	O
domains	O
further	O
along	O
the	O
wires	O
before	O
they	O
reach	O
the	O
read/write	B-Device
heads	I-Device
results	O
in	O
slower	O
random	O
access	O
times	O
.	O
</s>
<s>
Projections	O
in	O
2008	O
suggested	O
that	O
racetrack	B-General_Concept
memory	I-General_Concept
would	O
offer	O
performance	O
on	O
the	O
order	O
of	O
20-32ns	O
to	O
read	O
or	O
write	O
a	O
random	O
bit	O
.	O
</s>
<s>
This	O
compared	O
to	O
about	O
10,000,000	O
ns	O
for	O
a	O
hard	B-Device
drive	I-Device
,	O
or	O
20-30ns	O
for	O
conventional	O
DRAM	O
.	O
</s>
<s>
Aggregate	O
throughput	O
,	O
with	O
or	O
without	O
the	O
reservoir	O
,	O
would	O
be	O
on	O
the	O
order	O
of	O
250-670Mbit/s	O
for	O
racetrack	B-General_Concept
memory	I-General_Concept
,	O
compared	O
to	O
12800	O
Mbit/s	O
for	O
a	O
single	O
DDR3	O
DRAM	O
,	O
1000	O
Mbit/s	O
for	O
high-performance	O
hard	B-Device
drives	I-Device
,	O
and	O
1000	O
to	O
4000Mbit/s	O
for	O
flash	B-Device
memory	I-Device
devices	O
.	O
</s>
<s>
The	O
only	O
current	O
technology	O
that	O
offered	O
a	O
clear	O
latency	O
benefit	O
over	O
racetrack	B-General_Concept
memory	I-General_Concept
was	O
SRAM	B-Architecture
,	O
on	O
the	O
order	O
of	O
0.2ns	O
,	O
but	O
at	O
a	O
higher	O
cost	O
.	O
</s>
<s>
Racetrack	B-General_Concept
memory	I-General_Concept
is	O
one	O
among	O
several	O
emerging	O
technologies	O
that	O
aim	O
to	O
replace	O
conventional	O
memories	O
such	O
as	O
DRAM	O
and	O
Flash	O
,	O
and	O
potentially	O
offer	O
a	O
universal	B-Device
memory	I-Device
device	O
applicable	O
to	O
a	O
wide	O
variety	O
of	O
roles	O
.	O
</s>
<s>
Other	O
contenders	O
included	O
magnetoresistive	B-General_Concept
random-access	I-General_Concept
memory	I-General_Concept
(	O
MRAM	B-General_Concept
)	O
,	O
phase-change	B-Device
memory	I-Device
(	O
PCRAM	B-Device
)	O
and	O
ferroelectric	O
RAM	O
(	O
FeRAM	O
)	O
.	O
</s>
<s>
Most	O
of	O
these	O
technologies	O
offer	O
densities	O
similar	O
to	O
flash	B-Device
memory	I-Device
,	O
in	O
most	O
cases	O
worse	O
,	O
and	O
their	O
primary	O
advantage	O
is	O
the	O
lack	O
of	O
write-endurance	O
limits	O
like	O
those	O
in	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Field-MRAM	O
offers	O
excellent	O
performance	O
as	O
high	O
as	O
3ns	O
access	O
time	O
,	O
but	O
requires	O
a	O
large	O
25-40F²	O
cell	O
size	O
.	O
</s>
<s>
It	O
might	O
see	O
use	O
as	O
an	O
SRAM	B-Architecture
replacement	O
,	O
but	O
not	O
as	O
a	O
mass	O
storage	O
device	O
.	O
</s>
<s>
The	O
highest	O
densities	O
from	O
any	O
of	O
these	O
devices	O
is	O
offered	O
by	O
PCRAM	B-Device
,	O
with	O
a	O
cell	O
size	O
of	O
about	O
5.8F²	O
,	O
similar	O
to	O
flash	B-Device
memory	I-Device
,	O
as	O
well	O
as	O
fairly	O
good	O
performance	O
around	O
50ns	O
.	O
</s>
<s>
Nevertheless	O
,	O
none	O
of	O
these	O
can	O
come	O
close	O
to	O
competing	O
with	O
racetrack	B-General_Concept
memory	I-General_Concept
in	O
overall	O
terms	O
,	O
especially	O
density	O
.	O
</s>
<s>
For	O
example	O
,	O
50ns	O
allows	O
about	O
five	O
bits	O
to	O
be	O
operated	O
in	O
a	O
racetrack	B-General_Concept
memory	I-General_Concept
device	O
,	O
resulting	O
in	O
an	O
effective	O
cell	O
size	O
of	O
20/5	O
=	O
4F²	O
,	O
easily	O
exceeding	O
the	O
performance-density	O
product	O
of	O
PCM	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
without	O
sacrificing	O
bit	B-Device
density	I-Device
,	O
the	O
same	O
20F²	O
area	O
could	O
fit	O
2.5	O
2-bit	O
8F²	O
alternative	O
memory	O
cells	O
(	O
such	O
as	O
resistive	B-General_Concept
RAM	I-General_Concept
(	O
RRAM	B-General_Concept
)	O
or	O
spin-torque	B-General_Concept
transfer	I-General_Concept
MRAM	I-General_Concept
)	O
,	O
each	O
of	O
which	O
individually	O
operating	O
much	O
faster	O
(	O
~	O
10ns	O
)	O
.	O
</s>
<s>
For	O
instance	O
,	O
hard	B-Device
drives	I-Device
appeared	O
to	O
be	O
reaching	O
theoretical	O
limits	O
around	O
650nm²/bit	O
,	O
defined	O
primarily	O
by	O
the	O
capability	O
to	O
read	O
and	O
write	O
to	O
specific	O
areas	O
of	O
the	O
magnetic	O
surface	O
.	O
</s>
<s>
DRAM	O
has	O
a	O
cell	O
size	O
of	O
about	O
6F²	O
,	O
SRAM	B-Architecture
is	O
much	O
less	O
dense	O
at	O
120F²	O
.	O
</s>
<s>
NAND	O
flash	B-Device
memory	I-Device
is	O
currently	O
the	O
densest	O
form	O
of	O
non-volatile	B-General_Concept
memory	I-General_Concept
in	O
widespread	O
use	O
,	O
with	O
a	O
cell	O
size	O
of	O
about	O
4.5F²	O
,	O
but	O
storing	O
three	O
bits	O
per	O
cell	O
for	O
an	O
effective	O
size	O
of	O
1.5F²	O
.	O
</s>
<s>
NOR	O
flash	B-Device
memory	I-Device
is	O
slightly	O
less	O
dense	O
,	O
at	O
an	O
effective	O
4.75F²	O
,	O
accounting	O
for	O
2-bit	O
operation	O
on	O
a	O
9.5F²	O
cell	O
size	O
.	O
</s>
<s>
This	O
was	O
unexpected	O
,	O
and	O
led	O
to	O
performance	O
equal	O
roughly	O
to	O
that	O
of	O
hard	B-Device
drives	I-Device
,	O
as	O
much	O
as	O
1000	O
times	O
slower	O
than	O
predicted	O
.	O
</s>
<s>
The	O
resulting	O
power	O
draw	O
becomes	O
higher	O
than	O
that	O
required	O
for	O
other	O
memories	O
,	O
e.g.	O
,	O
spin-transfer	O
torque	O
memory	O
(	O
STT-RAM	O
)	O
or	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Another	O
challenge	O
associated	O
with	O
Racetrack	B-General_Concept
memory	I-General_Concept
is	O
the	O
stochastic	O
nature	O
in	O
which	O
the	O
domain	O
walls	O
move	O
,	O
i.e.	O
,	O
they	O
move	O
and	O
stop	O
at	O
random	O
positions	O
.	O
</s>
