<s>
The	O
RISC	B-Device
Single	I-Device
Chip	I-Device
,	O
or	O
RSC	O
,	O
is	O
a	O
single-chip	O
microprocessor	B-Architecture
developed	O
and	O
fabricated	B-Architecture
by	O
International	O
Business	O
Machines	O
(	O
IBM	O
)	O
.	O
</s>
<s>
The	O
RSC	O
was	O
a	O
feature-reduced	O
single-chip	O
implementation	O
of	O
the	O
POWER1	B-General_Concept
,	O
a	O
multi-chip	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
which	O
implemented	O
the	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
It	O
was	O
used	O
in	O
entry-level	O
workstation	B-Device
models	O
of	O
the	O
IBM	B-Device
RS/6000	I-Device
family	O
,	O
such	O
as	O
the	O
Model	O
220	O
and	O
230	O
.	O
</s>
<s>
It	O
has	O
three	O
execution	B-General_Concept
units	I-General_Concept
:	O
a	O
fixed	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
and	O
branch	O
processor	O
;	O
and	O
an	O
8KB	O
unified	O
instruction	O
and	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Like	O
the	O
POWER1	B-General_Concept
,	O
the	O
memory	O
controller	O
and	O
I/O	O
was	O
tightly	O
integrated	O
,	O
with	O
the	O
functional	B-General_Concept
units	I-General_Concept
responsible	O
for	O
the	O
functions	O
:	O
a	O
memory	O
interface	O
unit	O
and	O
sequencer	O
unit	O
;	O
residing	O
on	O
the	O
same	O
die	O
as	O
the	O
processor	O
.	O
</s>
<s>
The	O
RSC	O
contains	O
nine	O
functional	B-General_Concept
units	I-General_Concept
:	O
fixed-point	O
execution	B-General_Concept
unit	I-General_Concept
(	O
FXU	O
)	O
,	O
floating-point	B-Algorithm
execution	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
,	O
memory	O
interface	O
unit	O
(	O
MIU	O
)	O
,	O
sequencer	O
unit	O
,	O
common	O
on-chip	O
processor	O
unit	O
(	O
COP	O
)	O
,	O
instruction	O
fetch	O
unit	O
,	O
and	O
instruction	O
queue	O
and	O
dispatch	O
unit	O
.	O
</s>
<s>
The	O
fixed	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
executes	O
integer	O
instructions	O
,	O
generates	O
addresses	O
in	O
load	O
store	O
operations	O
and	O
some	O
portions	O
of	O
branch	O
instructions	O
.	O
</s>
<s>
It	O
has	O
a	O
three-stage	O
pipeline	B-General_Concept
consisting	O
of	O
decode	O
,	O
execute	O
and	O
writeback	O
stages	O
.	O
</s>
<s>
The	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
executes	O
floating	B-Algorithm
point	I-Algorithm
instructions	O
.	O
</s>
<s>
Unlike	O
the	O
POWER1	B-General_Concept
,	O
the	O
RSC	O
does	O
not	O
have	O
register	B-Architecture
renaming	I-Architecture
capability	O
due	O
to	O
a	O
limited	O
die	O
area	O
in	O
which	O
the	O
unit	O
must	O
fit	O
in	O
.	O
</s>
<s>
To	O
further	O
save	O
die	O
area	O
,	O
the	O
floating	B-Algorithm
point	I-Algorithm
multiply-add	O
array	O
is	O
32	O
bits	O
wide	O
.	O
</s>
<s>
The	O
floating	B-Algorithm
point	I-Algorithm
pipeline	B-General_Concept
consists	O
of	O
four	O
stages	O
,	O
decode	O
,	O
multiply	O
,	O
add	O
and	O
writeback	O
.	O
</s>
<s>
The	O
RSC	O
has	O
an	O
8KB	O
unified	O
cache	B-General_Concept
instead	O
of	O
the	O
separate	O
instruction	O
and	O
large	O
data	B-General_Concept
caches	I-General_Concept
like	O
the	O
POWER1	B-General_Concept
.	O
</s>
<s>
The	O
unified	O
cache	B-General_Concept
is	O
two-way	O
set	O
associative	O
and	O
uses	O
a	O
store-through	O
policy	O
with	O
no	O
reload	O
on	O
a	O
store	O
miss	O
and	O
a	O
least	O
recently	O
used	O
(	O
LRU	O
)	O
replacement	O
policy	O
.	O
</s>
<s>
It	O
has	O
a	O
cache	B-General_Concept
line	O
size	O
of	O
64	O
bytes	O
,	O
and	O
each	O
cache	B-General_Concept
line	O
is	O
sectored	O
into	O
four	O
quadwords	O
(	O
16	O
bytes	O
)	O
,	O
with	O
each	O
quadword	O
given	O
its	O
own	O
valid	O
bit	O
in	O
the	O
cache	B-General_Concept
directory	O
.	O
</s>
<s>
The	O
memory	O
data	O
bus	O
is	O
72	O
bits	O
wide	O
,	O
with	O
64	O
bits	O
used	O
for	O
the	O
data	O
path	O
and	O
8	O
bits	O
used	O
for	O
error	B-Error_Name
correcting	I-Error_Name
code	I-Error_Name
(	O
ECC	O
)	O
.	O
</s>
<s>
Compared	O
to	O
the	O
POWER1	B-General_Concept
,	O
the	O
RSC	O
memory	O
data	O
bus	O
is	O
narrower	O
and	O
uses	O
industry	O
standard	O
SIMMs	B-General_Concept
instead	O
of	O
custom	O
memory	O
cards	O
.	O
</s>
<s>
The	O
RSC	O
contained	O
approximately	O
one	O
million	O
transistors	O
on	O
a	O
14.9mm	O
by	O
15.2mm	O
(	O
226.48mm2	O
)	O
die	O
fabricated	B-Architecture
by	O
IBM	O
in	O
a	O
complementary	B-Device
metal-oxide	I-Device
semiconductor	I-Device
(	O
CMOS	B-Device
)	O
process	B-Architecture
with	O
a	O
minimal	O
feature	O
size	O
of	O
0.8	O
μm	O
and	O
three	O
levels	O
of	O
wiring	O
.	O
</s>
<s>
It	O
is	O
packaged	O
in	O
a	O
36mm	O
by	O
36mm	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
module	O
which	O
had	O
201	O
signal	O
pins	O
.	O
</s>
<s>
It	O
required	O
a	O
3.6	O
volt	O
power	B-Architecture
supply	O
and	O
consumed	O
4	O
watts	O
during	O
operation	O
at	O
33MHz	O
.	O
</s>
