<s>
RISC-V	B-Device
(	O
pronounced	O
"	O
risk-five	O
"	O
,	O
)	O
is	O
an	O
open	O
standard	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
based	O
on	O
established	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
principles	O
.	O
</s>
<s>
Unlike	O
most	O
other	O
ISA	O
designs	O
,	O
RISC-V	B-Device
is	O
provided	O
under	O
royalty-free	O
open-source	O
licenses	O
.	O
</s>
<s>
A	O
number	O
of	O
companies	O
are	O
offering	O
or	O
have	O
announced	O
RISC-V	B-Device
hardware	O
,	O
open	O
source	O
operating	B-General_Concept
systems	I-General_Concept
with	O
RISC-V	B-Device
support	O
are	O
available	O
,	O
and	O
the	O
instruction	B-General_Concept
set	I-General_Concept
is	O
supported	O
in	O
several	O
popular	O
software	B-General_Concept
toolchains	I-General_Concept
.	O
</s>
<s>
As	O
a	O
RISC	B-Architecture
architecture	B-General_Concept
,	O
the	O
RISC-V	B-Device
ISA	O
is	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
Its	O
floating-point	B-Algorithm
instructions	O
use	O
IEEE	O
754	O
floating-point	B-Algorithm
.	O
</s>
<s>
Notable	O
features	O
of	O
the	O
RISC-V	B-Device
ISA	O
include	O
instruction	O
bit	O
field	O
locations	O
chosen	O
to	O
simplify	O
the	O
use	O
of	O
multiplexers	O
in	O
a	O
CPU	O
,	O
a	O
design	O
that	O
is	O
architecturally	O
neutral	O
,	O
and	O
most-significant	O
bits	O
of	O
immediate	O
values	O
placed	O
at	O
a	O
fixed	O
location	O
to	O
speed	O
sign	O
extension	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
is	O
designed	O
for	O
a	O
wide	O
range	O
of	O
uses	O
.	O
</s>
<s>
The	O
base	O
instruction	B-General_Concept
set	I-General_Concept
has	O
a	O
fixed	O
length	O
of	O
32-bit	O
naturally	O
aligned	O
instructions	O
,	O
and	O
the	O
ISA	O
supports	O
variable	O
length	O
extensions	O
where	O
each	O
instruction	O
can	O
be	O
any	O
number	O
of	O
16-bit	B-Device
parcels	O
in	O
length	O
.	O
</s>
<s>
Subsets	O
support	O
small	O
embedded	B-Architecture
systems	I-Architecture
,	O
personal	B-Device
computers	I-Device
,	O
supercomputers	B-Architecture
with	O
vector	B-Operating_System
processors	I-Operating_System
,	O
and	O
warehouse-scale	O
19	O
inch	O
rack-mounted	O
parallel	B-Operating_System
computers	I-Operating_System
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
specification	O
defines	O
32-bit	O
and	O
64-bit	B-Device
address	B-General_Concept
space	I-General_Concept
variants	O
.	O
</s>
<s>
The	O
specification	O
includes	O
a	O
description	O
of	O
a	O
128-bit	O
flat	O
address	B-General_Concept
space	I-General_Concept
variant	O
,	O
as	O
an	O
extrapolation	O
of	O
32	O
and	O
64	B-Device
bit	I-Device
variants	O
,	O
but	O
the	O
128-bit	O
ISA	O
remains	O
"	O
not	O
frozen	O
"	O
intentionally	O
,	O
because	O
there	O
is	O
yet	O
so	O
little	O
practical	O
experience	O
with	O
such	O
large	O
memory	O
systems	O
.	O
</s>
<s>
Unlike	O
other	O
academic	O
designs	O
which	O
are	O
typically	O
optimized	O
only	O
for	O
simplicity	O
of	O
exposition	O
,	O
the	O
designers	O
intended	O
that	O
the	O
RISC-V	B-Device
instruction	B-General_Concept
set	I-General_Concept
be	O
usable	O
for	O
practical	O
computers	O
.	O
</s>
<s>
CPU	B-General_Concept
design	I-General_Concept
requires	O
design	O
expertise	O
in	O
several	O
specialties	O
:	O
electronic	O
digital	O
logic	O
,	O
compilers	B-Language
,	O
and	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
To	O
cover	O
the	O
costs	O
of	O
such	O
a	O
team	O
,	O
commercial	O
vendors	O
of	O
computer	B-General_Concept
designs	I-General_Concept
,	O
such	O
as	O
Arm	B-Architecture
Ltd.	O
,	O
Cortus	O
and	O
MIPS	B-Device
Technologies	O
,	O
charge	O
royalties	O
for	O
the	O
use	O
of	O
their	O
designs	O
,	O
patents	O
and	O
copyrights	O
.	O
</s>
<s>
RISC-V	B-Device
was	O
begun	O
with	O
a	O
goal	O
to	O
make	O
a	O
practical	O
ISA	O
that	O
was	O
open-sourced	O
,	O
usable	O
academically	O
,	O
and	O
deployable	O
in	O
any	O
hardware	O
or	O
software	O
design	O
without	O
royalties	O
.	O
</s>
<s>
The	O
RISC-V	B-Device
authors	O
are	O
academics	O
who	O
have	O
substantial	O
experience	O
in	O
computer	B-General_Concept
design	I-General_Concept
,	O
and	O
the	O
RISC-V	B-Device
ISA	O
is	O
a	O
direct	O
development	O
from	O
a	O
series	O
of	O
academic	O
computer-design	O
projects	O
,	O
especially	O
Berkeley	B-General_Concept
RISC	I-General_Concept
.	O
</s>
<s>
RISC-V	B-Device
was	O
originated	O
in	O
part	O
to	O
aid	O
all	O
such	O
projects	O
.	O
</s>
<s>
To	O
build	O
a	O
large	O
,	O
continuing	O
community	O
of	O
users	O
and	O
thereby	O
accumulate	O
designs	O
and	O
software	O
,	O
the	O
RISC-V	B-Device
ISA	O
designers	O
intentionally	O
support	O
a	O
wide	O
variety	O
of	O
practical	O
use	O
cases	O
:	O
compact	O
,	O
performance	O
,	O
and	O
low-power	O
real-world	O
implementations	O
without	O
over-architecting	O
for	O
a	O
given	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
requirements	O
of	O
a	O
large	O
base	O
of	O
contributors	O
is	O
part	O
of	O
the	O
reason	O
why	O
RISC-V	B-Device
was	O
engineered	O
to	O
address	O
many	O
possible	O
uses	O
.	O
</s>
<s>
The	O
designers	O
 '	O
primary	O
assertion	O
is	O
that	O
the	O
instruction	B-General_Concept
set	I-General_Concept
is	O
the	O
key	O
interface	O
in	O
a	O
computer	O
as	O
it	O
is	O
situated	O
at	O
the	O
interface	O
between	O
the	O
hardware	O
and	O
the	O
software	O
.	O
</s>
<s>
If	O
a	O
good	O
instruction	B-General_Concept
set	I-General_Concept
were	O
open	O
and	O
available	O
for	O
use	O
by	O
all	O
,	O
then	O
it	O
can	O
dramatically	O
reduce	O
the	O
cost	O
of	O
software	O
by	O
enabling	O
far	O
more	O
reuse	O
.	O
</s>
<s>
The	O
designers	O
maintain	O
that	O
new	O
principles	O
are	O
becoming	O
rare	O
in	O
instruction	B-General_Concept
set	I-General_Concept
design	O
,	O
as	O
the	O
most	O
successful	O
designs	O
of	O
the	O
last	O
forty	O
years	O
have	O
grown	O
increasingly	O
similar	O
.	O
</s>
<s>
Of	O
those	O
that	O
failed	O
,	O
most	O
did	O
so	O
because	O
their	O
sponsoring	O
companies	O
were	O
financially	O
unsuccessful	O
,	O
not	O
because	O
the	O
instruction	B-General_Concept
sets	I-General_Concept
were	O
technically	O
poor	O
.	O
</s>
<s>
Thus	O
,	O
a	O
well-designed	O
open	O
instruction	B-General_Concept
set	I-General_Concept
designed	O
using	O
well-established	O
principles	O
should	O
attract	O
long-term	O
support	O
by	O
many	O
vendors	O
.	O
</s>
<s>
RISC-V	B-Device
also	O
encourages	O
academic	O
usage	O
.	O
</s>
<s>
The	O
variable-length	O
ISA	O
provides	O
room	O
for	O
instruction	B-General_Concept
set	I-General_Concept
extensions	O
for	O
both	O
student	O
exercises	O
and	O
research	O
,	O
and	O
the	O
separated	O
privileged	O
instruction	B-General_Concept
set	I-General_Concept
permits	O
research	O
in	O
operating	B-General_Concept
system	I-General_Concept
support	O
without	O
redesigning	O
compilers	B-Language
.	O
</s>
<s>
RISC-V	B-Device
'	O
s	O
open	O
intellectual	O
property	O
paradigm	O
allows	O
derivative	O
designs	O
to	O
be	O
published	O
,	O
reused	O
,	O
and	O
modified	O
.	O
</s>
<s>
The	O
term	O
RISC	B-Architecture
dates	O
from	O
about	O
1980	O
.	O
</s>
<s>
Simple	O
,	O
effective	O
computers	O
have	O
always	O
been	O
of	O
academic	O
interest	O
,	O
and	O
resulted	O
in	O
the	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
DLX	B-Architecture
for	O
the	O
first	O
edition	O
of	O
Computer	B-General_Concept
Architecture	I-General_Concept
:	O
A	O
Quantitative	O
Approach	O
in	O
1990	O
of	O
which	O
David	O
Patterson	O
was	O
a	O
co-author	O
,	O
and	O
he	O
later	O
participated	O
in	O
the	O
RISC-V	B-Device
origination	O
.	O
</s>
<s>
DLX	B-Architecture
was	O
intended	O
for	O
educational	O
use	O
;	O
academics	O
and	O
hobbyists	O
implemented	O
it	O
using	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
,	O
but	O
it	O
was	O
never	O
truly	O
intended	O
for	O
commercial	O
deployment	O
.	O
</s>
<s>
ARM	B-Architecture
CPUs	O
,	O
versions	O
2	O
and	O
earlier	O
,	O
had	O
a	O
public-domain	O
instruction	B-General_Concept
set	I-General_Concept
and	O
are	O
still	O
supported	O
by	O
the	O
GNU	B-Application
Compiler	I-Application
Collection	I-Application
(	O
GCC	B-Application
)	O
,	O
a	O
popular	O
free-software	B-Application
compiler	B-Language
.	O
</s>
<s>
Three	O
open-source	O
cores	B-Architecture
exist	O
for	O
this	O
ISA	O
,	O
but	O
were	O
never	O
manufactured	O
.	O
</s>
<s>
OpenRISC	B-Device
is	O
an	O
open-source	O
ISA	O
based	O
on	O
DLX	B-Architecture
,	O
with	O
associated	O
RISC	B-Architecture
designs	O
,	O
and	O
is	O
fully	O
supported	O
with	O
GCC	B-Application
and	O
Linux	B-Application
implementations	O
,	O
although	O
it	O
too	O
has	O
few	O
commercial	O
implementations	O
.	O
</s>
<s>
David	O
Patterson	O
at	O
Berkeley	O
joined	O
the	O
collaboration	O
as	O
he	O
was	O
the	O
originator	O
of	O
the	O
Berkeley	B-General_Concept
RISC	I-General_Concept
,	O
and	O
the	O
RISC-V	B-Device
is	O
the	O
eponymous	O
fifth	O
generation	O
of	O
his	O
long	O
series	O
of	O
cooperative	O
RISC-based	B-Architecture
research	O
projects	O
.	O
</s>
<s>
At	O
this	O
stage	O
,	O
students	O
provided	O
initial	O
software	O
,	O
simulations	O
,	O
and	O
CPU	B-General_Concept
designs	I-General_Concept
.	O
</s>
<s>
The	O
RISC-V	B-Device
authors	O
and	O
their	O
institution	O
originally	O
sourced	O
the	O
ISA	O
documents	O
and	O
several	O
CPU	B-General_Concept
designs	I-General_Concept
under	O
BSD	B-Operating_System
licenses	I-Operating_System
,	O
which	O
allow	O
derivative	O
works	O
—	O
such	O
as	O
RISC-V	B-Device
chip	B-General_Concept
designs	I-General_Concept
—	O
to	O
be	O
either	O
open	O
and	O
free	O
,	O
or	O
closed	O
and	O
proprietary	O
.	O
</s>
<s>
The	O
ISA	O
specification	O
itself	O
(	O
i.e.	O
,	O
the	O
encoding	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
)	O
was	O
published	O
in	O
2011	O
as	O
open	O
source	O
,	O
with	O
all	O
rights	O
reserved	O
.	O
</s>
<s>
The	O
actual	O
technical	O
report	O
(	O
an	O
expression	O
of	O
the	O
specification	O
)	O
was	O
later	O
placed	O
under	O
a	O
Creative	O
Commons	O
license	O
to	O
permit	O
enhancement	O
by	O
external	O
contributors	O
through	O
the	O
RISC-V	B-Device
Foundation	I-Device
,	O
and	O
later	O
RISC-V	B-Device
International	O
.	O
</s>
<s>
A	O
full	O
history	O
of	O
RISC-V	B-Device
has	O
been	O
published	O
on	O
the	O
RISC-V	B-Device
International	O
website	O
.	O
</s>
<s>
To	O
address	O
this	O
issue	O
,	O
the	O
RISC-V	B-Device
Foundation	I-Device
was	O
formed	O
in	O
2015	O
to	O
own	O
,	O
maintain	O
,	O
and	O
publish	O
intellectual	O
property	O
related	O
to	O
RISC-V	B-Device
'	O
s	O
definition	O
.	O
</s>
<s>
In	O
November	O
2019	O
,	O
the	O
RISC-V	B-Device
Foundation	I-Device
announced	O
that	O
it	O
would	O
relocate	O
to	O
Switzerland	B-Protocol
,	O
citing	O
concerns	O
over	O
U.S.	O
trade	O
regulations	O
.	O
</s>
<s>
As	O
of	O
March	O
2020	O
,	O
the	O
organization	O
was	O
named	O
RISC-V	B-Device
International	O
,	O
a	O
Swiss	O
nonprofit	O
business	O
association	O
.	O
</s>
<s>
,	O
RISC-V	B-Device
International	O
freely	O
publishes	O
the	O
documents	O
defining	O
RISC-V	B-Device
and	O
permits	O
unrestricted	O
use	O
of	O
the	O
ISA	O
for	O
design	O
of	O
software	O
and	O
hardware	O
.	O
</s>
<s>
However	O
,	O
only	O
members	O
of	O
RISC-V	B-Device
International	O
can	O
vote	O
to	O
approve	O
changes	O
,	O
and	O
only	O
member	O
organizations	O
use	O
the	O
trademarked	O
compatibility	O
logo	O
.	O
</s>
<s>
RISC-V	B-Device
has	O
a	O
modular	O
design	O
,	O
consisting	O
of	O
alternative	O
base	O
parts	O
,	O
with	O
added	O
optional	O
extensions	O
.	O
</s>
<s>
The	O
base	O
alone	O
can	O
implement	O
a	O
simplified	O
general-purpose	O
computer	O
,	O
with	O
full	O
software	O
support	O
,	O
including	O
a	O
general-purpose	O
compiler	B-Language
.	O
</s>
<s>
Many	O
RISC-V	B-Device
computers	O
might	O
implement	O
the	O
compressed	B-Architecture
instructions	I-Architecture
extension	O
to	O
reduce	O
power	O
consumption	O
,	O
code	O
size	O
,	O
and	O
memory	O
use	O
.	O
</s>
<s>
There	O
are	O
also	O
future	O
plans	O
to	O
support	O
hypervisors	B-Operating_System
and	O
virtualization	B-General_Concept
.	O
</s>
<s>
Together	O
with	O
a	O
supervisor	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
extension	O
,	O
S	O
,	O
an	O
RVGC	O
defines	O
all	O
instructions	O
needed	O
to	O
conveniently	O
support	O
a	O
general	O
purpose	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
+	O
32-bit	O
RISC-V	B-Device
instruction	O
formats	O
Format	O
Bit	O
31	O
30	O
29	O
28	O
27	O
26	O
25	O
24	O
23	O
22	O
21	O
20	O
19	O
18	O
17	O
16	O
15	O
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Register/register	O
funct7	O
rs2	O
rs1	O
funct3	O
rd	O
opcode	B-Language
Immediate	O
imm[11:0]	O
rs1	O
funct3	O
rd	O
opcode	B-Language
Upper	O
immediate	O
imm[31:12]	O
rd	O
opcode	B-Language
Store	O
imm[11:5]	O
rs2	O
rs1	O
funct3	O
imm[4:0]	O
opcode	B-Language
Branch	O
 [ 12 ] 	O
imm[10:5]	O
rs2	O
rs1	O
funct3	O
imm[4:1]	O
 [ 11 ] 	O
opcode	B-Language
Jump	O
 [ 20 ] 	O
imm[10:1]	O
 [ 11 ] 	O
imm[19:12]	O
rd	O
opcode	B-Language
opcode	B-Language
(	O
7	O
bits	O
)	O
:	O
Partially	O
specifies	O
which	O
of	O
the	O
6	O
types	O
of	O
instruction	O
formats	O
.	O
</s>
<s>
funct7	O
,	O
and	O
funct3	O
(	O
10	O
bits	O
)	O
:	O
These	O
two	O
fields	O
,	O
further	O
than	O
the	O
opcode	B-Language
field	O
,	O
specify	O
the	O
operation	O
to	O
be	O
performed	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
base	O
is	O
specified	O
first	O
,	O
coding	O
for	O
RISC-V	B-Device
,	O
the	O
register	O
bit-width	O
,	O
and	O
the	O
variant	O
;	O
e.g.	O
,	O
or	O
.	O
</s>
<s>
The	O
base	O
,	O
extended	O
integer	O
and	O
floating	B-Algorithm
point	I-Algorithm
calculations	O
,	O
and	O
synchronization	O
primitives	O
for	O
multi-core	O
computing	O
,	O
the	O
base	O
and	O
extensions	O
MAFD	O
,	O
are	O
considered	O
to	O
be	O
necessary	O
for	O
general-purpose	O
computation	O
,	O
and	O
thus	O
have	O
the	O
shorthand	O
,	O
G	O
.	O
</s>
<s>
A	O
small	O
32-bit	O
computer	O
for	O
an	O
embedded	B-Architecture
system	I-Architecture
might	O
be	O
.	O
</s>
<s>
A	O
large	O
64-bit	B-Device
computer	I-Device
might	O
be	O
;	O
i.e.	O
,	O
shorthand	O
for	O
.	O
</s>
<s>
Extensions	O
specific	O
to	O
supervisor	B-Operating_System
privilege	O
level	O
are	O
named	O
in	O
the	O
same	O
way	O
using	O
"	O
S	O
"	O
for	O
prefix	O
.	O
</s>
<s>
Extensions	O
specific	O
to	O
hypervisor	B-Operating_System
level	O
are	O
named	O
using	O
"	O
H	O
"	O
for	O
prefix	O
.	O
</s>
<s>
Supervisor	B-Operating_System
,	O
hypervisor	B-Operating_System
and	O
machine	O
level	O
instruction	B-General_Concept
set	I-General_Concept
extensions	O
are	O
named	O
after	O
less	O
privileged	O
extensions	O
.	O
</s>
<s>
RISC-V	B-Device
developers	O
may	O
create	O
their	O
own	O
non-standard	O
instruction	B-General_Concept
set	I-General_Concept
extensions	O
.	O
</s>
<s>
RISC-V	B-Device
has	O
32	O
(	O
or	O
16	O
in	O
the	O
embedded	O
variant	O
)	O
integer	O
registers	O
,	O
and	O
,	O
when	O
the	O
floating-point	B-Algorithm
extension	O
is	O
implemented	O
,	O
separate	O
32	O
floating-point	B-Algorithm
registers	O
.	O
</s>
<s>
Using	O
the	O
zero	O
register	O
as	O
a	O
placeholder	O
makes	O
for	O
a	O
simpler	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Control	O
and	O
status	B-General_Concept
registers	I-General_Concept
exist	O
,	O
but	O
user-mode	O
programs	O
can	O
access	O
only	O
those	O
used	O
for	O
performance	O
measurement	O
and	O
floating-point	B-Algorithm
management	O
.	O
</s>
<s>
Like	O
many	O
RISC	B-Architecture
designs	O
,	O
RISC-V	B-Device
is	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
:	O
instructions	O
address	O
only	O
registers	O
,	O
with	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
conveying	O
data	O
to	O
and	O
from	O
memory	O
.	O
</s>
<s>
Most	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
include	O
a	O
12-bit	O
offset	O
and	O
two	O
register	O
identifiers	O
.	O
</s>
<s>
Likewise	O
the	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
can	O
access	O
a	O
record-style	O
structure	O
or	O
a	O
memory-mapped	O
I/O	O
device	O
.	O
</s>
<s>
Words	O
,	O
up	O
to	O
the	O
register	O
size	O
,	O
can	O
be	O
accessed	O
with	O
the	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
RISC-V	B-Device
was	O
originally	O
specified	O
as	O
little-endian	O
to	O
resemble	O
other	O
familiar	O
,	O
successful	O
computers	O
,	O
for	O
example	O
,	O
x86	B-Operating_System
.	O
</s>
<s>
For	O
example	O
,	O
the	O
RISC-V	B-Device
instruction	B-General_Concept
set	I-General_Concept
decodes	O
starting	O
at	O
the	O
lowest-addressed	O
byte	O
of	O
the	O
instruction	O
.	O
</s>
<s>
An	O
execution	O
environment	O
interface	O
may	O
allow	O
accessed	O
memory	O
addresses	O
not	O
to	O
be	O
aligned	O
to	O
their	O
word	O
width	O
,	O
but	O
accesses	O
to	O
aligned	O
addresses	O
may	O
be	O
faster	O
;	O
for	O
example	O
,	O
simple	O
CPUs	O
may	O
implement	O
unaligned	O
accesses	O
with	O
slow	O
software	O
emulation	O
driven	O
from	O
an	O
alignment	O
failure	O
interrupt	B-Application
.	O
</s>
<s>
Like	O
many	O
RISC	B-Architecture
instruction	I-Architecture
sets	I-Architecture
(	O
and	O
some	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
instruction	B-General_Concept
sets	I-General_Concept
,	O
such	O
as	O
x86	B-Operating_System
and	O
IBM	B-Application
System/360	I-Application
and	O
its	O
successors	O
through	O
z/Architecture	B-Device
)	O
,	O
RISC-V	B-Device
lacks	O
address-modes	O
that	O
write	O
back	O
to	O
the	O
registers	O
.	O
</s>
<s>
RISC-V	B-Device
manages	O
memory	O
systems	O
that	O
are	O
shared	O
between	O
CPUs	O
or	O
threads	B-Operating_System
by	O
ensuring	O
a	O
thread	B-Operating_System
of	I-Operating_System
execution	I-Operating_System
always	O
sees	O
its	O
memory	O
operations	O
in	O
the	O
programmed	O
order	O
.	O
</s>
<s>
But	O
between	O
threads	B-Operating_System
and	O
I/O	O
devices	O
,	O
RISC-V	B-Device
is	O
simplified	O
:	O
it	O
does	O
n't	O
guarantee	O
the	O
order	O
of	O
memory	O
operations	O
,	O
except	O
by	O
specific	O
instructions	O
,	O
such	O
as	O
.	O
</s>
<s>
A	O
instruction	O
guarantees	O
that	O
the	O
results	O
of	O
predecessor	O
operations	O
are	O
visible	O
to	O
successor	O
operations	O
of	O
other	O
threads	B-Operating_System
or	O
I/O	O
devices	O
.	O
</s>
<s>
One	O
CPU	O
with	O
one	O
thread	B-Operating_System
may	O
decode	O
as	O
.	O
</s>
<s>
Some	O
RISC	B-Architecture
CPUs	O
(	O
such	O
as	O
MIPS	B-Device
,	O
PowerPC	B-Architecture
,	O
DLX	B-Architecture
,	O
and	O
Berkeley	O
's	O
RISC-I	O
)	O
place	O
16	B-Device
bits	I-Device
of	O
offset	O
in	O
the	O
loads	O
and	O
stores	O
.	O
</s>
<s>
They	O
set	O
the	O
upper	O
16	B-Device
bits	I-Device
by	O
a	O
load	O
upper	O
word	O
instruction	O
.	O
</s>
<s>
RISC-V	B-Device
uses	O
a	O
SPARC-like	O
combination	O
of	O
12-bit	O
offsets	O
and	O
20-bit	O
set	O
upper	O
instructions	O
.	O
</s>
<s>
The	O
smaller	O
12-bit	O
offset	O
helps	O
compact	O
,	O
32-bit	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
select	O
two	O
of	O
32	O
registers	O
yet	O
still	O
have	O
enough	O
bits	O
to	O
support	O
RISC-V	B-Device
'	O
s	O
variable-length	O
instruction	O
coding	O
.	O
</s>
<s>
RISC-V	B-Device
handles	O
32-bit	O
constants	O
and	O
addresses	O
with	O
instructions	O
that	O
set	O
the	O
upper	O
20	O
bits	O
of	O
a	O
32-bit	O
register	O
.	O
</s>
<s>
This	O
method	O
is	O
extended	O
to	O
permit	O
position-independent	B-Operating_System
code	I-Operating_System
by	O
adding	O
an	O
instruction	O
,	O
that	O
generates	O
20	O
upper	O
address	O
bits	O
by	O
adding	O
an	O
offset	O
to	O
the	O
program	O
counter	O
and	O
storing	O
the	O
result	O
into	O
a	O
base	O
register	O
.	O
</s>
<s>
In	O
64-bit	B-Device
and	O
128-bit	O
ISAs	O
,	O
and	O
sign-extend	O
the	O
result	O
to	O
get	O
the	O
larger	O
address	O
.	O
</s>
<s>
RISC-V	B-Device
'	O
s	O
subroutine	O
call	O
(	O
jump	O
and	O
link	O
)	O
places	O
its	O
return	B-Language
address	I-Language
in	O
a	O
register	O
.	O
</s>
<s>
This	O
is	O
faster	O
in	O
many	O
computer	B-General_Concept
designs	I-General_Concept
,	O
because	O
it	O
saves	O
a	O
memory	O
access	O
compared	O
to	O
systems	O
that	O
push	O
a	O
return	B-Language
address	I-Language
directly	O
on	O
a	O
stack	O
in	O
memory	O
.	O
</s>
<s>
has	O
a	O
20-bit	O
signed	O
(	O
two	B-General_Concept
's	I-General_Concept
complement	I-General_Concept
)	O
offset	O
.	O
</s>
<s>
If	O
the	O
result	O
is	O
not	O
at	O
a	O
32-bit	O
address	O
(	O
i.e.	O
,	O
evenly	O
divisible	O
by	O
4	O
)	O
,	O
the	O
CPU	O
may	O
force	O
an	O
exception	B-General_Concept
.	O
</s>
<s>
RISC-V	B-Device
CPUs	O
jump	O
to	O
calculated	O
addresses	O
using	O
a	O
jump	O
and	O
link-register	O
,	O
instruction	O
.	O
</s>
<s>
Like	O
them	O
,	O
can	O
be	O
used	O
with	O
the	O
instructions	O
that	O
set	O
the	O
upper	O
20	O
bits	O
of	O
a	O
base	O
register	O
to	O
make	O
32-bit	O
branches	O
,	O
either	O
to	O
an	O
absolute	O
address	O
(	O
using	O
)	O
or	O
a	O
PC-relative	O
one	O
(	O
using	O
for	O
position-independent	B-Operating_System
code	I-Operating_System
)	O
.	O
</s>
<s>
RISC-V	B-Device
recycles	O
and	O
to	O
get	O
unconditional	O
20-bit	O
PC-relative	O
jumps	O
and	O
unconditional	O
register-based	O
12-bit	O
jumps	O
.	O
</s>
<s>
Jumps	O
just	O
make	O
the	O
linkage	O
register	O
0	O
so	O
that	O
no	O
return	B-Language
address	I-Language
is	O
saved	O
.	O
</s>
<s>
RISC-V	B-Device
also	O
recycles	O
to	O
return	O
from	O
a	O
subroutine	O
:	O
To	O
do	O
this	O
,	O
'	O
s	O
base	O
register	O
is	O
set	O
to	O
be	O
the	O
linkage	O
register	O
saved	O
by	O
or	O
.	O
</s>
<s>
'	O
s	O
offset	O
is	O
zero	O
and	O
the	O
linkage	O
register	O
is	O
zero	O
,	O
so	O
that	O
there	O
is	O
no	O
offset	O
,	O
and	O
no	O
return	B-Language
address	I-Language
is	O
saved	O
.	O
</s>
<s>
Like	O
many	O
RISC	B-Architecture
designs	O
,	O
in	O
a	O
subroutine	O
call	O
,	O
a	O
RISC-V	B-Device
compiler	B-Language
must	O
use	O
individual	O
instructions	O
to	O
save	O
registers	O
to	O
the	O
stack	O
at	O
the	O
start	O
,	O
and	O
then	O
restore	O
these	O
from	O
the	O
stack	O
on	O
exit	O
.	O
</s>
<s>
RISC-V	B-Device
has	O
no	O
save	O
multiple	O
or	O
restore	O
multiple	O
register	O
instructions	O
.	O
</s>
<s>
RISC-V	B-Device
has	O
no	O
condition	B-General_Concept
code	I-General_Concept
register	I-General_Concept
or	O
carry	B-Algorithm
bit	I-Algorithm
.	O
</s>
<s>
As	O
a	O
result	O
,	O
predication	B-General_Concept
(	O
the	O
conditional	O
execution	O
of	O
instructions	O
)	O
is	O
not	O
supported	O
.	O
</s>
<s>
The	O
designers	O
claim	O
that	O
very	O
fast	O
,	O
out-of-order	O
CPU	B-General_Concept
designs	I-General_Concept
do	O
predication	B-General_Concept
anyway	O
,	O
by	O
doing	O
the	O
comparison	O
branch	O
and	O
conditional	O
code	O
in	O
parallel	O
,	O
then	O
discarding	O
the	O
unused	O
path	O
's	O
effects	O
.	O
</s>
<s>
They	O
also	O
claim	O
that	O
even	O
in	O
simpler	O
CPUs	O
,	O
predication	B-General_Concept
is	O
less	O
valuable	O
than	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
which	O
can	O
prevent	O
most	O
stalls	O
associated	O
with	O
conditional	O
branches	O
.	O
</s>
<s>
Code	O
without	O
predication	B-General_Concept
is	O
larger	O
,	O
with	O
more	O
branches	O
,	O
but	O
they	O
also	O
claim	O
that	O
a	O
compressed	B-Architecture
instruction	I-Architecture
set	I-Architecture
(	O
such	O
as	O
RISC-V	B-Device
'	O
s	O
set	O
C	O
)	O
solves	O
that	O
problem	O
in	O
most	O
cases	O
.	O
</s>
<s>
Instead	O
,	O
RISC-V	B-Device
has	O
short	O
branches	O
that	O
perform	O
comparisons	O
:	O
equal	O
,	O
not-equal	O
,	O
less-than	O
,	O
unsigned	O
less-than	O
,	O
greater-than	O
or	O
equal	O
and	O
unsigned	O
greater-than	O
or	O
equal	O
.	O
</s>
<s>
Ten	O
comparison-branch	O
operations	O
are	O
implemented	O
with	O
only	O
six	O
instructions	O
,	O
by	O
reversing	O
the	O
order	O
of	O
operands	O
in	O
the	O
assembler	B-Language
.	O
</s>
<s>
Unlike	O
some	O
RISC	B-Architecture
architectures	I-Architecture
,	O
RISC-V	B-Device
does	O
not	O
include	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
,	O
a	O
position	O
after	O
a	O
branch	O
instruction	O
that	O
can	O
be	O
filled	O
with	O
an	O
instruction	O
that	O
is	O
executed	O
whether	O
or	O
not	O
the	O
branch	O
is	O
taken	O
.	O
</s>
<s>
RISC-V	B-Device
omits	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
because	O
it	O
complicates	O
multicycle	O
CPUs	O
,	O
superscalar	O
CPUs	O
,	O
and	O
long	O
pipelines	O
.	O
</s>
<s>
Dynamic	O
branch	B-General_Concept
predictors	I-General_Concept
have	O
succeeded	O
well	O
enough	O
to	O
reduce	O
the	O
need	O
for	O
delayed	O
branches	O
.	O
</s>
<s>
On	O
the	O
first	O
encounter	O
with	O
a	O
branch	O
,	O
RISC-V	B-Device
CPUs	O
should	O
assume	O
that	O
a	O
negative	O
relative	O
branch	O
(	O
i.e.	O
</s>
<s>
Other	O
than	O
this	O
,	O
RISC-V	B-Device
does	O
not	O
require	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
but	O
core	O
implementations	O
are	O
allowed	O
to	O
add	O
it	O
.	O
</s>
<s>
RISC-V	B-Device
segregates	O
math	O
into	O
a	O
minimal	O
set	O
of	O
integer	O
instructions	O
(	O
set	O
I	O
)	O
with	O
add	B-General_Concept
,	I-General_Concept
subtract	I-General_Concept
,	I-General_Concept
shift	I-General_Concept
,	I-General_Concept
bitwise	I-General_Concept
logic	I-General_Concept
and	O
comparing-branches	O
.	O
</s>
<s>
These	O
can	O
simulate	O
most	O
of	O
the	O
other	O
RISC-V	B-Device
instruction	B-General_Concept
sets	I-General_Concept
with	O
software	O
.	O
</s>
<s>
(	O
The	O
atomic	O
instructions	O
are	O
a	O
notable	O
exception	B-General_Concept
.	O
)	O
</s>
<s>
RISC-V	B-Device
integer	O
instructions	O
lacks	O
the	O
count	O
leading	O
zero	O
and	O
bit-field	O
operations	O
normally	O
used	O
to	O
speed	O
software	O
floating-point	B-Algorithm
in	O
a	O
pure-integer	O
processor	O
,	O
However	O
,	O
while	O
nominally	O
in	O
the	O
bit	O
manipulation	O
extension	O
,	O
the	O
ratified	O
Zbb	O
,	O
Zba	O
and	O
Zbs	O
extensions	O
contain	O
further	O
integer	O
instructions	O
including	O
a	O
count	O
leading	O
zero	O
instruction	O
.	O
</s>
<s>
The	O
ISA	O
document	O
recommends	O
that	O
implementors	O
of	O
CPUs	O
and	O
compilers	B-Language
fuse	O
a	O
standardized	O
sequence	O
of	O
high	O
and	O
low	O
multiply	O
and	O
divide	O
instructions	O
to	O
one	O
operation	O
if	O
possible	O
.	O
</s>
<s>
The	O
floating-point	B-Algorithm
instructions	O
(	O
set	O
F	O
)	O
include	O
single-precision	O
arithmetic	O
and	O
also	O
comparison-branches	O
similar	O
to	O
the	O
integer	O
arithmetic	O
.	O
</s>
<s>
It	O
requires	O
an	O
additional	O
set	O
of	O
32	O
floating-point	B-Algorithm
registers	O
.	O
</s>
<s>
The	O
double-precision	O
floating	B-Algorithm
point	I-Algorithm
instructions	O
(	O
set	O
D	O
)	O
generally	O
assume	O
that	O
the	O
floating-point	B-Algorithm
registers	O
are	O
64-bit	B-Device
(	O
i.e.	O
,	O
double-width	O
)	O
,	O
and	O
the	O
F	O
subset	O
is	O
coordinated	O
with	O
the	O
D	O
set	O
.	O
</s>
<s>
A	O
quad-precision	O
128-bit	O
floating-point	B-Algorithm
ISA	O
(	O
Q	O
)	O
is	O
also	O
defined	O
.	O
</s>
<s>
RISC-V	B-Device
computers	O
without	O
floating-point	B-Algorithm
can	O
use	O
a	O
floating-point	B-Algorithm
software	O
library	O
.	O
</s>
<s>
RISC-V	B-Device
does	O
not	O
cause	O
exceptions	B-General_Concept
on	O
arithmetic	O
errors	O
,	O
including	O
overflow	B-Algorithm
,	O
underflow	O
,	O
subnormal	O
,	O
and	O
divide	O
by	O
zero	O
.	O
</s>
<s>
Instead	O
,	O
both	O
integer	O
and	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
produce	O
reasonable	O
default	O
values	O
,	O
and	O
floating-point	B-Algorithm
instructions	O
set	O
status	O
bits	O
.	O
</s>
<s>
The	O
status	O
bits	O
can	O
be	O
tested	O
by	O
an	O
operating	B-General_Concept
system	I-General_Concept
or	O
periodic	O
interrupt	B-Application
.	O
</s>
<s>
RISC-V	B-Device
supports	O
computers	O
that	O
share	O
memory	O
between	O
multiple	O
CPUs	O
and	O
threads	B-Operating_System
.	O
</s>
<s>
RISC-V	B-Device
'	O
s	O
standard	O
memory	O
consistency	O
model	O
is	O
release	B-General_Concept
consistency	I-General_Concept
.	O
</s>
<s>
The	O
base	O
instruction	B-General_Concept
set	I-General_Concept
includes	O
minimal	O
support	O
in	O
the	O
form	O
of	O
a	O
instruction	O
to	O
enforce	O
memory	O
ordering	O
.	O
</s>
<s>
The	O
atomic	O
memory	O
operation	O
extension	O
supports	O
two	O
types	O
of	O
atomic	O
memory	O
operations	O
for	O
release	B-General_Concept
consistency	I-General_Concept
.	O
</s>
<s>
performs	O
a	O
load	O
,	O
and	O
tries	O
to	O
reserve	O
that	O
address	O
for	O
its	O
thread	B-Operating_System
.	O
</s>
<s>
The	O
second	O
group	O
of	O
atomic	O
instructions	O
perform	O
read-modify-write	B-Operating_System
sequences	O
:	O
a	O
load	O
(	O
which	O
is	O
optionally	O
a	O
load-acquire	O
)	O
to	O
a	O
destination	O
register	O
,	O
then	O
an	O
operation	O
between	O
the	O
loaded	O
value	O
and	O
a	O
source	O
register	O
,	O
then	O
a	O
store	O
of	O
the	O
result	O
(	O
which	O
may	O
optionally	O
be	O
a	O
store-release	O
)	O
.	O
</s>
<s>
Making	O
the	O
memory	B-General_Concept
barriers	I-General_Concept
optional	O
permits	O
combining	O
the	O
operations	O
.	O
</s>
<s>
RISC-V	B-Device
defines	O
nine	O
possible	O
operations	O
:	O
swap	O
(	O
use	O
source	O
register	O
value	O
directly	O
)	O
;	O
add	O
;	O
bitwise	O
and	O
,	O
or	O
,	O
and	O
exclusive-or	O
;	O
and	O
signed	O
and	O
unsigned	O
minimum	O
and	O
maximum	O
.	O
</s>
<s>
The	O
IBM	B-Device
System/370	I-Device
and	O
its	O
successors	O
including	O
z/Architecture	B-Device
,	O
and	O
x86	B-Operating_System
,	O
both	O
implement	O
a	O
compare-and-swap	B-Operating_System
(	O
)	O
instruction	O
,	O
which	O
tests	O
and	O
conditionally	O
updates	O
a	O
location	O
in	O
memory	O
:	O
if	O
the	O
location	O
contains	O
an	O
expected	O
old	O
value	O
,	O
replaces	O
it	O
with	O
a	O
given	O
new	O
value	O
;	O
it	O
then	O
returns	O
an	O
indication	O
of	O
whether	O
it	O
made	O
the	O
change	O
.	O
</s>
<s>
The	O
classic	O
problem	O
is	O
that	O
if	O
a	O
thread	B-Operating_System
reads	O
(	O
loads	O
)	O
a	O
value	O
A	O
,	O
calculates	O
a	O
new	O
value	O
C	O
,	O
and	O
then	O
uses	O
(	O
)	O
to	O
replace	O
A	O
with	O
C	O
,	O
it	O
has	O
no	O
way	O
to	O
know	O
whether	O
concurrent	B-Operating_System
activity	O
in	O
another	O
thread	B-Operating_System
has	O
replaced	O
A	O
with	O
some	O
other	O
value	O
B	O
and	O
then	O
restored	O
the	O
A	O
in	O
between	O
.	O
</s>
<s>
In	O
some	O
algorithms	O
(	O
e.g.	O
,	O
ones	O
in	O
which	O
the	O
values	O
in	O
memory	O
are	O
pointers	O
to	O
dynamically	O
allocated	O
blocks	O
)	O
,	O
this	O
ABA	B-Operating_System
problem	I-Operating_System
can	O
lead	O
to	O
incorrect	O
results	O
.	O
</s>
<s>
However	O
,	O
unlike	O
,	O
it	O
can	O
permit	O
livelock	B-Application
,	O
in	O
which	O
two	O
or	O
more	O
threads	B-Operating_System
repeatedly	O
cause	O
each	O
other	O
's	O
instructions	O
to	O
fail	O
.	O
</s>
<s>
RISC-V	B-Device
guarantees	O
forward	O
progress	O
(	O
no	O
livelock	B-Application
)	O
if	O
the	O
code	O
follows	O
rules	O
on	O
the	O
timing	O
and	O
sequence	O
of	O
instructions	O
:	O
1	O
)	O
It	O
must	O
use	O
only	O
the	O
I	O
subset	O
.	O
</s>
<s>
3	O
)	O
It	O
must	O
include	O
no	O
system	O
or	O
fence	B-General_Concept
instructions	I-General_Concept
,	O
or	O
taken	O
backward	O
branches	O
between	O
the	O
and	O
.	O
</s>
<s>
The	O
specification	O
gives	O
an	O
example	O
of	O
how	O
to	O
use	O
the	O
read-modify-write	B-Operating_System
atomic	O
instructions	O
to	O
lock	O
a	O
data	O
structure	O
.	O
</s>
<s>
The	O
standard	O
RISC-V	B-Device
ISA	O
specifies	O
that	O
all	O
instructions	O
are	O
32	O
bits	O
.	O
</s>
<s>
This	O
makes	O
for	O
a	O
particularly	O
simple	O
implementation	O
,	O
but	O
like	O
other	O
RISC	B-Architecture
processors	I-Architecture
with	O
32-bit	O
instruction	O
encoding	O
,	O
results	O
in	O
larger	O
code	O
size	O
than	O
in	O
instruction	B-General_Concept
sets	I-General_Concept
with	O
variable-length	O
instructions	O
.	O
</s>
<s>
To	O
compensate	O
,	O
RISC-V	B-Device
'	O
s	O
32-bit	O
instructions	O
are	O
actually	O
30	O
bits	O
;	O
of	O
the	O
opcode	B-Language
space	O
is	O
reserved	O
for	O
an	O
optional	O
(	O
but	O
recommended	O
)	O
variable-length	O
compressed	B-Architecture
instruction	I-Architecture
set	I-Architecture
,	O
RVC	O
,	O
that	O
includes	O
16-bit	B-Device
instructions	O
.	O
</s>
<s>
Like	O
ARM	B-Architecture
's	O
Thumb	O
and	O
the	O
MIPS16	O
,	O
the	O
compressed	B-Architecture
instructions	I-Architecture
are	O
simply	O
aliases	O
for	O
a	O
subset	O
of	O
the	O
larger	O
instructions	O
.	O
</s>
<s>
Unlike	O
ARM	B-Architecture
's	O
Thumb	O
or	O
the	O
MIPS	B-Device
compressed	O
set	O
,	O
space	O
was	O
reserved	O
from	O
the	O
beginning	O
so	O
there	O
is	O
no	O
separate	O
operating	O
mode	O
.	O
</s>
<s>
Standard	O
and	O
compressed	B-Architecture
instructions	I-Architecture
may	O
be	O
intermixed	O
freely	O
.	O
</s>
<s>
Because	O
(	O
like	O
Thumb-1	O
and	O
MIPS16	O
)	O
the	O
compressed	B-Architecture
instructions	I-Architecture
are	O
simply	O
alternate	O
encodings	O
(	O
aliases	O
)	O
for	O
a	O
selected	O
subset	O
of	O
larger	O
instructions	O
,	O
the	O
compression	O
can	O
be	O
implemented	O
in	O
the	O
assembler	B-Language
,	O
and	O
it	O
is	O
not	O
essential	O
for	O
the	O
compiler	B-Language
to	O
even	O
know	O
about	O
it	O
.	O
</s>
<s>
The	O
prototype	O
code	O
was	O
20%	O
smaller	O
than	O
an	O
x86	B-Operating_System
PC	O
and	O
MIPS	B-Device
compressed	O
code	O
,	O
and	O
2%	O
larger	O
than	O
ARM	B-Architecture
Thumb-2	O
code	O
.	O
</s>
<s>
The	O
researcher	O
intended	O
to	O
reduce	O
the	O
code	O
's	O
binary	O
size	O
for	O
small	O
computers	O
,	O
especially	O
embedded	B-Architecture
computer	I-Architecture
systems	I-Architecture
.	O
</s>
<s>
The	O
prototype	O
included	O
33	O
of	O
the	O
most	O
frequently	O
used	O
instructions	O
,	O
recoded	O
as	O
compact	O
16-bit	B-Device
formats	O
using	O
operation	B-Language
codes	I-Language
previously	O
reserved	O
for	O
the	O
compressed	O
set	O
.	O
</s>
<s>
The	O
compression	O
was	O
done	O
in	O
the	O
assembler	B-Language
,	O
with	O
no	O
changes	O
to	O
the	O
compiler	B-Language
.	O
</s>
<s>
Compressed	B-Architecture
instructions	I-Architecture
omitted	O
fields	O
that	O
are	O
often	O
zero	O
,	O
used	O
small	O
immediate	O
values	O
or	O
accessed	O
subsets	O
(	O
16	O
or	O
8	O
)	O
of	O
the	O
registers	O
.	O
</s>
<s>
Much	O
of	O
the	O
difference	O
in	O
size	O
compared	O
to	O
ARM	B-Architecture
's	O
Thumb	O
set	O
occurred	O
because	O
RISC-V	B-Device
,	O
and	O
the	O
prototype	O
,	O
have	O
no	O
instructions	O
to	O
save	O
and	O
restore	O
multiple	O
registers	O
.	O
</s>
<s>
Instead	O
,	O
the	O
compiler	B-Language
generated	O
conventional	O
instructions	O
that	O
access	O
the	O
stack	O
.	O
</s>
<s>
The	O
prototype	O
RVC	O
assembler	B-Language
then	O
often	O
converted	O
these	O
to	O
compressed	O
forms	O
that	O
were	O
half	O
the	O
size	O
.	O
</s>
<s>
However	O
,	O
this	O
still	O
took	O
more	O
code	O
space	O
than	O
the	O
ARM	B-Architecture
instructions	O
that	O
save	O
and	O
restore	O
multiple	O
registers	O
.	O
</s>
<s>
The	O
researcher	O
proposed	O
to	O
modify	O
the	O
compiler	B-Language
to	O
call	O
library	O
routines	O
to	O
save	O
and	O
restore	O
registers	O
.	O
</s>
<s>
An	O
instruction	B-General_Concept
set	I-General_Concept
for	O
the	O
smallest	O
embedded	O
CPUs	O
(	O
set	O
E	O
)	O
is	O
reduced	O
in	O
other	O
ways	O
:	O
Only	O
16	O
of	O
the	O
32	O
integer	O
registers	O
are	O
supported	O
.	O
</s>
<s>
All	O
current	O
extensions	O
may	O
be	O
used	O
;	O
a	O
floating-point	B-Algorithm
extension	O
to	O
use	O
the	O
integer	O
registers	O
for	O
floating-point	B-Algorithm
values	O
is	O
being	O
considered	O
.	O
</s>
<s>
The	O
privileged	O
instruction	B-General_Concept
set	I-General_Concept
supports	O
only	O
machine	O
mode	O
,	O
user	O
mode	O
and	O
memory	O
schemes	O
that	O
use	O
base-and-bound	O
address	O
relocation	O
.	O
</s>
<s>
Discussion	O
has	O
occurred	O
for	O
a	O
microcontroller	B-Architecture
profile	O
for	O
RISC-V	B-Device
,	O
to	O
ease	O
development	O
of	O
deeply	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
It	O
centers	O
on	O
faster	O
,	O
simple	O
C-language	O
support	O
for	O
interrupts	B-Application
,	O
simplified	O
security	O
modes	O
and	O
a	O
simplified	O
POSIX	O
application	O
binary	O
interface	O
.	O
</s>
<s>
Correspondents	O
have	O
also	O
proposed	O
smaller	O
,	O
non-standard	O
,	O
16-bit	B-Device
RV16E	O
ISAs	O
:	O
Several	O
serious	O
proposals	O
would	O
use	O
the	O
16-bit	B-Device
C	O
instructions	O
with	O
8	O
×	O
16-bit	B-Device
registers	O
.	O
</s>
<s>
An	O
April	O
fools	O
 '	O
joke	O
proposed	O
a	O
very	O
practical	O
arrangement	O
:	O
Utilize	O
16	O
×	O
16-bit	B-Device
integer	O
registers	O
,	O
with	O
the	O
standard	O
EIMC	O
ISAs	O
(	O
including	O
32-bit	O
instructions	O
.	O
)	O
</s>
<s>
The	O
joke	O
was	O
to	O
use	O
bank	B-General_Concept
switching	I-General_Concept
when	O
a	O
32-bit	O
CPU	O
would	O
be	O
clearly	O
superior	O
with	O
the	O
larger	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
RISC-V	B-Device
'	O
s	O
ISA	O
includes	O
a	O
separate	O
privileged	O
instruction	B-General_Concept
set	I-General_Concept
specification	O
.	O
</s>
<s>
,	O
version	O
1.12	O
is	O
ratified	O
by	O
RISC-V	B-Device
International	O
.	O
</s>
<s>
Systems	O
that	O
have	O
only	O
machine	O
mode	O
,	O
perhaps	O
for	O
embedded	B-Architecture
systems	I-Architecture
,	O
</s>
<s>
Systems	O
with	O
both	O
machine	O
mode	O
(	O
for	O
the	O
supervisor	B-Operating_System
)	O
and	O
user-mode	O
to	O
implement	O
operating	B-General_Concept
systems	I-General_Concept
that	O
run	O
the	O
kernel	B-Operating_System
in	O
a	O
privileged	O
mode	O
.	O
</s>
<s>
Systems	O
with	O
machine-mode	O
,	O
hypervisors	B-Operating_System
,	O
multiple	O
supervisors	O
,	O
and	O
user-modes	O
under	O
each	O
supervisor	B-Operating_System
.	O
</s>
<s>
These	O
correspond	O
roughly	O
to	O
systems	O
with	O
up	O
to	O
four	O
rings	O
of	O
privilege	O
and	O
security	O
,	O
at	O
most	O
:	O
machine	O
,	O
hypervisor	B-Operating_System
,	O
supervisor	B-Operating_System
and	O
user	O
.	O
</s>
<s>
The	O
ISA	O
also	O
includes	O
a	O
hypervisor	B-Operating_System
mode	O
that	O
is	O
orthogonal	B-Application
to	O
the	O
user	O
and	O
supervisor	B-Operating_System
modes	O
.	O
</s>
<s>
The	O
basic	O
feature	O
is	O
a	O
configuration	O
bit	O
that	O
either	O
permits	O
supervisor-level	O
code	O
to	O
access	O
hypervisor	B-Operating_System
registers	O
,	O
or	O
causes	O
an	O
interrupt	B-Application
on	O
accesses	O
.	O
</s>
<s>
This	O
bit	O
lets	O
supervisor	B-Operating_System
mode	O
directly	O
handle	O
the	O
hardware	O
needed	O
by	O
a	O
hypervisor	B-Operating_System
.	O
</s>
<s>
This	O
simplifies	O
the	O
implementation	O
of	O
hypervisors	B-Operating_System
that	O
are	O
hosted	O
by	O
an	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
To	O
support	O
non-hosted	O
hypervisors	B-Operating_System
,	O
the	O
bit	O
can	O
cause	O
these	O
accesses	O
to	O
interrupt	B-Application
to	O
a	O
hypervisor	B-Operating_System
.	O
</s>
<s>
The	O
design	O
also	O
simplifies	O
nesting	O
of	O
hypervisors	B-Operating_System
,	O
in	O
which	O
a	O
hypervisor	B-Operating_System
runs	O
under	O
a	O
hypervisor	B-Operating_System
,	O
and	O
if	O
necessary	O
it	O
lets	O
the	O
kernel	B-Operating_System
use	O
hypervisor	B-Operating_System
features	O
within	O
its	O
own	O
kernel	B-Operating_System
code	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
hypervisor	B-Operating_System
form	O
of	O
the	O
ISA	O
supports	O
five	O
modes	O
:	O
machine	O
,	O
supervisor	B-Operating_System
,	O
user	O
,	O
supervisor-under-hypervisor	O
and	O
user-under-hypervisor	O
.	O
</s>
<s>
The	O
privileged	O
instruction	B-General_Concept
set	I-General_Concept
specification	O
explicitly	O
defines	O
hardware	O
threads	B-Operating_System
,	O
or	O
harts	O
.	O
</s>
<s>
Multiple	O
hardware	O
threads	B-Operating_System
are	O
a	O
common	O
practice	O
in	O
more-capable	O
computers	O
.	O
</s>
<s>
When	O
one	O
thread	B-Operating_System
is	O
stalled	O
,	O
waiting	O
for	O
memory	O
,	O
others	O
can	O
often	O
proceed	O
.	O
</s>
<s>
Hardware	O
threads	B-Operating_System
can	O
help	O
make	O
better	O
use	O
of	O
the	O
large	O
number	O
of	O
registers	O
and	O
execution	O
units	O
in	O
fast	O
out-of-order	O
CPUs	O
.	O
</s>
<s>
Finally	O
,	O
hardware	O
threads	B-Operating_System
can	O
be	O
a	O
simple	O
,	O
powerful	O
way	O
to	O
handle	O
interrupts	B-Application
:	O
No	O
saving	O
or	O
restoring	O
of	O
registers	O
is	O
required	O
,	O
simply	O
executing	O
a	O
different	O
hardware	O
thread	B-Operating_System
.	O
</s>
<s>
However	O
,	O
the	O
only	O
hardware	O
thread	B-Operating_System
required	O
in	O
a	O
RISC-V	B-Device
computer	O
is	O
thread	B-Operating_System
zero	O
.	O
</s>
<s>
The	O
existing	O
control	O
and	O
status	B-General_Concept
register	I-General_Concept
definitions	O
support	O
RISC-V	B-Device
'	O
s	O
error	O
and	O
memory	O
exceptions	B-General_Concept
,	O
and	O
a	O
small	O
number	O
of	O
interrupts	B-Application
.	O
</s>
<s>
For	O
systems	O
with	O
more	O
interrupts	B-Application
,	O
the	O
specification	O
also	O
defines	O
an	O
interrupt	B-Application
controller	O
.	O
</s>
<s>
Interrupts	B-Application
always	O
start	O
at	O
the	O
highest-privileged	O
machine	O
level	O
,	O
and	O
the	O
control	O
registers	O
of	O
each	O
level	O
have	O
explicit	O
forwarding	O
bits	O
to	O
route	O
interrupts	B-Application
to	O
less-privileged	O
code	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
hypervisor	B-Operating_System
need	O
not	O
include	O
software	O
that	O
executes	O
on	O
each	O
interrupt	B-Application
to	O
forward	O
an	O
interrupt	B-Application
to	O
an	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
Instead	O
,	O
on	O
set-up	O
,	O
it	O
can	O
set	O
bits	O
to	O
forward	O
the	O
interrupt	B-Application
.	O
</s>
<s>
Physical-only	O
is	O
suited	O
to	O
the	O
simplest	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
There	O
are	O
also	O
three	O
UNIX-style	O
virtual	B-Architecture
memory	I-Architecture
systems	O
for	O
memory	O
cached	O
in	O
mass-storage	O
systems	O
.	O
</s>
<s>
The	O
virtual	B-Architecture
memory	I-Architecture
systems	O
support	O
MMU	B-General_Concept
with	O
three	O
sizes	O
,	O
with	O
addresses	O
sized	O
32	O
,	O
39	O
and	O
48	O
bits	O
.	O
</s>
<s>
All	O
virtual	B-Architecture
memory	I-Architecture
systems	O
support	O
4KiB	O
pages	O
,	O
multilevel	O
page-table	O
trees	O
and	O
use	O
very	O
similar	O
algorithms	O
to	O
walk	O
the	O
page	O
table	O
trees	O
.	O
</s>
<s>
The	O
Zba	O
,	O
Zbb	O
,	O
and	O
Zbs	O
extensions	O
are	O
arguably	O
extensions	O
of	O
the	O
standard	O
I	O
integer	O
instructions	O
:	O
Zba	O
contains	O
instructions	O
to	O
speed	O
up	O
the	O
computation	O
of	O
the	O
addresses	O
of	O
array	O
elements	O
in	O
arrays	O
of	O
datatypes	O
of	O
size	O
2	O
,	O
4	O
,	O
or	O
8	O
bytes	O
(	O
sh1add	O
,	O
sh2add	O
,	O
sh3add	O
)	O
,	O
and	O
for	O
64	B-Device
(	O
and	O
128	O
)	O
bit	O
processors	O
when	O
indexed	O
with	O
unsigned	O
integers	O
(	O
add.uw	O
,	O
sh1add.uw	O
,	O
sh2add.uw	O
,	O
sh3add.uw	O
and	O
slli.uw	O
)	O
.	O
</s>
<s>
pack	O
two	O
words	O
,	O
bytes	O
or	O
halfwords	O
in	O
one	O
register	O
,	O
CRC	O
instructions	O
,	O
bit-matrix	O
operations	O
(	O
RV64	O
only	O
)	O
,	O
conditional	O
mix	O
,	O
conditional	B-General_Concept
move	I-General_Concept
,	O
funnel	O
shifts	O
.	O
</s>
<s>
The	O
criteria	O
for	O
inclusion	O
documented	O
in	O
the	O
draft	O
were	O
compliant	O
with	O
RV5	O
philosophies	O
and	O
ISA	O
formats	O
,	O
substantial	O
improvements	O
in	O
code	O
density	O
or	O
speed	O
(	O
i.e.	O
,	O
at	O
least	O
a	O
3-for-1	O
reduction	O
in	O
instructions	O
)	O
,	O
and	O
substantial	O
real-world	O
applications	O
,	O
including	O
preexisting	O
compiler	B-Language
support	O
.	O
</s>
<s>
Packed-SIMD	O
instructions	O
are	O
widely	O
used	O
by	O
commercial	O
CPUs	O
to	O
inexpensively	O
accelerate	O
multimedia	O
and	O
other	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
For	O
simple	O
,	O
cost-reduced	O
RISC-V	B-Device
systems	O
,	O
the	O
base	O
ISA	O
's	O
specification	O
proposed	O
to	O
use	O
the	O
floating-point	B-Algorithm
registers	O
 '	O
bits	O
to	O
perform	O
parallel	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
sub-word	O
arithmetic	O
.	O
</s>
<s>
The	O
proposal	O
lacked	O
instruction	O
formats	O
and	O
a	O
license	O
assignment	O
to	O
RISC-V	B-Device
International	O
,	O
but	O
it	O
was	O
reviewed	O
by	O
the	O
mailing	O
list	O
.	O
</s>
<s>
Some	O
unpopular	O
parts	O
of	O
this	O
proposal	O
were	O
that	O
it	O
added	O
a	O
condition	O
code	O
,	O
the	O
first	O
in	O
a	O
RISC-V	B-Device
design	O
,	O
linked	O
adjacent	O
registers	O
(	O
also	O
a	O
first	O
)	O
,	O
and	O
has	O
a	O
loop	O
counter	O
that	O
can	O
be	O
difficult	O
to	O
implement	O
in	O
some	O
microarchitectures	B-General_Concept
.	O
</s>
<s>
The	O
proposed	O
vector-processing	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
may	O
make	O
the	O
packed	O
SIMD	B-Device
set	O
obsolete	O
.	O
</s>
<s>
However	O
,	O
a	O
true	O
vector	B-Operating_System
coprocessor	I-Operating_System
could	O
execute	O
the	O
same	O
code	O
with	O
higher	O
performance	O
.	O
</s>
<s>
It	O
is	O
a	O
conservative	O
,	O
flexible	O
design	O
of	O
a	O
general-purpose	O
mixed-precision	O
vector	B-Operating_System
processor	I-Operating_System
,	O
suitable	O
to	O
execute	O
compute	B-Operating_System
kernels	I-Operating_System
.	O
</s>
<s>
In	O
contrast	O
,	O
short-vector	O
SIMD	B-Device
extensions	O
are	O
less	O
convenient	O
.	O
</s>
<s>
These	O
are	O
used	O
in	O
x86	B-Operating_System
,	O
ARM	B-Architecture
and	O
PA-RISC	B-Device
.	O
</s>
<s>
In	O
these	O
,	O
a	O
change	O
in	O
word-width	O
forces	O
a	O
change	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
to	O
expand	O
the	O
vector	O
registers	O
(	O
in	O
the	O
case	O
of	O
x86	B-Operating_System
,	O
from	O
64-bit	B-Device
MMX	B-Architecture
registers	O
to	O
128-bit	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	O
)	O
,	O
to	O
256-bit	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	O
)	O
,	O
and	O
AVX-512	B-General_Concept
)	O
.	O
</s>
<s>
The	O
result	O
is	O
a	O
growing	O
instruction	B-General_Concept
set	I-General_Concept
,	O
and	O
a	O
need	O
to	O
port	O
working	O
code	O
to	O
the	O
new	O
instructions	O
.	O
</s>
<s>
In	O
the	O
RISC-V	B-Device
vector	O
ISA	O
,	O
rather	O
than	O
fix	O
the	O
vector	O
length	O
in	O
the	O
architecture	B-General_Concept
,	O
instructions	O
(	O
,	O
,	O
and	O
)	O
are	O
available	O
which	O
take	O
a	O
requested	O
size	O
and	O
sets	O
the	O
vector	O
length	O
to	O
the	O
minimum	O
of	O
the	O
hardware	O
limit	O
and	O
the	O
requested	O
size	O
.	O
</s>
<s>
So	O
,	O
the	O
RISC-V	B-Device
proposal	O
is	O
more	O
like	O
a	O
Cray	B-Device
's	O
long-vector	O
design	O
or	O
ARM	B-Architecture
's	O
Scalable	O
Vector	O
Extension	O
.	O
</s>
<s>
(	O
Added	O
hardware	O
limits	O
may	O
also	O
exist	O
,	O
which	O
in	O
turn	O
may	O
permit	O
SIMD-style	O
implementations	O
.	O
)	O
</s>
<s>
Outside	O
of	O
vector	O
loops	O
,	O
the	O
application	O
can	O
zero	O
the	O
number	O
of	O
requested	O
vector	O
registers	O
,	O
saving	O
the	O
operating	B-General_Concept
system	I-General_Concept
the	O
work	O
of	O
preserving	O
them	O
on	O
context	B-Operating_System
switches	I-Operating_System
.	O
</s>
<s>
To	O
achieve	O
this	O
flexibility	O
,	O
the	O
instruction	B-General_Concept
set	I-General_Concept
is	O
likely	O
to	O
use	O
variable-width	O
data	O
paths	O
and	O
variable-type	O
operations	O
using	O
polymorphic	O
overloading	O
.	O
</s>
<s>
The	O
plan	O
is	O
that	O
these	O
can	O
reduce	O
the	O
size	O
and	O
complexity	O
of	O
the	O
ISA	O
and	O
compiler	B-Language
.	O
</s>
<s>
Recent	O
experimental	O
vector	B-Operating_System
processors	I-Operating_System
with	O
variable-width	O
data	O
paths	O
also	O
show	O
profitable	O
increases	O
in	O
operations	O
per	O
:	O
second	O
(	O
speed	O
)	O
,	O
area	O
(	O
lower	O
cost	O
)	O
,	O
and	O
watt	O
(	O
longer	O
battery	O
life	O
)	O
.	O
</s>
<s>
Unlike	O
a	O
typical	O
modern	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
,	O
there	O
are	O
no	O
plans	O
to	O
provide	O
special	O
hardware	O
to	O
support	O
branch	B-General_Concept
predication	I-General_Concept
.	O
</s>
<s>
Instead	O
,	O
lower	O
cost	O
compiler-based	O
predication	B-General_Concept
will	O
be	O
used	O
.	O
</s>
<s>
There	O
is	O
a	O
preliminary	O
specification	O
for	O
RISC-V	B-Device
'	O
s	O
hardware-assisted	O
debugger	B-Application
.	O
</s>
<s>
The	O
debugger	B-Application
will	O
use	O
a	O
transport	O
system	O
such	O
as	O
Joint	O
Test	O
Action	O
Group	O
(	O
JTAG	O
)	O
or	O
Universal	O
Serial	O
Bus	O
(	O
USB	B-Protocol
)	O
to	O
access	O
debug	O
registers	O
.	O
</s>
<s>
Correspondents	O
claim	O
that	O
similar	O
systems	O
are	O
used	O
by	O
Freescale	O
's	O
background	B-Application
debug	I-Application
mode	I-Application
interface	I-Application
(	O
BDM	O
)	O
for	O
some	O
CPUs	O
,	O
ARM	B-Architecture
,	O
OpenRISC	B-Device
,	O
and	O
Aeroflex	O
's	O
LEON	B-General_Concept
.	O
</s>
<s>
In	O
instruction	O
feeding	O
,	O
the	O
CPU	O
will	O
process	O
a	O
debug	O
exception	B-General_Concept
to	O
execute	O
individual	O
instructions	O
written	O
to	O
a	O
register	O
.	O
</s>
<s>
Instruction	O
feeding	O
lets	O
the	O
debugger	B-Application
access	O
the	O
computer	O
exactly	O
as	O
software	O
would	O
.	O
</s>
<s>
This	O
was	O
said	O
to	O
be	O
especially	O
apt	O
for	O
RISC-V	B-Device
because	O
it	O
is	O
designed	O
explicitly	O
for	O
many	O
types	O
of	O
computers	O
.	O
</s>
<s>
The	O
data-passing	O
register	O
allows	O
a	O
debugger	B-Application
to	O
write	O
a	O
data-movement	O
loop	O
to	O
RAM	O
,	O
and	O
then	O
execute	O
the	O
loop	O
to	O
move	O
data	O
into	O
or	O
out	O
of	O
the	O
computer	O
at	O
a	O
speed	O
near	O
the	O
maximum	O
speed	O
of	O
the	O
debug	O
system	O
's	O
data	O
channel	O
.	O
</s>
<s>
Correspondents	O
say	O
that	O
similar	O
systems	O
are	O
used	O
by	O
MIPS	B-Device
Technologies	O
MIPS	B-Device
,	O
Intel	B-Device
Quark	I-Device
,	O
Tensilica	B-General_Concept
's	O
Xtensa	O
,	O
and	O
for	O
Freescale	O
Power	B-Architecture
ISA	I-Architecture
CPUs	O
 '	O
background	B-Application
debug	I-Application
mode	I-Application
interface	I-Application
(	O
BDM	O
)	O
.	O
</s>
<s>
The	O
RISC-V	B-Device
organization	O
maintains	O
a	O
list	O
of	O
RISC-V	B-Device
CPU	O
and	O
SoC	O
implementations	O
.	O
</s>
<s>
Allwinner	B-Architecture
Technology	I-Architecture
has	O
implemented	O
the	O
XuanTie	O
C906	O
CPU	O
into	O
their	O
D1	O
Application	O
Processor	O
.	O
</s>
<s>
Andes	O
Technology	O
Corporation	O
,	O
a	O
Founding	O
Premier	O
member	O
of	O
RISC-V	B-Device
International	O
.	O
</s>
<s>
Its	O
RISC-V	B-Device
CPU	O
families	O
range	O
from	O
tiny	O
32-bit	O
cores	B-Architecture
to	O
advanced	O
64-bit	B-Device
cores	B-Architecture
with	O
DSP	O
,	O
FPU	O
,	O
Vector	O
,	O
superscalar	O
,	O
and/or	O
multicore	O
capabilities	O
.	O
</s>
<s>
Bouffalo	O
Lab	O
has	O
a	O
series	O
of	O
MCUs	O
based	O
on	O
RISC-V	B-Device
(	O
RV32IMACF	O
,	O
BL60x/BL70x	O
series	O
)	O
.	O
</s>
<s>
CloudBEAR	O
is	O
a	O
processor	O
IP	O
company	O
that	O
develops	O
its	O
own	O
RISC-V	B-Device
cores	B-Architecture
for	O
a	O
range	O
of	O
applications	O
.	O
</s>
<s>
Codasip	O
,	O
a	O
founding	O
member	O
of	O
RISC-V	B-Device
International	O
,	O
has	O
developed	O
a	O
range	O
of	O
low-power	O
embedded	O
,	O
high-performance	O
embedded	O
and	O
application	O
processor	O
cores	B-Architecture
.	O
</s>
<s>
Cortus	O
,	O
an	O
original	O
founding	O
Platinum	O
member	O
of	O
the	O
RISC-V	B-Device
foundation	I-Device
and	O
the	O
RISC-V	B-Device
International	O
,	O
has	O
a	O
number	O
of	O
RISC-V	B-Device
implementations	O
.	O
</s>
<s>
Cortus	O
offers	O
ASIC	O
design	O
services	O
using	O
its	O
large	O
IP	O
portfolio	O
including	O
RISC-V	B-Device
32/64	O
-bit	O
processors	O
from	O
low-end	O
to	O
very	O
high	O
performance	O
RISC-V	B-Device
OoO	O
processors	O
,	O
digital	O
,	O
analog	O
,	O
RF	O
,	O
security	O
and	O
a	O
complete	O
IDE/toolchain/debug	O
eco-system	O
.	O
</s>
<s>
Espressif	O
added	O
a	O
RISC-V	B-Device
ULP	O
coprocessor	O
to	O
their	O
ESP32-S2	O
microcontroller	B-Architecture
.	O
</s>
<s>
In	O
November	O
2020	O
Espressif	O
announced	O
their	O
ESP32-C3	O
,	O
a	O
single-core	O
,	O
32-bit	O
,	O
RISC-V	B-Device
(	O
RV32IMC	O
)	O
based	O
MCU	O
.	O
</s>
<s>
Fraunhofer	O
IPMS	O
was	O
the	O
first	O
organization	O
to	O
develop	O
a	O
RISC-V	B-Device
core	O
that	O
can	O
meet	O
functional	O
safety	O
requirements	O
.	O
</s>
<s>
The	O
IP	B-Architecture
Core	I-Architecture
EMSA5	O
is	O
a	O
32-bit	O
processor	O
with	O
a	O
five-stage	O
pipeline	O
and	O
is	O
available	O
as	O
a	O
General	O
Purpose	O
variant	O
(	O
EMSA5-GP	O
)	O
and	O
as	O
a	O
Safety	O
variant	O
(	O
EMSA5-FS	O
)	O
that	O
can	O
meet	O
an	O
ISO	O
26262	O
Automotive	O
Safety	O
Integrity	O
Level-D	O
standard	O
.	O
</s>
<s>
GigaDevice	O
has	O
a	O
series	O
of	O
MCUs	O
based	O
on	O
RISC-V	B-Device
(	O
RV32IMAC	O
,	O
GD32V	O
series	O
)	O
,	O
with	O
one	O
of	O
them	O
used	O
on	O
the	O
Longan	O
Nano	O
board	O
produced	O
by	O
a	O
Chinese	O
electronic	O
company	O
Sipeed	O
.	O
</s>
<s>
GreenWaves	O
Technologies	O
announced	O
the	O
availability	O
of	O
GAP8	O
,	O
a	O
32-bit	O
1	O
controller	O
plus	O
8	O
compute	O
cores	B-Architecture
,	O
32-bit	O
SoC	O
(	O
RV32IMC	O
)	O
and	O
developer	O
board	O
in	O
February	O
2018	O
.	O
</s>
<s>
RISC-V	B-Device
cores	B-Architecture
from	O
FPGA	B-Architecture
Cores	B-Architecture
.	O
</s>
<s>
System	B-Architecture
On	I-Architecture
Chip	I-Architecture
,	O
including	O
RISC-V	B-Device
cores	B-Architecture
,	O
defined	O
by	O
C++	O
.	O
</s>
<s>
Micro	O
Magic	O
Inc	O
.	O
announced	O
the	O
world	O
's	O
fastest	O
64-bit	B-Device
RISC-V	B-Device
core	O
achieving	O
5GHz	O
and	O
13,000	O
CoreMarks	O
in	O
October	O
2020	O
.	O
</s>
<s>
MIPS	B-Device
pivoted	O
to	O
developing	O
RISC-V	B-Device
cores	B-Architecture
in	O
2021	O
.	O
</s>
<s>
Seagate	O
,	O
in	O
December	O
2020	O
announced	O
that	O
it	O
had	O
developed	O
two	O
RISC-V	B-Device
general-purpose	O
cores	B-Architecture
for	O
use	O
in	O
upcoming	O
controllers	O
for	O
its	O
storage	O
devices	O
.	O
</s>
<s>
SiFive	O
,	O
a	O
company	O
established	O
specifically	O
for	O
developing	O
RISC-V	B-Device
hardware	O
,	O
has	O
processor	O
models	O
released	O
in	O
2017	O
.	O
</s>
<s>
These	O
include	O
a	O
quad-core	O
,	O
64-bit	B-Device
(	O
RV64GC	O
)	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
capable	O
of	O
running	O
general-purpose	B-General_Concept
operating	I-General_Concept
systems	I-General_Concept
such	O
as	O
Linux	B-Application
.	O
</s>
<s>
StarFive	O
,	O
an	O
offshoot	O
of	O
SiFive	O
based	O
in	O
China	O
,	O
offers	O
two	O
RISC-V	B-Device
implementationsone	O
for	O
big	O
data	O
applications	O
and	O
the	O
other	O
for	O
computational	O
storage	O
.	O
</s>
<s>
Syntacore	O
,	O
a	O
founding	O
member	O
of	O
RISC-V	B-Device
International	O
and	O
one	O
of	O
the	O
first	O
commercial	O
RISC-V	B-Device
IP	O
vendors	O
,	O
develops	O
and	O
licenses	O
family	O
of	O
RISC-V	B-Device
IP	O
since	O
2015	O
.	O
,	O
product	O
line	O
includes	O
eight	O
32	O
-	O
and	O
64-bit	B-Device
cores	B-Architecture
,	O
including	O
open-source	O
SCR1	O
MCU	O
core	O
(	O
RV32I/E	O
 [ MC ] 	O
)	O
.	O
</s>
<s>
Codasip	O
and	O
UltraSoC	O
have	O
developed	O
fully	O
supported	O
intellectual	O
property	O
for	O
RISC-V	B-Device
embedded	O
SOCs	O
that	O
combine	O
Codasip	O
's	O
RISC-V	B-Device
cores	B-Architecture
and	O
other	O
IP	O
with	O
UltraSoC	O
's	O
debug	O
,	O
optimization	O
and	O
analytics	O
.	O
</s>
<s>
As	O
of	O
2020	O
,	O
the	O
Indian	O
defence	O
and	O
strategic	O
sector	O
started	O
using	O
the	O
64-bit	B-Device
RISC-V	B-Device
based	O
100-350MHz	O
Risecreek	O
processor	O
developed	O
by	O
IIT-Madras	O
which	O
is	O
fabricated	O
by	O
Intel	O
with	O
22nm	O
FinFET	O
process	O
.	O
</s>
<s>
ASTC	O
developed	O
a	O
RISC-V	B-Device
CPU	O
for	O
embedded	O
ICs	O
.	O
</s>
<s>
Centre	O
for	O
Development	O
of	O
Advanced	O
Computing	O
(	O
C-DAC	O
)	O
in	O
India	O
is	O
developing	O
a	O
single	O
core	O
32-bit	O
in-order	O
,	O
a	O
single	O
core	O
64-bit	B-Device
in-order	O
and	O
three	O
out-of-order	O
single	O
,	O
dual	O
and	O
quad-core	O
RISC-V	B-Device
processor	O
under	O
VEGA	B-General_Concept
Microprocessors	I-General_Concept
series	O
.	O
</s>
<s>
Cobham	O
Gaisler	O
NOEL-V	O
64-bit	B-Device
.	O
</s>
<s>
Computer	O
Laboratory	O
,	O
University	O
of	O
Cambridge	O
,	O
in	O
collaboration	O
with	O
the	O
FreeBSD	B-Operating_System
Project	I-Operating_System
,	O
has	O
ported	O
that	O
operating	B-General_Concept
system	I-General_Concept
to	O
64-bit	B-Device
RISC-V	B-Device
to	O
use	O
as	O
a	O
hardware-software	O
research	O
platform	O
.	O
</s>
<s>
Esperanto	O
Technologies	O
announced	O
that	O
they	O
are	O
developing	O
three	O
RISC-V	B-Device
based	O
processors	O
:	O
the	O
ET-Maxion	O
high-performance	O
core	O
,	O
ET-Minion	O
energy-efficient	O
core	O
,	O
and	O
ET-Graphics	O
graphics	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
ETH	O
Zurich	O
and	O
the	O
University	O
of	O
Bologna	O
have	O
cooperatively	O
developed	O
the	O
open-source	O
RISC-V	B-Device
PULPino	O
processor	O
as	O
part	O
of	O
the	O
Parallel	O
Ultra-Low	O
Power	O
(	O
PULP	O
)	O
project	O
for	O
energy-efficient	O
IoT	B-Operating_System
computing	O
.	O
</s>
<s>
European	B-General_Concept
Processor	I-General_Concept
Initiative	I-General_Concept
(	O
EPI	B-General_Concept
)	O
,	O
RISC-V	B-Device
Accelerator	O
Stream	O
.	O
</s>
<s>
Reconfigurable	O
Intelligent	O
Systems	O
Engineering	O
Group	O
(	O
RISE	O
)	O
of	O
IIT-Madras	O
is	O
developing	O
six	O
Shakti	B-General_Concept
series	O
RISC-V	B-Device
open-source	O
CPU	B-General_Concept
designs	I-General_Concept
for	O
six	O
distinct	O
uses	O
,	O
from	O
a	O
small	O
32-bit	O
CPU	O
for	O
the	B-Operating_System
Internet	I-Operating_System
of	I-Operating_System
Things	I-Operating_System
(	O
IoT	B-Operating_System
)	O
to	O
large	O
,	O
64-bit	B-Device
CPUs	I-Device
designed	O
for	O
warehouse-scale	O
computers	O
such	O
as	O
server	B-Operating_System
farms	I-Operating_System
based	O
on	O
RapidIO	B-General_Concept
and	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
technologies	O
.	O
</s>
<s>
lowRISC	O
is	O
a	O
non	O
profit	O
project	O
to	O
implement	O
a	O
fully	O
open-source	O
hardware	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
based	O
on	O
the	O
64-bit	B-Device
RISC-V	B-Device
ISA	O
.	O
</s>
<s>
Nvidia	O
plans	O
to	O
use	O
RISC-V	B-Device
to	O
replace	O
their	O
Falcon	O
processor	O
on	O
their	O
GeForce	B-Application
graphics	O
cards	O
.	O
</s>
<s>
RV64X	O
consortium	O
is	O
working	O
on	O
a	O
set	O
of	O
graphics	O
extensions	O
to	O
RISC-V	B-Device
and	O
has	O
announced	O
that	O
they	O
are	O
developing	O
an	O
open	O
source	O
RISC-V	B-Device
core	O
with	O
a	O
GPU	B-Architecture
unit	O
.	O
</s>
<s>
SiFive	O
announced	O
their	O
first	O
RISC-V	B-Device
out-of-order	O
high	O
performance	O
CPU	O
core	O
,	O
the	O
U8	O
Series	O
Processor	O
IP	O
.	O
</s>
<s>
Ventana	O
revealed	O
they	O
are	O
developing	O
high	O
performance	O
RISC-V	B-Device
CPU	O
IP	O
and	O
chiplet	O
technology	O
targeting	O
data	O
center	O
applications	O
.	O
</s>
<s>
Many	O
open-sourced	O
RISC-V	B-Device
CPU	B-General_Concept
designs	I-General_Concept
exist	O
,	O
including	O
:	O
</s>
<s>
These	O
are	O
implemented	O
in	O
a	O
unique	O
hardware	B-General_Concept
design	I-General_Concept
language	O
,	O
Chisel	O
,	O
and	O
some	O
are	O
named	O
for	O
famous	O
train	O
engines	O
:	O
</s>
<s>
64-bit	B-Device
Rocket	O
.	O
</s>
<s>
The	O
64-bit	B-Device
Berkeley	O
Out	O
of	O
Order	O
Machine	O
(	O
BOOM	O
)	O
.	O
</s>
<s>
The	O
Berkeley	O
Out-of-Order	O
Machine	O
(	O
BOOM	O
)	O
is	O
a	O
synthesizable	O
and	O
parameterizable	O
open	O
source	O
RV64GC	O
RISC-V	B-Device
core	O
written	O
in	O
the	O
Chisel	O
hardware	O
construction	O
language	O
.	O
</s>
<s>
BOOM	O
uses	O
much	O
of	O
the	O
infrastructure	O
created	O
for	O
Rocket	O
,	O
and	O
may	O
be	O
usable	O
for	O
personal	O
,	O
supercomputer	B-Architecture
,	O
and	O
warehouse-scale	O
computers	O
.	O
</s>
<s>
Five	O
32-bit	O
Sodor	O
CPU	B-General_Concept
designs	I-General_Concept
from	O
Berkeley	O
,	O
designed	O
for	O
student	O
projects	O
.	O
</s>
<s>
picorv32	O
by	O
Claire	O
Wolf	O
,	O
a	O
32-bit	O
microcontroller	B-Architecture
unit	I-Architecture
(	O
MCU	O
)	O
class	O
RV32IMC	O
implementation	O
in	O
Verilog	B-Language
.	O
</s>
<s>
scr1	O
from	O
Syntacore	O
,	O
a	O
32-bit	O
microcontroller	B-Architecture
unit	I-Architecture
(	O
MCU	O
)	O
class	O
RV32IMC	O
implementation	O
in	O
Verilog	B-Language
.	O
</s>
<s>
SERV	O
is	O
a	O
physically	O
small	O
,	O
validated	O
bit-serial	O
RV32I	O
core	O
in	O
Verilog	B-Language
.	O
</s>
<s>
An	O
FPGA	B-Architecture
implementation	O
was	O
354	O
lookup	O
tables	O
(	O
LUTs	O
)	O
and	O
345	O
flip-flops	B-General_Concept
,	O
running	O
at	O
1.5	O
MIPS	B-Device
,	O
In	O
a	O
130nm-node	O
ASIC	O
,	O
it	O
was	O
0.04mm2	O
and	O
a	O
high-end	O
FPGA	B-Architecture
could	O
hold	O
6,000	O
cores	B-Architecture
.	O
</s>
<s>
The	O
cores	B-Architecture
in	O
PULPino	O
implement	O
a	O
simple	O
RV32IMC	O
ISA	O
for	O
microcontrollers	B-Architecture
(	O
Zero-Riscy	O
)	O
or	O
a	O
more	O
powerful	O
RV32IMFC	O
ISA	O
with	O
custom	O
DSP	O
extensions	O
for	O
embedded	O
signal	O
processing	O
.	O
</s>
<s>
In	O
December	O
2019	O
,	O
WD	O
announced	O
the	O
SweRV	O
EH2	O
an	O
in-order	O
core	O
with	O
two	O
hardware	O
threads	B-Operating_System
and	O
a	O
nine-stage	O
pipeline	O
and	O
the	O
SweRV	O
EL2	O
a	O
single	O
issue	O
core	O
with	O
a	O
4-stage	O
pipeline	O
WD	O
plans	O
to	O
use	O
SweRV	O
based	O
processors	O
in	O
their	O
flash	O
controllers	O
and	O
SSDs	O
,	O
and	O
released	O
it	O
as	O
open-source	O
to	O
third	O
parties	O
in	O
January	O
2019	O
.	O
</s>
<s>
NEORV32	O
by	O
Stephan	O
Nolting	O
,	O
a	O
highly-configurable	O
32-bit	O
microcontroller	B-Architecture
unit	I-Architecture
(	O
MCU	O
)	O
class	O
RV32[I/E]MACUX_Zbb_Zfinx_Zicsr_Zifencei	O
CPU	O
with	O
on-chip	O
debugger	B-Application
support	O
written	O
in	O
platform-independent	O
VHDL	B-Language
.	O
</s>
<s>
The	O
project	O
includes	O
a	O
microcontroller-like	O
SoC	O
that	O
already	O
includes	O
common	O
modules	O
like	O
UART	O
,	O
timers	O
,	O
SPI	O
,	O
TWI	O
,	O
a	O
TRNG	O
and	O
embedded	O
memories	O
.	O
</s>
<s>
Alibaba	O
Group	O
,	O
in	O
July	O
2019	O
announced	O
the	O
2.5GHz	O
16-core	O
64-bit	B-Device
(	O
RV64GCV	O
)	O
XuanTie	O
910	O
out-of-order	O
processor	O
.	O
</s>
<s>
The	O
Institute	O
of	O
Computing	O
Technology	O
of	O
the	O
Chinese	O
Academy	O
of	O
Sciences	O
(	O
ICT	O
CAS	O
)	O
,	O
in	O
June	O
2020	O
launched	O
the	O
XiangShan	O
high-performance	O
RISC-V	B-Device
processor	O
project	O
.	O
</s>
<s>
A	O
normal	O
problem	O
for	O
a	O
new	O
instruction	B-General_Concept
set	I-General_Concept
is	O
a	O
lack	O
of	O
CPU	B-General_Concept
designs	I-General_Concept
and	O
software	O
—	O
both	O
issues	O
limit	O
its	O
usability	O
and	O
reduce	O
adoption	O
.	O
</s>
<s>
RISC-V	B-Device
has	O
a	O
large	O
number	O
of	O
CPU	B-General_Concept
designs	I-General_Concept
.	O
</s>
<s>
RISC-V	B-Device
software	O
includes	O
toolchains	B-General_Concept
,	O
operating	B-General_Concept
systems	I-General_Concept
,	O
middleware	B-General_Concept
and	O
design	O
software	O
.	O
</s>
<s>
Available	O
RISC-V	B-Device
software	O
tools	O
include	O
a	O
GNU	B-Application
Compiler	I-Application
Collection	I-Application
(	O
GCC	B-Application
)	O
toolchain	B-General_Concept
(	O
with	O
GDB	B-Language
,	O
the	O
debugger	B-Application
)	O
,	O
an	O
LLVM	B-Application
toolchain	B-General_Concept
,	O
the	O
OVPsim	B-Application
simulator	O
(	O
and	O
library	O
of	O
RISC-V	B-Device
Fast	O
Processor	O
Models	O
)	O
,	O
the	O
Spike	O
simulator	O
,	O
and	O
a	O
simulator	O
in	O
QEMU	B-Application
(	O
RV32GC/RV64GC	O
)	O
.	O
</s>
<s>
is	O
already	O
integrated	O
into	O
mainline	O
OpenJDK	B-Language
repository	O
.	O
</s>
<s>
Operating	B-General_Concept
system	I-General_Concept
support	O
exists	O
for	O
the	O
Linux	B-Application
kernel	B-Operating_System
,	O
FreeBSD	B-Operating_System
,	O
NetBSD	B-Device
,	O
and	O
OpenBSD	B-Operating_System
but	O
the	O
supervisor-mode	O
instructions	O
were	O
unstandardized	O
before	O
version	O
1.11	O
of	O
the	O
privileged	O
ISA	O
specification	O
,	O
so	O
this	O
support	O
is	O
provisional	O
.	O
</s>
<s>
The	O
preliminary	O
FreeBSD	B-Operating_System
port	O
to	O
the	O
RISC-V	B-Device
architecture	I-Device
was	O
upstreamed	O
in	O
February	O
2016	O
,	O
and	O
shipped	O
in	O
FreeBSD	B-Operating_System
11.0	O
.	O
</s>
<s>
Ports	O
of	O
the	O
Debian	O
and	O
Fedora	O
Linux	B-Application
distributions	I-Application
,	O
and	O
a	O
port	O
of	O
Haiku	B-Language
,	O
are	O
stabilizing	O
(	O
all	O
only	O
support	O
64-bit	B-Device
RISC-V	B-Device
,	O
with	O
no	O
plans	O
to	O
support	O
32-bit	O
version	O
)	O
.	O
</s>
<s>
A	O
port	O
of	O
Das	B-Language
U-Boot	I-Language
exists	O
.	O
</s>
<s>
UEFI	O
Spec	O
v2.7	O
has	O
defined	O
the	O
RISC-V	B-Device
binding	O
and	O
a	O
TianoCore	B-Language
port	O
has	O
been	O
done	O
by	O
HPE	O
engineers	O
and	O
is	O
expected	O
to	O
be	O
upstreamed	O
.	O
</s>
<s>
Hex	O
Five	O
released	O
the	O
first	O
Secure	O
IoT	B-Operating_System
Stack	O
for	O
RISC-V	B-Device
with	O
FreeRTOS	B-Operating_System
support	O
.	O
</s>
<s>
Also	O
xv6	B-Operating_System
,	O
a	O
modern	O
reimplementation	O
of	O
Sixth	B-Operating_System
Edition	I-Operating_System
Unix	I-Operating_System
in	O
ANSI	O
C	O
used	O
for	O
pedagogical	O
purposes	O
in	O
MIT	O
,	O
was	O
ported	O
.	O
</s>
<s>
Pharos	O
RTOS	O
has	O
been	O
ported	O
to	O
64-bit	B-Device
RISC-V	B-Device
(	O
including	O
time	O
and	O
memory	O
protection	O
)	O
.	O
</s>
<s>
Also	O
see	O
Comparison	B-Operating_System
of	I-Operating_System
real-time	I-Operating_System
operating	I-Operating_System
systems	I-Operating_System
.	O
</s>
<s>
A	O
simulator	O
exists	O
to	O
run	O
a	O
RISC-V	B-Device
Linux	B-Application
system	O
on	O
a	O
web	B-Application
browser	I-Application
using	O
JavaScript	B-Language
.	O
</s>
<s>
QEMU	B-Application
supports	O
running	O
(	O
using	O
binary	O
translation	O
)	O
32	O
-	O
and	O
64-bit	B-Device
RISC-V	B-Device
systems	O
(	O
e.g.	O
</s>
<s>
Linux	B-Application
)	O
with	O
a	O
number	O
of	O
emulated	O
or	O
virtualized	B-General_Concept
devices	O
(	O
serial	O
,	O
parallel	O
,	O
USB	B-Protocol
,	O
network	O
,	O
storage	O
,	O
real	O
time	O
clock	O
,	O
watchdog	O
,	O
audio	O
)	O
,	O
as	O
well	O
as	O
running	O
RISC-V	B-Device
Linux	B-Application
binaries	O
(	O
translating	O
syscalls	O
to	O
the	O
host	O
kernel	B-Operating_System
)	O
.	O
</s>
<s>
The	O
Creator	O
simulator	O
is	O
portable	O
and	O
allows	O
the	O
user	O
to	O
learn	O
various	O
assembly	B-Language
languages	I-Language
of	O
different	O
processors	O
(	O
Creator	O
has	O
examples	O
with	O
an	O
implementation	O
of	O
RISC-V	B-Device
and	O
MIPS32	O
instructions	O
)	O
.	O
</s>
<s>
The	O
extensible	O
educational	O
simulator	O
WepSIM	O
implements	O
a	O
(	O
)	O
subset	O
of	O
RISC-V	B-Device
instructions	O
(	O
RV32I+M	O
)	O
and	O
allows	O
the	O
execution	O
of	O
in	O
assembly	O
.	O
</s>
<s>
A	O
number	O
of	O
languages	O
have	O
been	O
applied	O
to	O
creating	O
RISC-V	B-Device
IP	B-Architecture
cores	I-Architecture
including	O
a	O
Scala-based	O
hardware	O
description	O
language	O
,	O
Chisel	O
,	O
which	O
can	O
reduce	O
the	O
designs	O
to	O
Verilog	B-Language
for	O
use	O
in	O
devices	O
,	O
and	O
the	O
CodAL	O
processor	O
description	O
language	O
which	O
has	O
been	O
used	O
in	O
to	O
describe	O
RISC-V	B-Device
processor	O
cores	B-Architecture
and	O
to	O
generate	O
corresponding	O
HDKs	O
(	O
RTL	O
,	O
testbench	O
and	O
UVM	O
)	O
and	O
SDKs	O
.	O
</s>
<s>
The	O
RISC-V	B-Device
International	O
Compliance	O
Task	O
Group	O
has	O
a	O
GitHub	B-Application
repository	O
for	O
RV32IMC	O
.	O
</s>
<s>
IAR	O
Systems	O
released	O
the	O
first	O
version	O
of	O
IAR	O
Embedded	O
Workbench	O
for	O
RISC-V	B-Device
,	O
which	O
supports	O
RV32	O
32-bit	O
RISC-V	B-Device
cores	B-Architecture
and	O
extensions	O
in	O
the	O
first	O
version	O
.	O
</s>
<s>
Future	O
releases	O
will	O
include	O
64-bit	B-Device
support	I-Device
and	O
support	O
for	O
the	O
smaller	O
RV32E	O
base	O
instruction	B-General_Concept
set	I-General_Concept
,	O
as	O
well	O
as	O
functional	O
safety	O
certification	O
and	O
security	O
solutions	O
.	O
</s>
<s>
Lauterbach	O
added	O
support	O
for	O
RISC-V	B-Device
to	O
their	O
TRACE32	O
JTAG	O
debuggers	B-Application
.	O
</s>
<s>
Lauterbach	O
also	O
announced	O
support	O
for	O
SiFives	O
RISC-V	B-Device
NEXUS	O
based	O
processor	O
trace	O
.	O
</s>
<s>
SEGGER	O
added	O
support	O
for	O
RISC-V	B-Device
cores	B-Architecture
to	O
their	O
debug	O
probe	O
J-Link	O
,	O
their	O
integrated	O
development	O
environment	O
Embedded	O
Studio	O
,	O
and	O
their	O
RTOS	O
embOS	O
and	O
embedded	O
software	O
.	O
</s>
