<s>
The	O
RHPPC	B-General_Concept
is	O
a	O
radiation	O
hardened	O
processor	B-Architecture
based	O
on	O
PowerPC	B-Architecture
603e	O
technology	O
licensed	O
from	O
Motorola	O
(	O
now	O
Freescale	O
)	O
and	O
manufactured	O
by	O
Honeywell	O
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
is	O
equivalent	O
to	O
the	O
commercial	O
PowerPC	B-Architecture
603e	O
processor	B-Architecture
with	O
the	O
minor	O
exceptions	O
of	O
the	O
phase	O
locked	O
loop	O
(	O
PLL	O
)	O
and	O
the	O
processor	B-Architecture
version	O
register	O
(	O
PVR	O
)	O
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
processor	B-Architecture
is	O
compatible	O
with	O
the	O
PowerPC	B-Architecture
architecture	O
(	O
Book	O
I-III	O
)	O
,	O
the	O
PowerPC	B-Architecture
603e	O
programmers	O
interface	O
and	O
is	O
also	O
supported	O
by	O
common	O
PowerPC	B-Architecture
software	O
tools	O
and	O
embedded	O
operating	O
systems	O
,	O
like	O
VxWorks	B-Operating_System
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
processor	B-Architecture
generates	O
190	O
MIPS	O
with	O
the	O
Dhrystone	O
mix	O
with	O
its	O
core	O
clock	O
at	O
100MHz	O
(	O
i.e.	O
</s>
<s>
the	O
RHPPC	B-General_Concept
processor	B-Architecture
completes	O
1.9	O
instructions	O
per	O
cycle	O
)	O
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
runs	O
with	O
a	O
25	O
,	O
33.3	O
,	O
40	O
,	O
or	O
50MHz	O
60x	O
bus	O
clock	O
(	O
SYSCLK	O
)	O
which	O
is	O
generated	O
based	O
on	O
the	O
PCI	O
clock	O
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
processor	B-Architecture
is	O
a	O
superscalar	B-General_Concept
machine	O
with	O
five	O
execution	O
units	O
:	O
system	O
register	O
unit	O
,	O
integer	B-General_Concept
unit	I-General_Concept
,	O
load/store	O
unit	O
,	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
and	O
branch	O
processing	O
unit	O
.	O
</s>
<s>
The	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
has	O
a	O
three	O
level	O
deep	O
pipeline	O
.	O
</s>
<s>
Out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
is	O
supported	O
through	O
the	O
use	O
of	O
shadow	O
or	O
rename	O
registers	O
.	O
</s>
<s>
Thus	O
,	O
in	O
theory	O
,	O
the	O
RHPPC	B-General_Concept
processor	B-Architecture
can	O
complete	O
three	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
and	O
a	O
16	O
kB	O
data	O
L1	B-General_Concept
caches	I-General_Concept
that	O
are	O
4	O
way	O
set	O
associative	O
,	O
and	O
support	O
write	O
through	O
or	O
copy-back	O
protocol	O
.	O
</s>
<s>
The	O
RHPPC	B-General_Concept
processor	B-Architecture
is	O
fabricated	B-Architecture
with	O
Honeywell	O
’s	O
SOI-V	O
0.35µm	O
,	O
four	O
level	O
metal	O
process	O
.	O
</s>
<s>
The	O
lead	O
can	O
have	O
either	O
solder	B-Algorithm
balls	I-Algorithm
,	O
solder	O
columns	O
,	O
or	O
short	O
pins	O
attached	O
.	O
</s>
<s>
Standard	O
die	O
attach	O
and	O
wire	B-Algorithm
bond	I-Algorithm
die	O
interconnect	O
are	O
used	O
.	O
</s>
