<s>
RAM	B-General_Concept
parity	I-General_Concept
checking	O
is	O
the	O
storing	O
of	O
a	O
redundant	O
parity	B-Error_Name
bit	I-Error_Name
representing	O
the	O
parity	B-Error_Name
(	O
odd	O
or	O
even	O
)	O
of	O
a	O
small	O
amount	O
of	O
computer	O
data	O
(	O
typically	O
one	O
byte	B-Application
)	O
stored	O
in	O
random-access	B-Architecture
memory	I-Architecture
,	O
and	O
the	O
subsequent	O
comparison	O
of	O
the	O
stored	O
and	O
the	O
computed	O
parity	B-Error_Name
to	O
detect	B-Error_Name
whether	I-Error_Name
a	I-Error_Name
data	I-Error_Name
error	I-Error_Name
has	I-Error_Name
occurred	I-Error_Name
.	O
</s>
<s>
The	O
parity	B-Error_Name
bit	I-Error_Name
was	O
originally	O
stored	O
in	O
additional	O
individual	O
memory	O
chips	O
;	O
with	O
the	O
introduction	O
of	O
plug-in	O
DIMM	B-General_Concept
,	O
SIMM	B-General_Concept
,	O
etc	O
.	O
</s>
<s>
modules	O
,	O
they	O
became	O
available	O
in	O
non-parity	O
and	O
parity	B-Error_Name
(	O
with	O
an	O
extra	O
bit	O
per	O
byte	B-Application
,	O
storing	O
9	O
bits	O
for	O
every	O
8	O
bits	O
of	O
actual	O
data	O
)	O
versions	O
.	O
</s>
<s>
Early	O
computers	O
sometimes	O
required	O
the	O
use	O
of	O
parity	B-General_Concept
RAM	I-General_Concept
,	O
and	O
parity-checking	O
could	O
not	O
be	O
disabled	O
.	O
</s>
<s>
A	O
parity	B-Error_Name
error	I-Error_Name
typically	O
caused	O
the	O
machine	O
to	O
halt	O
,	O
with	O
loss	O
of	O
unsaved	O
data	O
;	O
this	O
is	O
usually	O
a	O
better	O
option	O
than	O
saving	O
corrupt	O
data	O
.	O
</s>
<s>
Logic	B-General_Concept
parity	I-General_Concept
RAM	I-General_Concept
,	O
also	O
known	O
as	O
fake	O
parity	B-General_Concept
RAM	I-General_Concept
,	O
is	O
non-parity	B-General_Concept
RAM	I-General_Concept
that	O
can	O
be	O
used	O
in	O
computers	O
that	O
require	O
parity	B-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
Logic	B-General_Concept
parity	I-General_Concept
RAM	I-General_Concept
recalculates	O
an	O
always-valid	O
parity	B-Error_Name
bit	I-Error_Name
each	O
time	O
a	O
byte	B-Application
is	O
read	O
from	O
memory	O
,	O
instead	O
of	O
storing	O
the	O
parity	B-Error_Name
bit	I-Error_Name
when	O
the	O
memory	O
is	O
written	O
to	O
;	O
the	O
calculated	O
parity	B-Error_Name
bit	I-Error_Name
,	O
which	O
will	O
not	O
reveal	O
if	O
the	O
data	O
has	O
been	O
corrupted	O
(	O
hence	O
the	O
name	O
"	O
fake	O
parity	B-Error_Name
"	O
)	O
,	O
is	O
presented	O
to	O
the	O
parity-checking	O
logic	O
.	O
</s>
<s>
It	O
is	O
a	O
means	O
of	O
using	O
cheaper	O
8-bit	O
RAM	B-Architecture
in	O
a	O
system	O
designed	O
to	O
use	O
only	O
9-bit	O
parity	B-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
In	O
the	O
1970s-80s	O
,	O
RAM	B-Architecture
reliability	O
was	O
often	O
less-than-perfect	O
;	O
in	O
particular	O
,	O
the	O
4116	O
DRAMs	O
which	O
were	O
an	O
industry	O
standard	O
from	O
1975	O
to	O
1983	O
had	O
a	O
considerable	O
failure	O
rate	O
as	O
they	O
used	O
triple	O
voltages	O
(	O
-5	O
,	O
+5	O
,	O
and	O
+12	O
)	O
which	O
resulted	O
in	O
high	O
operating	O
temperatures	O
.	O
</s>
<s>
However	O
,	O
RAM	B-Architecture
did	O
not	O
achieve	O
modern	O
standards	O
of	O
reliability	O
until	O
the	O
1990s	O
.	O
</s>
<s>
Since	O
then	O
errors	O
have	O
become	O
less	O
visible	O
as	O
simple	O
parity	B-General_Concept
RAM	I-General_Concept
has	O
fallen	O
out	O
of	O
use	O
;	O
either	O
they	O
are	O
invisible	O
as	O
they	O
are	O
not	O
detected	O
,	O
or	O
they	O
are	O
corrected	O
invisibly	O
with	O
ECC	B-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
Modern	O
RAM	B-Architecture
is	O
believed	O
,	O
with	O
much	O
justification	O
,	O
to	O
be	O
reliable	O
,	O
and	O
error-detecting	O
RAM	B-Architecture
has	O
largely	O
fallen	O
out	O
of	O
use	O
for	O
non-critical	O
applications	O
.	O
</s>
<s>
By	O
the	O
mid-1990s	O
,	O
most	O
DRAM	O
had	O
dropped	O
parity	B-Error_Name
checking	I-Error_Name
as	O
manufacturers	O
felt	O
confident	O
that	O
it	O
was	O
no	O
longer	O
necessary	O
.	O
</s>
<s>
Some	O
machines	O
that	O
support	O
parity	B-Error_Name
or	O
ECC	O
allow	O
checking	O
to	O
be	O
enabled	O
or	O
disabled	O
in	O
the	O
BIOS	B-Operating_System
,	O
permitting	O
cheaper	O
non-parity	B-General_Concept
RAM	I-General_Concept
to	O
be	O
used	O
.	O
</s>
<s>
If	O
parity	B-General_Concept
RAM	I-General_Concept
is	O
used	O
the	O
chipset	O
will	O
usually	O
use	O
it	O
to	O
implement	O
error	B-Error_Name
correction	I-Error_Name
,	O
rather	O
than	O
halting	O
the	O
machine	O
on	O
a	O
single-bit	O
parity	B-Error_Name
error	I-Error_Name
.	O
</s>
<s>
However	O
,	O
as	O
discussed	O
in	O
the	O
article	O
on	O
ECC	B-General_Concept
memory	I-General_Concept
,	O
errors	O
,	O
while	O
not	O
everyday	O
events	O
,	O
are	O
not	O
negligibly	O
infrequent	O
.	O
</s>
<s>
Even	O
in	O
the	O
absence	O
of	O
manufacturing	O
defects	O
,	O
naturally	O
occurring	O
radiation	O
causes	O
random	O
errors	O
;	O
tests	O
on	O
Google	B-Application
's	I-Application
many	O
servers	O
found	O
that	O
memory	O
errors	O
were	O
not	O
rare	O
events	O
,	O
and	O
that	O
the	O
incidence	O
of	O
memory	O
errors	O
and	O
the	O
range	O
of	O
error	O
rates	O
across	O
different	O
DIMMs	B-General_Concept
were	O
much	O
higher	O
than	O
previously	O
reported	O
.	O
</s>
<s>
Simple	O
go/no	O
go	O
parity	B-Error_Name
checking	I-Error_Name
requires	O
that	O
the	O
memory	O
have	O
extra	O
,	O
redundant	O
bits	O
beyond	O
those	O
needed	O
to	O
store	O
the	O
data	O
;	O
but	O
if	O
extra	O
bits	O
are	O
available	O
,	O
they	O
can	O
be	O
used	O
to	O
correct	O
,	O
as	O
well	O
as	O
detect	O
,	O
errors	O
.	O
</s>
<s>
Earlier	O
memory	O
as	O
used	O
in	O
,	O
for	O
example	O
,	O
the	O
IBM	B-Operating_System
PC/AT	I-Operating_System
(	O
FPM	O
and	O
EDO	O
memory	O
)	O
were	O
available	O
in	O
versions	O
that	O
supported	O
either	O
no	O
checking	O
or	O
parity	B-Error_Name
checking	I-Error_Name
(	O
in	O
earlier	O
computers	O
that	O
used	O
individual	O
RAM	B-Architecture
chips	I-Architecture
rather	O
than	O
DIMM	B-General_Concept
or	O
SIMM	B-General_Concept
modules	O
,	O
extra	O
chips	O
were	O
used	O
to	O
store	O
parity	B-Error_Name
bits	I-Error_Name
)	O
;	O
if	O
the	O
computer	O
detected	O
a	O
parity	B-Error_Name
error	I-Error_Name
it	O
would	O
display	O
a	O
message	O
to	O
that	O
effect	O
and	O
stop	O
.	O
</s>
<s>
The	O
SDRAM	O
and	O
DDR	O
modules	O
that	O
replaced	O
the	O
earlier	O
types	O
are	O
usually	O
available	O
either	O
without	O
error-checking	O
or	O
with	O
ECC	O
(	O
full	O
correction	O
,	O
not	O
just	O
parity	B-Error_Name
)	O
.	O
</s>
<s>
An	O
example	O
of	O
a	O
single-bit	O
error	O
that	O
would	O
be	O
ignored	O
by	O
a	O
system	O
with	O
no	O
error-checking	O
,	O
would	O
halt	O
a	O
machine	O
with	O
parity	B-Error_Name
checking	I-Error_Name
,	O
or	O
would	O
be	O
invisibly	O
corrected	O
by	O
ECC	O
:	O
a	O
single	O
bit	O
is	O
stuck	O
at	O
1	O
due	O
to	O
a	O
faulty	O
chip	O
,	O
or	O
becomes	O
changed	O
to	O
1	O
due	O
to	O
background	O
or	O
cosmic	O
radiation	O
;	O
a	O
spreadsheet	O
storing	O
numbers	O
in	O
ASCII	O
format	O
is	O
loaded	O
,	O
and	O
the	O
number	O
"	O
8	O
"	O
is	O
stored	O
in	O
the	O
byte	B-Application
which	O
contains	O
the	O
stuck	O
bit	O
as	O
its	O
eighth	O
bit	O
;	O
then	O
another	O
change	O
is	O
made	O
to	O
the	O
spreadsheet	O
and	O
it	O
is	O
stored	O
.	O
</s>
<s>
If	O
the	O
stored	O
parity	B-Error_Name
is	O
different	O
from	O
the	O
parity	B-Error_Name
computed	O
from	O
the	O
stored	O
data	O
,	O
at	O
least	O
one	O
bit	O
must	O
have	O
been	O
changed	O
due	O
to	O
data	O
corruption	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
the	O
home	O
PC	O
where	O
data	O
integrity	O
is	O
often	O
perceived	O
to	O
be	O
of	O
little	O
importance	O
—	O
certainly	O
true	O
for	O
,	O
say	O
games	O
and	O
web	O
browsing	O
,	O
less	O
so	O
for	O
Internet	O
banking	O
and	O
home	O
finances	O
—	O
non-parity	O
memory	O
is	O
an	O
affordable	O
option	O
.	O
</s>
<s>
However	O
,	O
if	O
data	O
integrity	O
is	O
required	O
,	O
parity	B-Error_Name
memory	O
will	O
halt	O
the	O
computer	O
and	O
prevent	O
the	O
corrupt	O
data	O
from	O
affecting	O
results	O
or	O
stored	O
data	O
,	O
although	O
losing	O
intermediate	O
unstored	O
data	O
and	O
preventing	O
use	O
until	O
any	O
faulty	O
RAM	B-Architecture
is	O
replaced	O
.	O
</s>
<s>
RAM	B-Architecture
with	O
ECC	O
or	O
Error	B-Error_Name
Correction	I-Error_Name
Code	O
can	O
detect	O
and	O
correct	B-Error_Name
errors	I-Error_Name
.	O
</s>
<s>
As	O
with	O
parity	B-General_Concept
RAM	I-General_Concept
,	O
additional	O
information	O
needs	O
to	O
be	O
stored	O
and	O
more	O
processing	O
needs	O
to	O
be	O
done	O
,	O
making	O
ECC	B-General_Concept
RAM	I-General_Concept
more	O
expensive	O
and	O
a	O
little	O
slower	O
than	O
non-parity	O
and	O
logic	B-General_Concept
parity	I-General_Concept
RAM	I-General_Concept
.	O
</s>
<s>
This	O
type	O
of	O
ECC	B-General_Concept
memory	I-General_Concept
is	O
especially	O
useful	O
for	O
any	O
application	O
where	O
uptime	O
is	O
a	O
concern	O
:	O
failing	O
bits	O
in	O
a	O
memory	O
word	O
are	O
detected	O
and	O
corrected	O
on	O
the	O
fly	O
with	O
no	O
impact	O
to	O
the	O
application	O
.	O
</s>
<s>
This	O
mechanism	O
of	O
detection	O
and	O
correction	O
is	O
known	O
as	O
EEC	O
or	O
Extended	B-General_Concept
Error	I-General_Concept
Correction	I-General_Concept
.	O
</s>
<s>
Parity	B-General_Concept
rams	I-General_Concept
compose	O
of	O
same	O
chips	O
in	O
quantity	O
of	O
3	O
and	O
9	O
(	O
single	O
side	O
)	O
,	O
and	O
6	O
or	O
18	O
(	O
double	O
side	O
)	O
on	O
the	O
memory	O
module	O
of	O
the	O
30	O
pin	O
unit	O
.	O
</s>
<s>
Parity	B-General_Concept
ram	I-General_Concept
chips	O
have	O
exact	O
'	O
2	O
to	O
1	O
 '	O
or	O
'	O
8	O
to	O
1	O
pin	O
 '	O
count	O
on	O
30	O
pin	O
modules	O
.	O
</s>
<s>
But	O
on	O
a	O
72	O
pin	O
module	O
,	O
parity	B-Error_Name
chips	O
compositions	O
are	O
quite	O
different	O
,	O
'	O
either	O
a	O
square	O
4x12	O
pin	O
chip	O
at	O
the	O
center	O
complementing	O
8	O
piece	O
of	O
2x12	O
pin	O
ram	B-Architecture
chips	I-Architecture
for	O
one	O
side	O
 '	O
,	O
'	O
4	O
little	O
2x7	O
pin	O
chips	O
complementing	O
to	O
a	O
normal	O
8	O
piece	O
2x7	O
pin	O
ram	B-Architecture
chips	I-Architecture
 '	O
or	O
'	O
totally	O
same	O
9	O
chips	O
stays	O
on	O
each	O
side	O
 '	O
.	O
</s>
<s>
Important	O
thing	O
here	O
is	O
that	O
,	O
parity	B-General_Concept
ram	I-General_Concept
chips	O
have	O
the	O
exact	O
'	O
8	O
to	O
1	O
 '	O
or	O
'	O
4	O
to	O
1	O
 '	O
pin	O
count	O
for	O
the	O
parity	B-Error_Name
on	O
a	O
72	O
pin	O
module	O
.	O
</s>
<s>
All	O
ECC	O
chips	O
have	O
different	O
markings	O
on	O
them	O
,	O
other	O
than	O
the	O
normal	O
ram	B-Architecture
chips	I-Architecture
.	O
</s>
<s>
The	O
second	O
option	O
for	O
5x2	O
pin	O
ram	B-Architecture
modules	O
again	O
in	O
quantity	O
of	O
8	O
,	O
there	O
can	O
be	O
four	O
additional	O
pieces	O
of	O
5x2	O
pin	O
ECC	O
modules	O
,	O
either	O
on	O
the	O
same	O
side	O
or	O
at	O
the	O
other	O
side	O
staying	O
together	O
.	O
</s>
<s>
If	O
ram	B-Architecture
modules	O
present	O
on	O
both	O
sizes	O
,	O
chip	O
count	O
doubles	O
to	O
18	O
chips	O
or	O
24	O
chips	O
respectively	O
.	O
</s>
<s>
Finally	O
,	O
if	O
ram	B-Architecture
capacity	O
increases	O
more	O
,	O
the	O
pin	O
count	O
on	O
all	O
chips	O
increases	O
by	O
+4	O
more	O
for	O
every	O
present	O
chip	O
.	O
</s>
<s>
So	O
,	O
unlike	O
parity	B-Error_Name
chips	O
,	O
there	O
is	O
no	O
exact	O
'	O
8	O
to	O
1	O
 '	O
and	O
'	O
2	O
to	O
1	O
 '	O
pin	O
count	O
;	O
only	O
'	O
4	O
to	O
1	O
 '	O
pin	O
count	O
design	O
and/or	O
+4	O
pin	O
on	O
each	O
side	O
ECC	O
chip	O
design	O
,	O
if	O
it	O
has	O
single	O
side	O
9	O
or	O
double	O
side	O
18	O
piece	O
of	O
chips	O
,	O
for	O
ECC	O
to	O
function	O
.	O
</s>
<s>
"	O
Non	O
Parity/non	O
ECC	O
"	O
,	O
"	O
Parity	B-Error_Name
"	O
and	O
"	O
ECC	O
"	O
modules	O
do	O
not	O
work	O
together	O
!	O
</s>
