<s>
The	O
R800	B-General_Concept
is	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
used	O
in	O
the	O
MSX	O
Turbo-R	O
home	O
computer	O
.	O
</s>
<s>
The	O
R800	B-General_Concept
was	O
designed	O
by	O
ASCII	O
Corporation	O
of	O
Japan	O
and	O
built	O
by	O
Mitsui	O
&	O
Co	O
The	O
goal	O
was	O
a	O
modern	O
and	O
pipelined	B-General_Concept
CPU	I-General_Concept
binary	O
compatible	O
with	O
the	O
Z80	B-General_Concept
,	O
and	O
therefore	O
with	O
MSX	O
software	O
,	O
while	O
also	O
maintaining	O
compatibility	B-Device
with	O
older	O
MSX	O
Z80-based	O
hardware	O
.	O
</s>
<s>
During	O
the	O
development	O
of	O
the	O
MSX	O
Turbo	O
R	O
,	O
ASCII	O
Corporation	O
considered	O
various	O
processors	O
,	O
both	O
compatible	O
and	O
incompatible	O
with	O
the	O
Z80	B-General_Concept
,	O
as	O
candidates	O
.	O
</s>
<s>
At	O
that	O
time	O
,	O
Kazuya	O
Kishioka	O
,	O
a	O
company	O
employee	O
,	O
was	O
researching	O
and	O
developing	O
an	O
ASIC	O
that	O
was	O
a	O
high-speed	O
version	O
of	O
the	O
Z80	B-General_Concept
and	O
largely	O
customized	O
for	O
the	O
MSX	O
architecture	O
.	O
</s>
<s>
For	O
software	O
compatibility	B-Device
with	O
older	O
MSX	O
software	O
,	O
the	O
R800	B-General_Concept
uses	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
as	O
the	O
Z80	B-General_Concept
,	O
with	O
only	O
minor	O
but	O
useful	O
additions	O
,	O
such	O
as	O
8x8-bit	O
and	O
16x16-bit	O
multiplication	O
instructions	O
called	O
MULUB	O
(	O
8-bit	O
)	O
,	O
and	O
MULUW	O
(	O
16-bit	B-Device
)	O
.	O
</s>
<s>
Also	O
,	O
many	O
of	O
the	O
undocumented	O
Z80	B-General_Concept
instructions	O
were	O
made	O
official	O
,	O
including	O
all	O
the	O
opcodes	B-Language
for	O
instructions	O
dealing	O
with	O
IX	O
and	O
IY	O
as	O
8-bit	O
registers	O
(	O
IXH	O
,	O
IXL	O
,	O
IYH	O
,	O
IYL	O
)	O
.	O
</s>
<s>
As	O
the	O
R800	B-General_Concept
is	O
not	O
based	O
directly	O
on	O
the	O
Z80	B-General_Concept
,	O
but	O
stems	O
from	O
the	O
Z800	B-Device
family	O
,	O
it	O
lacks	O
some	O
of	O
the	O
other	O
undocumented	O
Z80	B-General_Concept
features	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
undocumented	O
flags	O
represented	O
in	O
bits	O
3	O
and	O
5	O
of	O
the	O
F	O
register	O
do	O
n't	O
assume	O
the	O
same	O
values	O
as	O
in	O
Z80	B-General_Concept
(	O
causing	O
it	O
to	O
fail	O
ZEXALL	O
tests	O
)	O
and	O
the	O
undocumented	O
opcode	B-Language
often	O
called	O
SLL	O
is	O
just	O
an	O
alias	O
of	O
the	O
SLA	O
instruction	O
.	O
</s>
<s>
Being	O
a	O
much	O
newer	O
design	O
,	O
the	O
R800	B-General_Concept
implementation	O
was	O
quite	O
different	O
from	O
the	O
old	O
Z80	B-General_Concept
.	O
</s>
<s>
The	O
changes	O
were	O
similar	O
to	O
the	O
Z800	B-Device
,	O
Z280	B-Device
,	O
Z380	B-Device
and	O
eZ80	B-Device
lines	O
of	O
Z80	B-General_Concept
compatible	O
processors	O
.	O
</s>
<s>
The	O
original	O
Z80	B-General_Concept
uses	O
an	O
unusual	O
4-bit	O
ALU	B-General_Concept
hardware	O
internally	O
,	O
a	O
solution	O
actually	O
able	O
to	O
compete	O
with	O
similar	O
CPUs	O
using	O
full	O
hardwired	O
8-bit	O
ALU	B-General_Concept
logic	O
(	O
such	O
as	O
its	O
immediate	O
precursor	O
,	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
)	O
.	O
</s>
<s>
However	O
,	O
the	O
R800	B-General_Concept
designers	O
implemented	O
a	O
full	O
16-bit	B-Device
ALU	B-General_Concept
in	O
order	O
to	O
keep	O
up	O
with	O
its	O
more	O
pipelined	B-General_Concept
execution	O
.	O
</s>
<s>
Instructions	O
like	O
ADD	O
HL	O
,	O
BC	O
that	O
takes	O
11	O
clock	O
cycles	O
on	O
the	O
Z80	B-General_Concept
can	O
in	O
some	O
situations	O
execute	O
in	O
as	O
little	O
as	O
one	O
bus	O
cycle	O
(	O
1-2	O
clocks	O
)	O
on	O
the	O
R800	B-General_Concept
,	O
due	O
to	O
the	O
degree	O
of	O
pipelining	O
made	O
possible	O
by	O
this	O
full	O
width	O
ALU	B-General_Concept
.	O
</s>
<s>
The	O
data	B-General_Concept
bus	I-General_Concept
remained	O
8-bit	O
to	O
maintain	O
compatibility	B-Device
with	O
old	O
hardware	O
.	O
</s>
<s>
Additional	O
changes	O
were	O
made	O
in	O
the	O
way	O
the	O
CPU	O
fetches	O
opcodes	B-Language
.	O
</s>
<s>
The	O
original	O
Z80	B-General_Concept
uses	O
two	O
cycles	O
to	O
fetch	O
a	O
simple	O
instruction	O
like	O
OR	O
A	O
,	O
plus	O
two	O
cycles	O
for	O
refresh	O
.	O
</s>
<s>
A	O
review	O
of	O
the	O
fetch	O
mechanism	O
in	O
a	O
typical	O
MSX	O
environment	O
helps	O
in	O
explaining	O
the	O
R800	B-General_Concept
:	O
</s>
<s>
Since	O
most	O
implementations	O
of	O
MSX	O
use	O
RAM	B-Architecture
disposed	O
in	O
a	O
256×256	O
bytes	O
block	O
,	O
two	O
cycles	O
are	O
required	O
to	O
set	O
the	O
address	O
for	O
the	O
fetch	O
.	O
</s>
<s>
The	O
R800	B-General_Concept
avoids	O
this	O
by	O
remembering	O
the	O
last	O
known	O
state	O
of	O
the	O
higher	O
8-bits	O
.	O
</s>
<s>
However	O
,	O
on	O
the	O
Z80	B-General_Concept
,	O
the	O
refresh	O
cycles	O
destroy	O
the	O
information	O
on	O
the	O
higher	O
bits	O
,	O
so	O
a	O
workaround	O
was	O
needed	O
.	O
</s>
<s>
The	O
solution	O
used	O
in	O
the	O
R800	B-General_Concept
was	O
to	O
refresh	O
entire	O
blocks	O
of	O
RAM	B-Architecture
,	O
instead	O
of	O
refreshing	O
one	O
line	O
of	O
RAM	B-Architecture
on	O
each	O
instruction	O
issued	O
.	O
</s>
<s>
Each	O
30μs	O
,	O
the	O
CPU	O
is	O
halted	O
for	O
4μs	O
,	O
this	O
time	O
is	O
used	O
to	O
refresh	O
a	O
block	O
of	O
the	O
RAM	B-Architecture
.	O
</s>
<s>
Since	O
there	O
's	O
no	O
refresh	O
in	O
between	O
fetch	O
instructions	O
,	O
and	O
the	O
waitstate	O
is	O
removed	O
due	O
to	O
faster	O
RAM	B-Architecture
chips	I-Architecture
,	O
simple	O
instructions	O
can	O
be	O
issued	O
using	O
only	O
one	O
cycle	O
.	O
</s>
<s>
This	O
cycle	O
would	O
be	O
cycle	O
2	O
in	O
the	O
Z80	B-General_Concept
example	O
above	O
;	O
cycle	O
1	O
becomes	O
optional	O
,	O
and	O
it	O
's	O
only	O
issued	O
when	O
the	O
program	O
crosses	O
a	O
256-byte	O
boundary	O
.	O
</s>
<s>
All	O
this	O
only	O
applies	O
to	O
the	O
fast	O
RAM	B-Architecture
used	O
on	O
the	O
MSX	O
Turbo-R	O
.	O
</s>
<s>
External	O
hardware	O
,	O
connected	O
through	O
cartridge	O
slots	O
,	O
uses	O
timings	O
similar	O
to	O
Z80	B-General_Concept
.	O
</s>
<s>
Not	O
even	O
the	O
internal	O
ROM	B-Device
of	O
Turbo-R	O
is	O
fast	O
enough	O
for	O
this	O
fetch	O
scheme	O
,	O
so	O
additional	O
chips	O
on	O
the	O
Turbo-R	O
can	O
mirror	O
the	O
contents	O
of	O
ROM	B-Device
into	O
RAM	B-Architecture
,	O
in	O
order	O
to	O
make	O
it	O
run	O
faster	O
.	O
</s>
