<s>
The	O
R8000	B-General_Concept
is	O
a	O
microprocessor	B-Architecture
chipset	B-Device
developed	O
by	O
MIPS	O
Technologies	O
,	O
Inc	O
.	O
(	O
MTI	O
)	O
,	O
Toshiba	O
,	O
and	O
Weitek	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
implementation	O
of	O
the	O
MIPS	O
IV	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
R8000	B-General_Concept
is	O
also	O
known	O
as	O
the	O
TFP	O
,	O
for	O
Tremendous	O
Floating-Point	B-Algorithm
,	O
its	O
name	O
during	O
development	O
.	O
</s>
<s>
Development	O
of	O
the	O
R8000	B-General_Concept
started	O
in	O
the	O
early	O
1990s	O
at	O
Silicon	O
Graphics	O
,	O
Inc	O
.	O
(	O
SGI	O
)	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
was	O
specifically	O
designed	O
to	O
provide	O
the	O
performance	O
of	O
circa	O
1990s	O
supercomputers	B-Architecture
with	O
a	O
microprocessor	B-Architecture
instead	O
of	O
a	O
central	O
processing	O
unit	O
(	O
CPU	O
)	O
built	O
from	O
many	O
discrete	O
components	O
such	O
as	O
gate	O
arrays	O
.	O
</s>
<s>
At	O
the	O
time	O
,	O
the	O
performance	O
of	O
traditional	O
supercomputers	B-Architecture
was	O
not	O
advancing	O
as	O
rapidly	O
as	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
microprocessors	B-Architecture
.	O
</s>
<s>
It	O
was	O
predicted	O
that	O
RISC	B-Architecture
microprocessors	B-Architecture
would	O
eventually	O
match	O
the	O
performance	O
of	O
more	O
expensive	O
and	O
larger	O
supercomputers	B-Architecture
at	O
a	O
fraction	O
of	O
the	O
cost	O
and	O
size	O
,	O
making	O
computers	O
with	O
this	O
level	O
of	O
performance	O
more	O
accessible	O
and	O
enabling	O
deskside	O
workstations	B-Device
and	O
servers	O
to	O
replace	O
supercomputers	B-Architecture
in	O
many	O
situations	O
.	O
</s>
<s>
First	O
details	O
of	O
the	O
R8000	B-General_Concept
emerged	O
in	O
April	O
1992	O
in	O
an	O
announcement	O
by	O
MIPS	O
Computer	O
Systems	O
detailing	O
future	O
MIPS	O
microprocessors	B-Architecture
.	O
</s>
<s>
Development	O
of	O
the	O
R8000	B-General_Concept
was	O
transferred	O
to	O
MTI	O
,	O
where	O
it	O
continued	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
was	O
expected	O
to	O
be	O
introduced	O
in	O
1993	O
,	O
but	O
it	O
was	O
delayed	O
until	O
mid-1994	O
.	O
</s>
<s>
The	O
first	O
R8000	B-General_Concept
,	O
a	O
75MHz	O
part	O
,	O
was	O
introduced	O
on	O
7	O
June	O
1994	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
's	O
high	O
cost	O
and	O
narrow	O
market	O
(	O
technical	O
and	O
scientific	O
computing	O
)	O
restricted	O
its	O
market	O
share	O
,	O
and	O
although	O
it	O
was	O
popular	O
in	O
its	O
intended	O
market	O
,	O
it	O
was	O
largely	O
replaced	O
with	O
the	O
cheaper	O
and	O
generally	O
better	O
performing	O
R10000	B-General_Concept
introduced	O
January	O
1996	O
.	O
</s>
<s>
Users	O
of	O
the	O
R8000	B-General_Concept
were	O
SGI	O
,	O
who	O
used	O
it	O
in	O
their	O
Power	B-Application
Indigo2	I-Application
workstation	B-Device
,	O
Power	B-Application
Challenge	I-Application
server	O
,	O
Power	O
ChallengeArray	O
cluster	B-Architecture
and	O
Power	B-General_Concept
Onyx	I-General_Concept
visualization	O
system	O
.	O
</s>
<s>
In	O
the	O
November	O
1994	O
TOP500	B-Operating_System
list	O
,	O
50	O
systems	O
out	O
of	O
500	O
used	O
the	O
R8000	B-General_Concept
.	O
</s>
<s>
The	O
highest	O
ranked	O
R8000-based	O
systems	O
were	O
four	O
Power	O
Challenges	O
at	O
positions	O
154	O
to	O
157	O
.	O
</s>
<s>
Each	O
had	O
18	O
R8000s	B-General_Concept
.	O
</s>
<s>
The	O
chip	B-Device
set	I-Device
consisted	O
of	O
the	O
R8000	B-General_Concept
microprocessor	B-Architecture
,	O
the	O
R8010	O
floating-point	B-Algorithm
unit	O
,	O
two	O
Tag	O
RAMs	O
,	O
and	O
the	O
streaming	O
cache	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
is	O
superscalar	B-General_Concept
,	O
capable	O
of	O
issuing	O
up	O
to	O
four	O
instructions	O
per	O
cycle	O
,	O
and	O
executes	O
instructions	O
in	O
program	O
order	O
.	O
</s>
<s>
It	O
has	O
a	O
five-stage	O
integer	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
R8000	B-General_Concept
controlled	O
the	O
chip	B-Device
set	I-Device
and	O
executed	O
integer	O
instructions	O
.	O
</s>
<s>
It	O
contained	O
the	O
integer	O
execution	O
units	O
,	O
integer	O
register	B-General_Concept
file	I-General_Concept
,	O
primary	O
caches	O
and	O
hardware	O
for	O
instruction	O
fetch	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
the	O
translation	B-Architecture
lookaside	I-Architecture
buffers	I-Architecture
(	O
TLBs	O
)	O
.	O
</s>
<s>
Load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
begin	O
execution	O
in	O
stage	O
three	O
,	O
and	O
integer	O
instructions	O
in	O
stage	O
four	O
.	O
</s>
<s>
Results	O
are	O
written	O
to	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
in	O
stage	O
five	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
has	O
nine	O
read	O
ports	O
and	O
four	O
write	O
ports	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
issues	O
at	O
most	O
one	O
integer	O
store	O
per	O
cycle	O
,	O
and	O
one	O
final	O
read	O
port	O
delivers	O
the	O
integer	O
store	O
data	O
.	O
</s>
<s>
Two	O
register	B-General_Concept
file	I-General_Concept
write	O
ports	O
are	O
used	O
to	O
write	O
results	O
from	O
the	O
two	O
integer	O
functional	O
units	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
issues	O
two	O
integer	O
loads	O
per	O
cycle	O
,	O
and	O
the	O
other	O
two	O
write	O
ports	O
are	O
used	O
to	O
write	O
the	O
results	O
of	O
integer	O
loads	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
The	O
level	O
1	O
data	B-General_Concept
cache	I-General_Concept
was	O
organized	O
as	O
two	O
redundant	O
arrays	O
,	O
each	O
of	O
which	O
had	O
one	O
read	O
port	O
and	O
one	O
write	O
port	O
.	O
</s>
<s>
Integer	O
functional	O
units	O
consisted	O
of	O
two	O
integer	O
units	O
,	O
a	O
shift	O
unit	O
,	O
a	O
multiply-divide	O
unit	O
,	O
and	O
two	O
address	B-General_Concept
generator	I-General_Concept
units	I-General_Concept
.	O
</s>
<s>
The	O
R8000	B-General_Concept
has	O
two	O
address	B-General_Concept
generation	I-General_Concept
units	I-General_Concept
(	O
AGUs	B-General_Concept
)	O
that	O
calculate	O
virtual	O
address	O
for	O
loads	O
and	O
stores	O
.	O
</s>
<s>
The	O
16kB	O
data	B-General_Concept
cache	I-General_Concept
is	O
accessed	O
in	O
the	O
same	O
cycle	O
.	O
</s>
<s>
The	O
cache	O
is	O
not	O
protected	O
by	O
parity	B-Error_Name
or	O
by	O
error	B-Error_Name
correcting	I-Error_Name
code	I-Error_Name
(	O
ECC	O
)	O
.	O
</s>
<s>
If	O
the	O
loads	O
hit	O
in	O
the	O
data	B-General_Concept
cache	I-General_Concept
,	O
the	O
result	O
is	O
written	O
to	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
in	O
stage	O
five	O
.	O
</s>
<s>
The	O
R8010	O
executed	O
floating-point	B-Algorithm
instructions	O
provided	O
by	O
an	O
instruction	O
queue	O
on	O
the	O
R8000	B-General_Concept
.	O
</s>
<s>
The	O
queue	O
decoupled	O
the	O
floating-point	B-Algorithm
pipeline	B-General_Concept
from	O
the	O
integer	O
pipeline	B-General_Concept
,	O
implementing	O
a	O
limited	O
form	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
by	O
allowing	O
floating-point	B-Algorithm
instructions	O
to	O
execute	O
when	O
possible	O
after	O
or	O
before	O
the	O
integer	O
instructions	O
from	O
the	O
same	O
group	O
are	O
issued	O
.	O
</s>
<s>
It	O
contained	O
the	O
floating-point	B-Algorithm
register	B-General_Concept
file	I-General_Concept
,	O
a	O
load	O
queue	O
,	O
a	O
store	O
queue	O
,	O
and	O
two	O
identical	O
floating-point	B-Algorithm
units	O
.	O
</s>
<s>
The	O
R8010	O
implements	O
an	O
iterative	O
division	O
and	O
square-root	O
algorithm	O
that	O
uses	O
the	O
multiplier	O
for	O
a	O
key	O
part	O
,	O
requiring	O
the	O
pipeline	B-General_Concept
to	O
be	O
stalled	O
the	O
unit	O
for	O
the	O
duration	O
of	O
the	O
operation	O
.	O
</s>
<s>
The	O
streaming	O
cache	O
is	O
an	O
external	O
1	O
to	O
16MB	O
cache	O
that	O
serves	O
as	O
the	O
R8000	B-General_Concept
's	O
L2	O
unified	O
cache	O
and	O
the	O
R8010	O
's	O
L1	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
operates	O
at	O
the	O
same	O
clock	O
rate	O
as	O
the	O
R8000	B-General_Concept
and	O
is	O
built	O
from	O
commodity	O
synchronous	O
static	O
RAMs	O
.	O
</s>
<s>
This	O
scheme	O
was	O
used	O
to	O
attain	O
sustained	O
floating	B-Algorithm
point	I-Algorithm
performance	O
,	O
which	O
requires	O
frequent	O
access	O
to	O
data	O
.	O
</s>
<s>
A	O
small	O
low-latency	O
primary	B-General_Concept
cache	I-General_Concept
would	O
not	O
contain	O
enough	O
data	O
and	O
frequently	O
miss	O
,	O
necessitating	O
long	O
latency	O
refiles	O
that	O
reduce	O
performance	O
.	O
</s>
<s>
The	O
streaming	O
cache	O
is	O
two-way	O
interleaved	B-General_Concept
.	O
</s>
<s>
It	O
has	O
two	O
independent	O
banks	B-General_Concept
,	O
each	O
containing	O
data	O
from	O
even	O
or	O
odd	O
addresses	O
.	O
</s>
<s>
It	O
can	O
therefore	O
perform	O
two	O
reads	O
,	O
two	O
writes	O
,	O
or	O
a	O
read	O
and	O
a	O
write	O
every	O
cycle	O
,	O
provided	O
that	O
the	O
two	O
accesses	O
are	O
to	O
separate	O
banks	B-General_Concept
.	O
</s>
<s>
The	O
chips	O
are	O
implemented	O
in	O
a	O
0.7μm	O
BiCMOS	B-General_Concept
process	O
with	O
two	O
levels	O
of	O
polysilicon	O
and	O
two	O
levels	O
of	O
aluminium	O
interconnect	O
.	O
</s>
<s>
BiCMOS	B-General_Concept
circuitry	O
was	O
used	O
in	O
the	O
decoders	O
and	O
combined	O
sense	O
amplifier	O
and	O
comparator	O
portions	O
of	O
the	O
chip	O
to	O
reduce	O
cycle	O
time	O
.	O
</s>
<s>
The	O
pipeline	B-General_Concept
has	O
five	O
stages	O
:	O
in	O
stage	O
one	O
,	O
addresses	O
are	O
sent	O
to	O
the	O
Tag	O
RAMs	O
,	O
which	O
are	O
accessed	O
in	O
stage	O
two	O
.	O
</s>
<s>
In	O
stage	O
four	O
,	O
the	O
SSRAMs	O
are	O
accessed	O
and	O
data	O
is	O
returned	O
to	O
the	O
R8000	B-General_Concept
or	O
R8010	O
in	O
stage	O
five	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
contained	O
2.6	O
million	O
transistors	O
and	O
measured	O
17.34mm	O
by	O
17.30mm	O
(	O
299.98mm²	O
)	O
.	O
</s>
<s>
Both	O
were	O
fabricated	O
by	O
Toshiba	O
in	O
their	O
VHMOSIII	O
process	O
,	O
a	O
0.7μm	O
,	O
triple-layer	O
metal	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	O
.	O
</s>
<s>
Both	O
are	O
packaged	O
in	O
591-pin	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CPGA	O
)	O
packages	O
.	O
</s>
<s>
Both	O
chips	O
used	O
a	O
3.3V	O
power	O
supply	O
,	O
and	O
the	O
R8000	B-General_Concept
dissipated	O
13W	O
at	O
75MHz	O
.	O
</s>
