<s>
The	O
R5000	B-General_Concept
is	O
a	O
64-bit	O
,	O
bi-endian	O
,	O
superscalar	B-General_Concept
,	O
in-order	B-General_Concept
execution	O
2-issue	O
design	O
microprocessor	B-Architecture
,	O
that	O
implements	O
the	O
MIPS	B-Device
IV	I-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Quantum	O
Effect	O
Design	O
(	O
QED	O
)	O
in	O
1996	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
succeeded	O
the	O
QED	O
R4600	B-Device
and	O
R4700	B-Device
as	O
their	O
flagship	O
high-end	O
embedded	B-Architecture
microprocessor	I-Architecture
.	O
</s>
<s>
IDT	O
marketed	O
its	O
version	O
of	O
the	O
R5000	B-General_Concept
as	O
the	O
79RV5000	O
,	O
NEC	O
as	O
VR5000	O
,	O
NKK	O
as	O
the	O
NR5000	O
,	O
and	O
Toshiba	O
as	O
the	O
TX5000	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
was	O
sold	O
to	O
PMC-Sierra	O
when	O
the	O
company	O
acquired	O
QED	O
.	O
</s>
<s>
Derivatives	O
of	O
the	O
R5000	B-General_Concept
are	O
still	O
in	O
production	O
today	O
for	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Users	O
of	O
the	O
R5000	B-General_Concept
in	O
workstation	O
and	O
server	O
computers	O
were	O
Silicon	O
Graphics	O
,	O
Inc	O
.	O
(	O
SGI	O
)	O
and	O
Siemens-Nixdorf	O
.	O
</s>
<s>
SGI	O
used	O
the	O
R5000	B-General_Concept
in	O
their	O
O2	B-Device
and	O
Indy	B-Operating_System
low-end	O
workstations	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
was	O
also	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
such	O
as	O
network	O
routers	O
and	O
high-end	O
printers	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
found	O
its	O
way	O
into	O
the	O
arcade	O
gaming	O
industry	O
,	O
R5000	B-General_Concept
powered	O
mainboards	O
were	O
used	O
by	O
Atari	O
and	O
Midway	O
.	O
</s>
<s>
Initially	O
the	O
Cobalt	B-Application
Qube	I-Application
and	O
Cobalt	B-Application
RaQ	I-Application
used	O
a	O
derivative	O
model	O
,	O
the	O
RM5230	B-General_Concept
and	O
RM5231	B-General_Concept
.	O
</s>
<s>
The	O
Qube	O
2700	O
used	O
the	O
RM5230	B-General_Concept
microprocessor	B-Architecture
,	O
whereas	O
the	O
Qube	O
2	O
used	O
the	O
RM5231	B-General_Concept
.	O
</s>
<s>
The	O
original	O
RaQ	B-Application
systems	O
were	O
equipped	O
with	O
RM5230	B-General_Concept
or	O
RM5231	B-General_Concept
CPUs	O
but	O
later	O
models	O
used	O
AMD	O
K6-2	O
chips	O
and	O
then	O
eventually	O
Intel	O
Pentium	O
III	O
CPUs	O
for	O
the	O
final	O
models	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
was	O
introduced	O
in	O
January	O
1996	O
and	O
failed	O
to	O
achieve	O
200MHz	O
,	O
topping	O
out	O
at	O
180MHz	O
.	O
</s>
<s>
When	O
positioned	O
as	O
a	O
low-end	O
workstation	O
microprocessor	B-Architecture
,	O
the	O
competition	O
included	O
the	O
IBM	O
and	O
Motorola	O
PowerPC	O
604	O
,	O
the	O
HP	O
PA-7300LC	B-General_Concept
and	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
.	O
</s>
<s>
The	O
R5000	B-General_Concept
is	O
a	O
two-way	O
superscalar	B-General_Concept
design	O
that	O
executes	O
instructions	O
in-order	B-General_Concept
.	O
</s>
<s>
The	O
R5000	B-General_Concept
could	O
simultaneously	O
issue	O
an	O
integer	O
and	O
a	O
floating-point	O
instruction	O
.	O
</s>
<s>
It	O
had	O
one	O
simple	O
pipeline	B-General_Concept
for	O
integer	O
instructions	O
and	O
another	O
for	O
floating-point	O
to	O
save	O
transistors	O
and	O
die	O
area	O
to	O
reduce	O
cost	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
did	O
not	O
perform	O
dynamic	B-General_Concept
branch	I-General_Concept
prediction	I-General_Concept
for	O
cost	O
reasons	O
.	O
</s>
<s>
Instead	O
it	O
uses	O
a	O
static	O
approach	O
,	O
utilizing	O
the	O
hints	O
encoded	O
by	O
the	O
compiler	B-Language
in	O
the	O
branch-likely	O
instructions	O
first	O
introduced	O
in	O
the	O
MIPS	O
II	O
architecture	O
to	O
determine	O
how	O
likely	O
a	O
branch	O
is	O
taken	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
had	O
large	O
L1	O
caches	O
,	O
a	O
distinct	O
characteristic	O
of	O
QED	O
,	O
whose	O
designers	O
favored	O
simple	O
designs	O
with	O
large	O
caches	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
had	O
two	O
L1	O
caches	O
,	O
one	O
for	O
instructions	O
and	O
the	O
other	O
for	O
data	O
.	O
</s>
<s>
Instructions	O
were	O
predecoded	O
as	O
they	O
enter	O
the	O
instruction	O
cache	B-General_Concept
by	O
appending	O
four	O
bits	O
to	O
each	O
instruction	O
.	O
</s>
<s>
This	O
assisted	O
superscalar	B-General_Concept
instruction	O
issue	O
by	O
moving	O
some	O
of	O
the	O
dependency	O
and	O
conflict	O
checking	O
out	O
of	O
the	O
critical	O
path	O
.	O
</s>
<s>
The	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
was	O
a	O
fast	O
single-precision	O
(	O
32-bit	O
)	O
design	O
,	O
for	O
reduced	O
cost	O
and	O
to	O
benefit	O
SGI	O
,	O
whose	O
mid-range	O
3D	O
graphics	O
workstations	O
relied	O
mostly	O
on	O
single-precision	O
math	O
for	O
3D	O
graphics	O
applications	O
.	O
</s>
<s>
It	O
was	O
fully	O
pipelined	O
,	O
which	O
made	O
it	O
significantly	O
better	O
than	O
that	O
of	O
the	O
R4700	B-Device
.	O
</s>
<s>
The	O
R5000	B-General_Concept
implements	O
the	O
multiply-add	O
instruction	O
of	O
the	O
MIPS	B-Device
IV	I-Device
ISA	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
had	O
an	O
integrated	O
L2	O
cache	B-General_Concept
controller	O
that	O
supported	O
capacities	O
of	O
512KB	O
,	O
1MB	O
and	O
2MB	O
.	O
</s>
<s>
The	O
L2	O
cache	B-General_Concept
shares	O
the	O
SysAD	O
bus	B-General_Concept
with	O
the	O
external	O
interface	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
was	O
built	O
with	O
custom	O
synchronous	O
SRAMs	O
(	O
SSRAMs	O
)	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
uses	O
the	O
SysAD	O
bus	B-General_Concept
that	O
is	O
also	O
used	O
by	O
several	O
other	O
MIPS	O
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
bus	B-General_Concept
is	O
multiplexed	B-Architecture
(	O
address	O
and	O
data	O
share	O
the	O
same	O
set	O
of	O
wires	O
)	O
and	O
can	O
operate	O
at	O
clock	O
frequencies	O
up	O
to	O
100MHz	O
.	O
</s>
<s>
The	O
initial	O
R5000	B-General_Concept
did	O
not	O
support	O
multiprocessing	B-Operating_System
,	O
but	O
the	O
package	O
reserved	O
eight	O
pins	O
for	O
the	O
future	O
addition	O
of	O
this	O
feature	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
was	O
fabricated	O
by	O
IDT	O
,	O
NEC	O
and	O
NKK	O
.	O
</s>
<s>
All	O
three	O
companies	O
fabricated	O
the	O
R5000	B-General_Concept
in	O
a	O
0.35μm	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	O
,	O
but	O
with	O
different	O
process	O
features	O
.	O
</s>
<s>
IDT	O
fabricated	O
the	O
R5000	B-General_Concept
in	O
a	O
process	O
with	O
two	O
levels	O
of	O
polysilicon	O
and	O
three	O
levels	O
of	O
aluminium	O
interconnect	B-General_Concept
.	O
</s>
<s>
NEC	O
and	O
NKK	O
fabricated	O
the	O
R5000	B-General_Concept
in	O
a	O
process	O
with	O
one	O
level	O
of	O
polysilicon	O
and	O
three	O
levels	O
of	O
aluminium	O
interconnect	B-General_Concept
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
272-ball	O
plastic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
or	O
272-pin	O
plastic	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
.	O
</s>
<s>
It	O
was	O
not	O
pin-compatible	O
with	O
any	O
previous	O
MIPS	O
microprocessor	B-Architecture
.	O
</s>
<s>
In	O
the	O
late	O
1990s	O
,	O
Quantum	O
Effect	O
Design	O
acquired	O
a	O
license	O
to	O
manufacture	O
and	O
sell	O
MIPS	O
microprocessors	B-Architecture
from	O
MTI	O
and	O
became	O
a	O
microprocessor	B-Architecture
vendor	O
,	O
changing	O
its	O
name	O
to	O
Quantum	O
Effect	O
Devices	O
to	O
reflect	O
its	O
new	O
business	O
model	O
.	O
</s>
<s>
The	O
company	O
's	O
first	O
products	O
were	O
members	O
of	O
the	O
RM52xx	O
family	O
,	O
which	O
initially	O
consisted	O
of	O
two	O
models	O
,	O
the	O
RM5230	B-General_Concept
and	O
RM5260	B-General_Concept
.	O
</s>
<s>
The	O
RM5230	B-General_Concept
was	O
initially	O
available	O
at	O
100	O
and	O
133MHz	O
,	O
and	O
the	O
RM5260	B-General_Concept
at	O
133	O
and	O
150MHz	O
.	O
</s>
<s>
On	O
29	O
September	O
1997	O
,	O
new	O
150	O
and	O
175MHz	O
RM5230s	B-General_Concept
were	O
introduced	O
,	O
as	O
were	O
175	O
and	O
200MHz	O
RM5260s	B-General_Concept
.	O
</s>
<s>
Both	O
the	O
RM5230	B-General_Concept
and	O
RM5260	B-General_Concept
are	O
derivatives	O
of	O
the	O
R5000	B-General_Concept
and	O
differ	O
in	O
the	O
size	O
of	O
their	O
primary	O
caches	O
(	O
16KB	O
each	O
instead	O
of	O
32KB	O
)	O
,	O
the	O
width	O
of	O
their	O
system	O
interfaces	O
(	O
the	O
RM5230	B-General_Concept
has	O
a	O
32-bit	O
67MHz	O
SysAD	O
bus	B-General_Concept
,	O
and	O
the	O
RM5260	B-General_Concept
a	O
64-bit	O
75MHz	O
SysAD	O
bus	B-General_Concept
)	O
,	O
and	O
the	O
addition	O
of	O
multiply-add	O
and	O
three-operand	O
multiply	O
instructions	O
for	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
applications	O
.	O
</s>
<s>
These	O
microprocessors	B-Architecture
were	O
fabricated	O
by	O
the	O
Taiwan	O
Semiconductor	O
Manufacturing	O
Company	O
(	O
TSMC	O
)	O
in	O
its	O
0.35μm	O
process	O
with	O
three	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
They	O
were	O
packaged	O
by	O
Amkor	O
Technology	O
in	O
its	O
Power-Quad	O
4	O
packages	O
,	O
the	O
RM5230	B-General_Concept
in	O
a	O
128-pin	O
version	O
,	O
and	O
the	O
RM5260	B-General_Concept
in	O
a	O
208-pin	O
version	O
.	O
</s>
<s>
The	O
RM52xx	O
family	O
was	O
later	O
joined	O
by	O
the	O
RM5270	B-General_Concept
,	O
which	O
was	O
announced	O
at	O
the	O
Embedded	B-Architecture
Systems	I-Architecture
Conference	O
on	O
29	O
September	O
1997	O
.	O
</s>
<s>
Intended	O
for	O
high-end	O
embedded	O
applications	O
,	O
the	O
RM5270	B-General_Concept
was	O
available	O
at	O
150	O
and	O
200MHz	O
.	O
</s>
<s>
Improvements	O
were	O
the	O
addition	O
of	O
an	O
on-chip	O
secondary	B-General_Concept
cache	I-General_Concept
controller	O
that	O
supported	O
up	O
to	O
2MB	O
of	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
SysAD	O
bus	B-General_Concept
is	O
64	O
bits	O
wide	O
and	O
can	O
operate	O
at	O
100MHz	O
.	O
</s>
<s>
The	O
family	O
consisted	O
of	O
the	O
RM5231	B-General_Concept
,	O
RM5261	B-General_Concept
,	O
and	O
RM5271	B-General_Concept
.	O
</s>
<s>
These	O
microprocessors	B-Architecture
were	O
derivatives	O
of	O
the	O
corresponding	O
devices	O
from	O
the	O
RM52x0	O
family	O
fabricated	O
in	O
a	O
0.25μm	O
process	O
with	O
four	O
levels	O
of	O
metal	O
.	O
</s>
<s>
The	O
RM5231	B-General_Concept
was	O
initially	O
available	O
at	O
150	O
,	O
200	O
,	O
and	O
250MHz	O
;	O
whereas	O
the	O
RM5261	B-General_Concept
and	O
RM5271	B-General_Concept
were	O
available	O
at	O
250	O
and	O
266MHz	O
.	O
</s>
<s>
On	O
6	O
July	O
1999	O
,	O
a	O
300MHz	O
RM5271	B-General_Concept
was	O
introduced	O
,	O
priced	O
at	O
US$140	O
in	O
quantities	O
of	O
10,000	O
.	O
</s>
<s>
The	O
RM52x1	O
improved	O
upon	O
the	O
previous	O
family	O
with	O
larger	O
32KB	O
primary	O
caches	O
and	O
a	O
faster	O
SysAD	O
bus	B-General_Concept
that	O
supported	O
clock	O
rates	O
up	O
to	O
125MHz	O
.	O
</s>
<s>
These	O
microprocessors	B-Architecture
were	O
fabricated	O
by	O
TSMC	O
in	O
its	O
0.18μm	O
process	O
and	O
differ	O
from	O
the	O
previous	O
devices	O
by	O
featuring	O
higher	O
clock	O
rates	O
and	O
lower	O
power	O
consumption	O
.	O
</s>
<s>
R5900	O
used	O
in	O
Sony	O
's	O
PlayStation	B-Device
2	I-Device
is	O
a	O
modified	O
version	O
of	O
R5000	B-General_Concept
CPU	O
dubbed	O
the	O
Emotion	B-Architecture
Engine	I-Architecture
with	O
a	O
customized	O
instruction/data	O
cache	O
arrangement	O
and	O
Sony	O
's	O
proprietary	O
107	O
vector	O
SIMD	O
Multimedia	O
Extensions(MMI )	O
.	O
</s>
<s>
Its	O
custom	O
FPU	O
is	O
not	O
IEEE	O
754	O
compliant	O
unlike	O
FPUs	O
used	O
by	O
R5000	B-General_Concept
.	O
</s>
