<s>
The	O
R4200	B-Device
is	O
a	O
microprocessor	B-Architecture
designed	O
by	O
MIPS	O
Technologies	O
,	O
Inc	O
.	O
(	O
MTI	O
)	O
that	O
implemented	O
the	O
MIPS	B-Device
III	I-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
was	O
licensed	O
to	O
NEC	O
,	O
and	O
the	O
company	O
fabricated	O
and	O
marketed	O
it	O
as	O
the	O
VR4200	O
.	O
</s>
<s>
The	O
R4200	B-Device
was	O
at	O
least	O
in	O
part	O
intended	O
for	O
use	O
in	O
low-power	O
Windows	B-Device
NT	I-Device
computers	O
such	O
as	O
personal	O
computers	O
and	O
laptops	O
,	O
reportedly	O
offering	O
"	O
Pentium	B-General_Concept
processor	O
performance	O
at	O
a	O
tenth	O
of	O
the	O
price	O
"	O
,	O
having	O
initially	O
aimed	O
to	O
deliver	O
twice	O
the	O
performance	O
of	O
a	O
66MHz	O
Intel	O
486DX2	B-Device
processor	O
.	O
</s>
<s>
Reported	O
SPECint	O
benchmark	O
results	O
put	O
the	O
microprocessor	B-Architecture
's	O
integer	O
performance	O
at	O
around	O
85%	O
of	O
a	O
P5-variant	O
Pentium	B-General_Concept
microprocessor	B-Architecture
,	O
with	O
floating-point	B-Algorithm
performance	O
being	O
about	O
half	O
that	O
of	O
the	O
Pentium	B-General_Concept
.	O
</s>
<s>
Expected	O
to	O
be	O
used	O
in	O
Nintendo	O
's	O
"	O
new	O
machine	O
due	O
in	O
1995	O
"	O
,	O
the	O
R4300i	O
variant	O
was	O
used	O
in	O
the	O
widely	O
popular	O
Nintendo	B-Architecture
64	I-Architecture
video	B-Device
game	I-Device
console	I-Device
and	O
obscure	O
upgrades	O
,	O
SNK	O
Hyper	B-Application
Neo	I-Application
Geo	I-Application
64	I-Application
arcade	O
board	O
.	O
</s>
<s>
The	O
R4200	B-Device
ultimately	O
did	O
not	O
see	O
any	O
use	O
in	O
personal	O
computers	O
and	O
was	O
repositioned	O
as	O
an	O
embedded	B-Architecture
microprocessor	I-Architecture
that	O
competed	O
with	O
the	O
R4600	B-Device
.	O
</s>
<s>
The	O
R4200	B-Device
is	O
a	O
scalar	B-General_Concept
design	O
with	O
a	O
five-stage	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
A	O
notable	O
feature	O
is	O
the	O
use	O
of	O
the	O
integer	O
datapath	B-General_Concept
for	O
performing	O
arithmetic	O
operations	O
on	O
the	O
mantissa	B-Algorithm
portion	O
of	O
a	O
floating	B-Algorithm
point	I-Algorithm
number	I-Algorithm
.	O
</s>
<s>
A	O
separate	O
datapath	B-General_Concept
was	O
used	O
for	O
the	O
exponent	O
.	O
</s>
<s>
This	O
scheme	O
reduced	O
cost	O
by	O
reducing	O
the	O
number	O
of	O
transistors	B-Application
,	O
the	O
size	O
of	O
the	O
chip	O
,	O
and	O
power	O
consumption	O
.	O
</s>
<s>
It	O
also	O
impacted	O
floating	B-Algorithm
point	I-Algorithm
performance	O
negatively	O
,	O
but	O
the	O
R4200	B-Device
's	O
intended	O
applications	O
did	O
not	O
require	O
high	O
floating	B-Algorithm
point	I-Algorithm
performance	O
.	O
</s>
<s>
The	O
R4200	B-Device
has	O
a	O
16KB	O
instruction	O
cache	B-General_Concept
and	O
an	O
8KB	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
instruction	O
cache	B-General_Concept
has	O
a	O
32-byte	O
line	O
size	O
,	O
whereas	O
the	O
data	B-General_Concept
cache	I-General_Concept
has	O
16-byte	O
line	O
size	O
.	O
</s>
<s>
The	O
data	B-General_Concept
cache	I-General_Concept
uses	O
the	O
write-back	O
write	O
protocol	O
.	O
</s>
<s>
The	O
R4200	B-Device
has	O
a	O
32-entry	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
for	O
data	O
,	O
and	O
a	O
4-entry	O
TLB	O
for	O
instructions	O
.	O
</s>
<s>
A	O
33-bit	O
physical	B-General_Concept
address	I-General_Concept
is	O
supported	O
.	O
</s>
<s>
The	O
system	B-Architecture
bus	I-Architecture
is	O
64	O
bits	O
wide	O
and	O
operates	O
at	O
half	O
the	O
internal	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
R4200	B-Device
contained	O
1.3	O
million	O
transistors	B-Application
and	O
had	O
an	O
area	O
of	O
81mm2	O
.	O
</s>
<s>
NEC	O
fabricated	O
the	O
R4200	B-Device
in	O
a	O
600	B-Algorithm
nm	I-Algorithm
CMOS	B-Device
process	O
with	O
three	O
levels	O
of	O
interconnect	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
179-pin	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
that	O
was	O
compatible	O
with	O
the	O
R4x00PC	B-General_Concept
and	O
R4600	B-Device
,	O
or	O
a	O
208-pin	O
plastic	O
quad	O
flat	O
pack	O
(	O
PQFP	O
)	O
.	O
</s>
<s>
In	O
comparison	O
to	O
the	O
Pentium	B-General_Concept
,	O
SPECint	O
ratings	O
had	O
the	O
Pentium	B-General_Concept
at	O
64.5	O
and	O
the	O
R4200	B-Device
at	O
55	O
.	O
</s>
<s>
SPECfp	O
ratings	O
had	O
the	O
Pentium	B-General_Concept
at	O
56	O
versus	O
the	O
R4200	B-Device
at	O
30	O
.	O
</s>
<s>
The	O
R4300i	O
is	O
a	O
derivative	O
of	O
the	O
R4200	B-Device
designed	O
by	O
MTI	O
for	O
embedded	O
applications	O
announced	O
on	O
17	O
April	O
1995	O
.	O
</s>
<s>
It	O
differs	O
from	O
the	O
R4200	B-Device
by	O
featuring	O
an	O
improved	O
integer	O
multiplier	O
with	O
a	O
lower	O
latency	O
and	O
a	O
cut-down	O
32-bit	O
system	B-Architecture
bus	I-Architecture
for	O
reduced	O
cost	O
.	O
</s>
<s>
A	O
derivative	O
of	O
the	O
VR4300	O
was	O
developed	O
by	O
NEC	O
for	O
the	O
Nintendo	B-Architecture
64	I-Architecture
game	O
console	O
,	O
clocked	O
at	O
93.75MHz	O
and	O
labeled	O
NUS-CPU	O
.	O
</s>
<s>
Although	O
development	O
boards	O
for	O
the	O
Nintendo	B-Architecture
64	I-Architecture
used	O
stock	O
NEC	O
VR4300	O
CPUs	O
,	O
the	O
final	O
CPU	O
has	O
been	O
found	O
to	O
be	O
not	O
pin-compatible	O
.	O
</s>
<s>
NEC	O
produced	O
two	O
other	O
derivatives	O
of	O
the	O
R4300	B-Device
for	O
the	O
general	O
embedded	O
market	O
,	O
the	O
VR4305	O
and	O
VR4310	O
,	O
announced	O
on	O
20	O
January	O
1998	O
.	O
</s>
