<s>
The	O
R4000	B-General_Concept
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
MIPS	O
Computer	O
Systems	O
that	O
implements	O
the	O
MIPS	O
III	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
Officially	O
announced	O
on	O
1	O
October	O
1991	O
,	O
it	O
was	O
one	O
of	O
the	O
first	O
64-bit	O
microprocessors	B-Architecture
and	O
the	O
first	O
MIPS	O
III	O
implementation	O
.	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
when	O
RISC	B-Architecture
microprocessors	B-Architecture
were	O
expected	O
to	O
replace	O
CISC	O
microprocessors	B-Architecture
such	O
as	O
the	O
Intel	B-General_Concept
i486	I-General_Concept
,	O
the	O
R4000	B-General_Concept
was	O
selected	O
to	O
be	O
the	O
microprocessor	B-Architecture
of	O
the	O
Advanced	B-Device
Computing	I-Device
Environment	I-Device
(	O
ACE	O
)	O
,	O
an	O
industry	O
standard	O
that	O
intended	O
to	O
define	O
a	O
common	O
RISC	B-Architecture
platform	O
.	O
</s>
<s>
ACE	O
ultimately	O
failed	O
for	O
a	O
number	O
of	O
reasons	O
,	O
but	O
the	O
R4000	B-General_Concept
found	O
success	O
in	O
the	O
workstation	O
and	O
server	O
markets	O
.	O
</s>
<s>
There	O
are	O
three	O
configurations	O
of	O
the	O
R4000	B-General_Concept
:	O
the	O
R4000PC	O
,	O
an	O
entry-level	O
model	O
with	O
no	O
support	O
for	O
a	O
secondary	O
cache	O
;	O
the	O
R4000SC	O
,	O
a	O
model	O
with	O
secondary	O
cache	O
but	O
no	O
multiprocessor	O
capability	O
;	O
and	O
the	O
R4000MC	O
,	O
a	O
model	O
with	O
secondary	O
cache	O
and	O
support	O
for	O
the	O
cache	B-General_Concept
coherency	I-General_Concept
protocols	O
required	O
by	O
multiprocessor	O
systems	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
is	O
a	O
scalar	B-General_Concept
superpipelined	B-General_Concept
microprocessor	B-Architecture
with	O
an	O
eight-stage	O
integer	O
pipeline	O
.	O
</s>
<s>
During	O
the	O
first	O
stage	O
(	O
IF	O
)	O
,	O
a	O
virtual	B-General_Concept
address	I-General_Concept
for	O
an	O
instruction	O
is	O
generated	O
and	O
the	O
instruction	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
begins	O
the	O
translation	O
of	O
the	O
address	O
to	O
a	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
During	O
the	O
third	O
stage	O
(	O
RF	O
)	O
,	O
the	O
instruction	O
is	O
decoded	O
and	O
the	O
register	B-General_Concept
file	I-General_Concept
is	O
read	O
.	O
</s>
<s>
The	O
MIPS	O
III	O
defines	O
two	O
register	B-General_Concept
files	I-General_Concept
,	O
one	O
for	O
the	O
integer	O
unit	O
and	O
the	O
other	O
for	O
floating-point	O
.	O
</s>
<s>
Each	O
register	B-General_Concept
file	I-General_Concept
is	O
64	O
bits	O
wide	O
and	O
contained	O
32	O
entries	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
has	O
two	O
read	O
ports	O
and	O
one	O
write	O
port	O
,	O
while	O
the	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
has	O
two	O
read	O
ports	O
and	O
two	O
write	O
ports	O
.	O
</s>
<s>
Execution	O
begins	O
at	O
stage	O
four	O
(	O
EX	O
)	O
for	O
both	O
integer	O
and	O
floating-point	O
instructions	O
;	O
and	O
is	O
written	O
back	O
to	O
the	O
register	B-General_Concept
files	I-General_Concept
when	O
completed	O
in	O
stage	O
eight	O
(	O
WB	O
)	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
has	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
,	O
a	O
shifter	O
,	O
multiplier	O
and	O
divider	O
and	O
load	O
aligner	O
for	O
executing	O
integer	O
instructions	O
.	O
</s>
<s>
Load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
are	O
executed	O
by	O
the	O
integer	O
pipeline	O
,	O
and	O
access	O
the	O
on-chip	O
8KB	O
data	O
cache	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
has	O
an	O
on-die	O
IEEE	O
754-1985-compliant	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
referred	O
to	O
as	O
the	O
R4010	O
.	O
</s>
<s>
It	O
is	O
clocked	O
at	O
twice	O
the	O
clock	O
frequency	O
of	O
the	O
microprocessor	B-Architecture
for	O
adequate	O
performance	O
and	O
uses	O
dynamic	B-General_Concept
logic	I-General_Concept
to	O
achieve	O
the	O
high	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
uses	O
a	O
48-entry	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
to	O
translate	O
virtual	O
addresses	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
uses	O
a	O
64-bit	O
virtual	B-General_Concept
address	I-General_Concept
,	O
but	O
only	O
implements	O
40	O
of	O
the	O
64	O
bits	O
,	O
allowing	O
1	O
TB	O
of	O
virtual	B-Architecture
memory	I-Architecture
;	O
the	O
remaining	O
bits	O
are	O
checked	O
to	O
ensure	O
that	O
they	O
contain	O
zero	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
uses	O
a	O
36-bit	O
physical	B-General_Concept
address	I-General_Concept
,	O
thus	O
is	O
able	O
to	O
address	O
64GB	O
of	O
physical	O
memory	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
(	O
SC	O
and	O
MC	O
configurations	O
only	O
)	O
supports	O
an	O
external	O
secondary	O
cache	O
with	O
a	O
capacity	O
of	O
128KB	O
to	O
4MB	O
.	O
</s>
<s>
The	O
cache	O
is	O
built	O
from	O
standard	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
uses	O
a	O
64-bit	O
system	O
bus	O
called	O
the	O
SysAD	O
bus	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
contains	O
1.2	O
million	O
transistors	O
.	O
</s>
<s>
It	O
was	O
designed	O
for	O
a	O
1.0μm	O
two-layer	O
metal	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	O
.	O
</s>
<s>
As	O
MIPS	O
was	O
a	O
fabless	B-Algorithm
company	O
,	O
the	O
R4000	B-General_Concept
was	O
fabricated	O
by	O
partners	O
in	O
their	O
own	O
processes	O
,	O
which	O
had	O
a	O
0.8μm	O
minimum	O
feature	O
size	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
generates	O
the	O
various	O
clock	O
signals	O
from	O
a	O
master	O
clock	O
signal	O
generated	O
externally	O
.	O
</s>
<s>
For	O
the	O
operating	O
frequency	O
,	O
the	O
R4000	B-General_Concept
multiplies	O
the	O
master	O
clock	O
signal	O
by	O
two	O
by	O
use	O
of	O
an	O
on-die	O
phase-locked	O
loop	O
(	O
PLL	O
)	O
.	O
</s>
<s>
The	O
R4000PC	O
is	O
packaged	O
in	O
a	O
179-pin	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CPGA	O
)	O
.	O
</s>
<s>
The	O
R4000SC	O
and	O
R4000MC	O
are	O
packaged	O
in	O
a	O
447-pin	O
ceramic	O
staggered	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
SPGA	B-Algorithm
)	O
.	O
</s>
<s>
The	O
pin	O
out	O
of	O
the	O
R4000MC	O
is	O
different	O
from	O
the	O
R4000SC	O
,	O
with	O
some	O
pins	O
which	O
are	O
unused	O
on	O
the	O
R4000SC	O
used	O
for	O
signals	O
to	O
implement	O
cache	B-General_Concept
coherency	I-General_Concept
on	O
the	O
R4000MC	O
.	O
</s>
<s>
The	O
pin-out	O
of	O
the	O
R4000PC	O
is	O
similar	O
to	O
that	O
of	O
the	O
PGA-packaged	O
R4200	B-Device
and	O
R4600	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
This	O
characteristic	O
enables	O
a	O
properly	O
designed	O
system	O
to	O
use	O
any	O
of	O
the	O
three	O
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
R4400	B-General_Concept
is	O
a	O
further	O
development	O
of	O
the	O
R4000	B-General_Concept
.	O
</s>
<s>
Samples	O
of	O
the	O
microprocessor	B-Architecture
had	O
been	O
shipped	O
to	O
selected	O
customers	O
before	O
then	O
,	O
with	O
general	O
availability	O
in	O
January	O
1993	O
.	O
</s>
<s>
The	O
R4400	B-General_Concept
operates	O
at	O
clock	O
frequencies	O
of	O
100	O
,	O
133	O
,	O
150	O
,	O
200	O
,	O
and	O
250MHz	O
.	O
</s>
<s>
The	O
only	O
major	O
improvement	O
from	O
the	O
R4000	B-General_Concept
is	O
larger	O
primary	O
caches	O
,	O
which	O
were	O
doubled	O
in	O
capacity	O
to	O
16KB	O
each	O
from	O
8KB	O
each	O
.	O
</s>
<s>
The	O
R4400	B-General_Concept
was	O
licensed	O
by	O
Integrated	O
Device	O
Technology	O
(	O
IDT	O
)	O
,	O
LSI	O
Logic	O
,	O
NEC	O
,	O
Performance	O
Semiconductor	O
,	O
Siemens	O
AG	O
and	O
Toshiba	O
.	O
</s>
<s>
IDT	O
,	O
NEC	O
,	O
Siemens	O
and	O
Toshiba	O
fabricated	O
and	O
marketed	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
LSI	O
Logic	O
used	O
the	O
R4400	B-General_Concept
in	O
custom	O
products	O
.	O
</s>
<s>
Performance	O
Semiconductor	O
sold	O
their	O
logic	O
division	O
to	O
Cypress	O
Semiconductor	O
where	O
the	O
MIPS	O
microprocessor	B-Architecture
products	O
were	O
discontinued	O
.	O
</s>
<s>
NEC	O
also	O
produced	O
the	O
MR4401	O
,	O
a	O
ceramic	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
that	O
contained	O
a	O
VR4400SC	O
with	O
ten	O
1Mbit	O
SRAM	O
chips	O
that	O
implemented	O
a	O
1MB	O
secondary	O
cache	O
.	O
</s>
<s>
The	O
R4400	B-General_Concept
is	O
used	O
by	O
:	O
</s>
<s>
The	O
R4000	B-General_Concept
and	O
R4400	B-General_Concept
microprocessors	B-Architecture
were	O
interfaced	O
to	O
the	O
system	O
by	O
custom	O
ASICs	O
or	O
by	O
commercially	O
available	O
chipsets	O
.	O
</s>
<s>
Commercial	O
chipsets	O
were	O
developed	O
,	O
fabricated	O
and	O
marketed	O
by	O
companies	O
such	O
as	O
Toshiba	O
with	O
their	O
the	O
Tiger	O
Shark	O
chipset	O
,	O
which	O
provided	O
a	O
i486-compatible	O
bus	O
.	O
</s>
