<s>
The	O
R2000	B-Device
is	O
a	O
32-bit	O
microprocessor	B-Architecture
chip	O
set	O
developed	O
by	O
MIPS	O
Computer	O
Systems	O
that	O
implemented	O
the	O
MIPS	O
I	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
Introduced	O
in	O
January	O
1986	O
,	O
it	O
was	O
the	O
first	O
commercial	O
implementation	O
of	O
the	O
MIPS	O
architecture	O
and	O
the	O
first	O
commercial	O
RISC	B-Architecture
processor	I-Architecture
available	O
to	O
all	O
companies	O
.	O
</s>
<s>
The	O
R2000	B-Device
competed	O
with	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
VAX	B-Device
minicomputers	O
and	O
with	O
Motorola	B-Device
68000	I-Device
and	O
Intel	O
Corporation	O
80386	B-General_Concept
microprocessors	B-Architecture
.	O
</s>
<s>
R2000	B-Device
users	O
included	O
Ardent	O
Computer	O
,	O
DEC	O
,	O
Silicon	O
Graphics	O
,	O
Northern	O
Telecom	O
and	O
MIPS	O
's	O
own	O
Unix	O
workstations	O
.	O
</s>
<s>
The	O
chip	O
set	O
consisted	O
of	O
the	O
R2000	B-Device
microprocessor	I-Device
,	O
R2010	O
floating-point	O
accelerator	O
,	O
and	O
four	O
R2020	O
write	O
buffer	O
chips	O
.	O
</s>
<s>
The	O
core	O
R2000	B-Device
chip	O
executed	O
all	O
non-floating-point	O
instructions	O
with	O
a	O
simple	O
short	O
pipeline	O
.	O
</s>
<s>
The	O
R2000	B-Device
chip	O
contained	O
a	O
small	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
for	O
mapping	O
virtual	O
memory	O
addresses	O
.	O
</s>
<s>
But	O
the	O
R2020	O
chips	O
queued	O
and	O
completed	O
up	O
to	O
4	O
pending	O
writes	O
to	O
main	O
memory	O
,	O
allowing	O
the	O
R2000	B-Device
core	O
to	O
proceed	O
without	O
stalling	O
itself	O
.	O
</s>
<s>
This	O
was	O
much	O
faster	O
than	O
non-RISC	O
microprocessors	B-Architecture
of	O
that	O
time	O
which	O
needed	O
several	O
cycles	O
per	O
instruction	O
.	O
</s>
<s>
1986	O
also	O
saw	O
similar	O
technology	O
in	O
Sun	O
's	O
first	O
SPARC	B-Architecture
microprocessor	B-Architecture
and	O
Hewlett	O
Packard	O
's	O
first	O
PA-RISC	B-Device
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
R2000	B-Device
chip	O
set	O
and	O
SRAM	O
was	O
initially	O
sold	O
only	O
as	O
a	O
complete	O
circuit	O
board	O
to	O
ensure	O
good	O
cache	O
bus	O
timings	O
.	O
</s>
<s>
The	O
R2000	B-Device
was	O
available	O
in	O
8.3	O
,	O
12.5	O
and	O
15MHz	O
grades	O
.	O
</s>
<s>
MIPS	O
was	O
a	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
,	O
that	O
is	O
,	O
they	O
did	O
not	O
have	O
the	O
capability	O
to	O
fabricate	O
integrated	O
circuits	O
.	O
</s>
<s>
In	O
December	O
1987	O
,	O
MIPS	O
licensed	O
Integrated	O
Device	O
Technology	O
,	O
LSI	O
Logic	O
,	O
and	O
Performance	O
Semiconductor	O
to	O
also	O
fabricate	O
and	O
market	O
the	O
R2000	B-Device
.	O
</s>
<s>
In	O
1988	O
,	O
an	O
improved	O
version	O
was	O
introduced	O
,	O
the	O
R2000A	B-Device
.	O
</s>
<s>
It	O
was	O
composed	O
of	O
the	O
R2000A	B-Device
and	O
R2010A	O
ICs	O
.	O
</s>
<s>
In	O
1988	O
,	O
the	O
R2000	B-Device
was	O
followed	O
by	O
the	O
R3000	B-Device
,	O
using	O
a	O
similar	O
overall	O
system	O
design	O
but	O
faster	O
chip	O
implementation	O
.	O
</s>
