<s>
The	O
R10000	B-General_Concept
,	O
code-named	O
"	O
T5	O
"	O
,	O
is	O
a	O
RISC	B-Architecture
microprocessor	O
implementation	O
of	O
the	O
MIPS	O
IV	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
MIPS	O
Technologies	O
,	O
Inc	O
.	O
(	O
MTI	O
)	O
,	O
then	O
a	O
division	O
of	O
Silicon	O
Graphics	O
,	O
Inc	O
.	O
(	O
SGI	O
)	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
microarchitecture	B-General_Concept
is	O
known	O
as	O
ANDES	O
,	O
an	O
abbreviation	O
for	O
Architecture	B-General_Concept
with	I-General_Concept
Non-sequential	I-General_Concept
Dynamic	I-General_Concept
Execution	I-General_Concept
Scheduling	I-General_Concept
.	O
</s>
<s>
The	O
R10000	B-General_Concept
largely	O
replaces	O
the	O
R8000	B-General_Concept
in	O
the	O
high-end	O
and	O
the	O
R4400	O
elsewhere	O
.	O
</s>
<s>
MTI	O
was	O
a	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
;	O
the	O
R10000	B-General_Concept
was	O
fabricated	O
by	O
NEC	O
and	O
Toshiba	O
.	O
</s>
<s>
Previous	O
fabricators	O
of	O
MIPS	O
microprocessors	O
such	O
as	O
Integrated	O
Device	O
Technology	O
(	O
IDT	O
)	O
and	O
three	O
others	O
did	O
not	O
fabricate	O
the	O
R10000	B-General_Concept
as	O
it	O
was	O
more	O
expensive	O
to	O
do	O
so	O
than	O
the	O
R4000	O
and	O
R4400	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
was	O
introduced	O
in	O
January	O
1996	O
at	O
clock	O
frequencies	O
of	O
175MHz	O
and	O
195MHz	O
.	O
</s>
<s>
A	O
150MHz	O
version	O
was	O
introduced	O
in	O
the	O
O2	B-Device
product	O
line	O
in	O
1997	O
,	O
but	O
discontinued	O
shortly	O
after	O
due	O
to	O
customer	O
preference	O
for	O
the	O
175MHz	O
version	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
was	O
not	O
available	O
in	O
large	O
volumes	O
until	O
later	O
in	O
the	O
year	O
due	O
to	O
fabrication	O
problems	O
at	O
MIPS	O
's	O
foundries	O
.	O
</s>
<s>
On	O
25	O
September	O
1996	O
,	O
SGI	O
announced	O
that	O
R10000s	B-General_Concept
fabricated	O
by	O
NEC	O
between	O
March	O
and	O
the	O
end	O
of	O
July	O
that	O
year	O
were	O
faulty	O
,	O
drawing	O
too	O
much	O
current	O
and	O
causing	O
systems	O
to	O
shut	O
down	O
during	O
operation	O
.	O
</s>
<s>
SGI	O
recalled	O
10,000	O
R10000s	B-General_Concept
that	O
had	O
shipped	O
in	O
systems	O
as	O
a	O
result	O
,	O
which	O
impacted	O
the	O
company	O
's	O
earnings	O
.	O
</s>
<s>
In	O
1997	O
,	O
a	O
version	O
of	O
R10000	B-General_Concept
fabricated	O
in	O
a	O
0.25µm	O
process	O
enabled	O
the	O
microprocessor	O
to	O
reach	O
250MHz	O
.	O
</s>
<s>
Users	O
of	O
the	O
R10000	B-General_Concept
include	O
:	O
</s>
<s>
The	O
R10000	B-General_Concept
is	O
a	O
four-way	O
superscalar	B-General_Concept
design	O
that	O
implements	O
register	B-Architecture
renaming	I-Architecture
and	O
executes	O
instructions	O
out-of-order	B-General_Concept
.	O
</s>
<s>
Its	O
design	O
is	O
a	O
departure	O
from	O
previous	O
MTI	O
microprocessors	O
such	O
as	O
the	O
R4000	O
,	O
which	O
is	O
a	O
much	O
simpler	O
scalar	B-General_Concept
in-order	O
design	O
that	O
relies	O
largely	O
on	O
high	O
clock	O
rates	O
for	O
performance	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
fetches	O
four	O
instructions	O
every	O
cycle	O
from	O
its	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
These	O
instructions	O
are	O
decoded	O
and	O
then	O
placed	O
into	O
the	O
integer	O
,	O
floating-point	O
or	O
load/store	B-General_Concept
instruction	I-General_Concept
queues	O
depending	O
on	O
the	O
type	O
of	O
the	O
instruction	O
.	O
</s>
<s>
The	O
decode	O
unit	O
is	O
assisted	O
by	O
the	O
pre-decoded	O
instructions	O
from	O
the	O
instruction	O
cache	B-General_Concept
,	O
which	O
append	O
five	O
bits	O
to	O
every	O
instruction	O
to	O
enable	O
the	O
unit	O
to	O
quickly	O
identify	O
which	O
execution	O
unit	O
the	O
instruction	O
is	O
executed	O
in	O
,	O
and	O
rearrange	O
the	O
format	O
of	O
the	O
instruction	O
to	O
optimize	O
the	O
decode	O
process	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
can	O
thus	O
issue	O
up	O
to	O
five	O
instructions	O
every	O
cycle	O
.	O
</s>
<s>
The	O
integer	O
unit	O
consists	O
of	O
the	O
integer	O
register	B-General_Concept
file	I-General_Concept
and	O
three	O
pipelines	O
,	O
two	O
integer	O
,	O
one	O
load	O
store	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
is	O
64	O
bits	O
wide	O
and	O
contains	O
64	O
entries	O
,	O
of	O
which	O
32	O
are	O
architectural	O
registers	O
and	O
32	O
are	O
rename	O
registers	O
which	O
implement	O
register	B-Architecture
renaming	I-Architecture
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
has	O
seven	O
read	O
ports	O
and	O
three	O
write	O
ports	O
.	O
</s>
<s>
However	O
,	O
only	O
the	O
first	O
pipeline	B-General_Concept
has	O
a	O
barrel	O
shifter	O
and	O
hardware	O
for	O
confirming	O
the	O
prediction	O
of	O
conditional	O
branches	O
.	O
</s>
<s>
The	O
second	O
pipeline	B-General_Concept
is	O
used	O
to	O
access	O
the	O
multiplier	O
and	O
divider	O
.	O
</s>
<s>
The	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
consists	O
of	O
four	O
functional	O
units	O
,	O
an	O
adder	O
,	O
a	O
multiplier	O
,	O
divide	O
unit	O
and	O
square	O
root	O
unit	O
.	O
</s>
<s>
The	O
square	O
root	O
unit	O
executes	O
square	O
root	O
and	O
reciprocal	B-Library
square	I-Library
root	I-Library
instructions	O
.	O
</s>
<s>
Reciprocal	B-Library
square	I-Library
roots	I-Library
have	O
longer	O
latencies	O
,	O
30	O
to	O
52	O
cycles	O
for	O
single	O
precision	O
(	O
32-bit	O
)	O
and	O
double	O
precision	O
(	O
64-bit	O
)	O
respectively	O
.	O
</s>
<s>
The	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
contains	O
sixty-four	O
64-bit	O
registers	O
,	O
of	O
which	O
thirty-two	O
are	O
architectural	O
and	O
the	O
remaining	O
are	O
rename	O
registers	O
.	O
</s>
<s>
This	O
instruction	O
is	O
implemented	O
by	O
the	O
R10000	B-General_Concept
with	O
a	O
bypass	O
the	O
result	O
of	O
the	O
multiply	O
can	O
bypass	O
the	O
register	B-General_Concept
file	I-General_Concept
and	O
be	O
delivered	O
to	O
the	O
add	O
pipeline	B-General_Concept
as	O
an	O
operand	O
,	O
thus	O
it	O
is	O
not	O
a	O
fused	O
multiply	O
–	O
add	O
,	O
and	O
has	O
a	O
four-cycle	O
latency	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
has	O
two	O
comparatively	O
large	O
on-chip	B-General_Concept
caches	I-General_Concept
,	O
a	O
32KB	O
instruction	O
cache	B-General_Concept
and	O
a	O
32KB	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
instruction	O
cache	B-General_Concept
is	O
two-way	O
set-associative	O
and	O
has	O
a	O
128-byte	O
line	O
size	O
.	O
</s>
<s>
Instructions	O
are	O
partially	O
decoded	O
by	O
appending	O
four	O
bits	O
to	O
each	O
instruction	O
(	O
which	O
have	O
a	O
length	O
of	O
32	O
bits	O
)	O
before	O
they	O
are	O
placed	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
32KB	O
data	B-General_Concept
cache	I-General_Concept
is	O
dual-ported	O
through	O
two-way	O
interleaving	O
.	O
</s>
<s>
It	O
consists	O
of	O
two	O
16KB	O
banks	O
,	O
and	O
each	O
bank	B-General_Concept
are	O
two-way	O
set-associative	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
has	O
64-byte	O
lines	O
,	O
uses	O
the	O
write-back	O
protocol	O
,	O
and	O
is	O
virtually	O
indexed	O
and	O
physically	O
tagged	O
to	O
enable	O
the	O
cache	B-General_Concept
to	O
be	O
indexed	O
in	O
the	O
same	O
clock	O
cycle	O
and	O
to	O
maintain	O
coherency	B-General_Concept
with	O
the	O
secondary	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
external	O
secondary	O
unified	O
cache	B-General_Concept
supported	O
capacities	O
between	O
512KB	O
and	O
16MB	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
is	O
accessed	O
via	O
its	O
own	O
128-bit	O
bus	B-General_Concept
that	O
is	O
protected	O
by	O
9-bits	O
of	O
error	B-Error_Name
correcting	I-Error_Name
code	I-Error_Name
(	O
ECC	O
)	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
and	O
bus	B-General_Concept
operate	O
at	O
the	O
same	O
clock	O
rate	O
as	O
the	O
R10000	B-General_Concept
,	O
whose	O
maximum	O
frequency	O
was	O
200MHz	O
.	O
</s>
<s>
At	O
200MHz	O
,	O
the	O
bus	B-General_Concept
yielded	O
a	O
peak	O
bandwidth	O
of	O
3.2GB/s	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
is	O
two-way	O
set	O
associative	O
,	O
but	O
to	O
avoid	O
a	O
high	O
pin	O
count	O
,	O
the	O
R10000	B-General_Concept
predicts	O
which	O
way	O
is	O
accessed	O
.	O
</s>
<s>
MIPS	O
IV	O
is	O
a	O
64-bit	O
architecture	O
,	O
but	O
to	O
reduce	O
cost	O
the	O
R10000	B-General_Concept
does	O
not	O
implement	O
the	O
entire	O
physical	O
or	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
Instead	O
,	O
it	O
has	O
a	O
40-bit	O
physical	B-General_Concept
address	I-General_Concept
and	O
a	O
44-bit	O
virtual	B-General_Concept
address	I-General_Concept
,	O
thus	O
it	O
is	O
capable	O
of	O
addressing	O
1	O
TB	O
of	O
physical	O
memory	O
and	O
16	O
TB	O
of	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
The	O
R10000	B-General_Concept
uses	O
the	O
Avalanche	O
bus	B-General_Concept
,	O
a	O
64-bit	O
bus	B-General_Concept
that	O
operates	O
at	O
frequencies	O
up	O
to	O
100MHz	O
.	O
</s>
<s>
Avalanche	O
is	O
a	O
multiplexed	B-Architecture
address	O
and	O
data	B-General_Concept
bus	I-General_Concept
,	O
so	O
at	O
100MHz	O
it	O
yields	O
a	O
maximum	O
theoretical	O
bandwidth	O
of	O
800MB/s	O
,	O
but	O
its	O
peak	O
bandwidth	O
is	O
640MB/s	O
as	O
it	O
requires	O
some	O
cycles	O
to	O
transmit	O
addresses	O
.	O
</s>
<s>
The	O
system	O
interface	O
controller	O
supports	O
glue-less	O
symmetrical	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
of	O
up	O
to	O
four	O
microprocessors	O
.	O
</s>
<s>
Systems	O
using	O
the	O
R10000	B-General_Concept
with	O
external	O
logic	O
can	O
scale	O
to	O
hundreds	O
of	O
processors	O
.	O
</s>
<s>
An	O
example	O
of	O
such	O
a	O
system	O
is	O
the	O
Origin	B-Application
2000	I-Application
.	O
</s>
<s>
The	O
R10000	B-General_Concept
consists	O
of	O
approximately	O
6.8	O
million	O
transistors	O
,	O
of	O
which	O
approximately	O
4.4	O
million	O
are	O
contained	O
in	O
the	O
primary	O
caches	O
.	O
</s>
<s>
It	O
is	O
fabricated	O
in	O
a	O
0.35µm	O
process	O
and	O
packaged	O
in	O
599-pad	O
ceramic	B-Algorithm
land	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
.	O
</s>
<s>
Before	O
the	O
R10000	B-General_Concept
was	O
introduced	O
,	O
the	O
Microprocessor	O
Report	O
,	O
covering	O
the	O
1994	O
Microprocessor	O
Forum	O
,	O
reported	O
that	O
it	O
was	O
packaged	O
in	O
a	O
527-pin	O
ceramic	O
pin	O
grid	O
array	O
(	O
CPGA	O
)	O
;	O
and	O
that	O
vendors	O
also	O
investigated	O
the	O
possibility	O
of	O
using	O
a	O
339-pin	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
containing	O
the	O
microprocessor	O
die	O
and	O
1MB	O
of	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
R10000	B-General_Concept
was	O
extended	O
by	O
multiple	O
successive	O
derivatives	O
.	O
</s>
<s>
All	O
derivatives	O
after	O
the	O
R12000	B-General_Concept
have	O
their	O
clock	O
frequency	O
kept	O
as	O
low	O
as	O
possible	O
to	O
maintain	O
power	O
dissipation	O
in	O
the	O
15	O
to	O
20W	O
range	O
so	O
they	O
can	O
be	O
densely	O
packaged	O
in	O
SGI	O
's	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
(	O
HPC	O
)	O
systems	O
.	O
</s>
<s>
The	O
R12000	B-General_Concept
is	O
a	O
derivative	O
of	O
the	O
R10000	B-General_Concept
started	O
by	O
MIPS	O
and	O
completed	O
by	O
SGI	O
.	O
</s>
<s>
The	O
R12000	B-General_Concept
was	O
developed	O
as	O
a	O
stop-gap	O
solution	O
following	O
the	O
cancellation	O
of	O
the	O
"	O
Beast	O
"	O
project	O
,	O
which	O
intended	O
to	O
deliver	O
a	O
successor	O
to	O
the	O
R10000	B-General_Concept
.	O
</s>
<s>
R12000	B-General_Concept
users	O
include	O
NEC	O
,	O
Siemens-Nixdorf	O
,	O
SGI	O
and	O
Tandem	O
Computers	O
(	O
and	O
later	O
Compaq	O
,	O
after	O
their	O
acquisition	O
of	O
Tandem	O
)	O
.	O
</s>
<s>
The	O
R12000	B-General_Concept
improves	O
upon	O
the	O
R10000	B-General_Concept
microarchitecture	B-General_Concept
by	O
:	O
inserting	O
an	O
extra	O
pipeline	B-General_Concept
stage	O
to	O
improve	O
clock	O
frequency	O
by	O
resolving	O
a	O
critical	O
path	O
;	O
increasing	O
the	O
number	O
of	O
entries	O
in	O
the	O
branch	O
history	O
table	O
,	O
improving	O
prediction	O
;	O
modifying	O
the	O
instruction	O
queues	O
so	O
they	O
take	O
into	O
account	O
the	O
age	O
of	O
a	O
queued	O
instruction	O
,	O
enabling	O
older	O
instructions	O
to	O
be	O
executed	O
before	O
newer	O
ones	O
if	O
possible	O
.	O
</s>
<s>
The	O
R12000	B-General_Concept
was	O
fabricated	O
by	O
NEC	O
and	O
Toshiba	O
in	O
a	O
0.25µm	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
aluminum	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
use	O
of	O
a	O
new	O
process	O
does	O
not	O
mean	O
that	O
the	O
R12000	B-General_Concept
was	O
a	O
simple	O
die	O
shrink	O
with	O
a	O
tweaked	O
microarchitecture	B-General_Concept
;	O
the	O
layout	O
of	O
the	O
die	O
is	O
optimized	O
to	O
take	O
advantage	O
of	O
the	O
0.25µm	O
process	O
.	O
</s>
<s>
The	O
R12000A	B-General_Concept
is	O
a	O
derivative	O
of	O
the	O
R12000	B-General_Concept
developed	O
by	O
SGI	O
.	O
</s>
<s>
Introduced	O
in	O
July	O
2000	O
,	O
it	O
operates	O
at	O
400MHz	O
and	O
was	O
fabricated	O
by	O
NEC	O
a	O
0.18µm	O
process	O
with	O
aluminum	O
interconnects	B-General_Concept
.	O
</s>
<s>
The	O
R14000	B-General_Concept
is	O
a	O
further	O
development	O
of	O
the	O
R12000	B-General_Concept
announced	O
in	O
July	O
2001	O
.	O
</s>
<s>
The	O
R14000	B-General_Concept
operates	O
at	O
500MHz	O
,	O
enabled	O
by	O
the	O
0.13µm	O
CMOS	B-Device
process	O
with	O
five	O
levels	O
of	O
copper	O
interconnect	B-General_Concept
it	O
is	O
fabricated	O
with	O
.	O
</s>
<s>
It	O
features	O
improvements	O
to	O
the	O
microarchitecture	B-General_Concept
of	O
the	O
R12000	B-General_Concept
by	O
supporting	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
SSRAMs	O
for	O
the	O
secondary	B-General_Concept
cache	I-General_Concept
and	O
a	O
200MHz	O
system	O
bus	B-General_Concept
.	O
</s>
<s>
The	O
R14000A	B-General_Concept
is	O
a	O
further	O
development	O
of	O
the	O
R14000	B-General_Concept
announced	O
in	O
February	O
2002	O
.	O
</s>
<s>
It	O
operates	O
at	O
600MHz	O
,	O
dissipates	O
approximately	O
17W	O
,	O
and	O
was	O
fabricated	O
by	O
NEC	O
Corporation	O
in	O
a	O
0.13µm	O
CMOS	B-Device
process	O
with	O
seven	O
levels	O
of	O
copper	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
R16000	B-General_Concept
,	O
code-named	O
"	O
N0	O
"	O
,	O
is	O
the	O
last	O
derivative	O
of	O
the	O
R10000	B-General_Concept
.	O
</s>
<s>
It	O
is	O
developed	O
by	O
SGI	O
and	O
fabricated	O
by	O
NEC	O
in	O
their	O
0.11µm	O
process	O
with	O
eight	O
levels	O
of	O
copper	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
microprocessor	O
was	O
introduced	O
on	O
9	O
January	O
2003	O
,	O
debuting	O
at	O
700MHz	O
for	O
the	O
Fuel	B-Device
and	O
also	O
used	O
in	O
their	O
Onyx4	O
Ultimate	O
Vision	O
.	O
</s>
<s>
In	O
April	O
2003	O
,	O
a	O
600MHz	O
version	O
was	O
introduced	O
for	O
the	O
Origin	B-Application
350	I-Application
.	O
</s>
<s>
Improvements	O
are	O
64KB	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
The	O
R16000A	B-General_Concept
refers	O
to	O
R16000	B-General_Concept
microprocessors	O
with	O
clock	O
rates	O
higher	O
than	O
700MHz	O
.	O
</s>
<s>
The	O
first	O
R16000A	B-General_Concept
is	O
an	O
800MHz	O
version	O
,	O
introduced	O
on	O
4	O
February	O
2004	O
.	O
</s>
<s>
Later	O
,	O
a	O
900MHz	O
version	O
was	O
introduced	O
,	O
and	O
this	O
version	O
was	O
,	O
for	O
some	O
time	O
,	O
the	O
fastest	O
publicly	O
known	O
R16000ASGI	O
later	O
revealed	O
there	O
were	O
1.0GHz	O
R16000s	B-General_Concept
shipped	O
to	O
selected	O
customers	O
.	O
</s>
<s>
R16000	B-General_Concept
users	O
included	O
HP	O
and	O
SGI	O
.	O
</s>
<s>
SGI	O
used	O
the	O
microprocessor	O
in	O
their	O
Fuel	B-Device
and	O
Tezro	B-Device
workstations	O
;	O
and	O
the	O
Origin	O
3000	O
servers	O
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
HP	O
used	O
the	O
R16000A	B-General_Concept
in	O
their	O
NonStop	B-Architecture
Himalaya	I-Architecture
S-Series	I-Architecture
fault-tolerant	O
servers	O
inherited	O
from	O
Tandem	O
via	O
Compaq	O
.	O
</s>
<s>
The	O
R18000	B-General_Concept
is	O
a	O
canceled	O
further	O
development	O
of	O
the	O
R10000	B-General_Concept
microarchitecture	B-General_Concept
that	O
featured	O
major	O
improvements	O
by	O
Silicon	O
Graphics	O
,	O
Inc	O
.	O
described	O
at	O
the	O
Hot	O
Chips	O
symposium	O
in	O
2001	O
.	O
</s>
<s>
The	O
R18000	B-General_Concept
was	O
designed	O
specifically	O
for	O
SGI	O
's	O
ccNUMA	O
servers	O
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
Each	O
node	O
would	O
have	O
two	O
R18000s	B-General_Concept
connected	O
via	O
a	O
multiplexed	B-Architecture
bus	B-General_Concept
to	O
a	O
system	O
controller	O
,	O
which	O
would	O
interface	O
the	O
microprocessors	O
to	O
their	O
local	O
memory	O
and	O
the	O
rest	O
of	O
the	O
system	O
via	O
a	O
hypercube	O
network	O
.	O
</s>
<s>
The	O
R18000	B-General_Concept
improved	O
the	O
floating-point	O
instruction	O
queues	O
and	O
revised	O
the	O
floating-point	B-General_Concept
unit	I-General_Concept
to	O
feature	O
two	O
multiply	O
–	O
add	O
units	O
,	O
quadrupling	O
the	O
peak	O
FLOPS	O
count	O
.	O
</s>
<s>
It	O
would	O
have	O
a	O
52-bit	O
virtual	B-General_Concept
address	I-General_Concept
and	O
a	O
48-bit	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
The	O
bidirectional	O
multiplexed	B-Architecture
address	O
and	O
data	O
system	O
bus	B-General_Concept
of	O
the	O
earlier	O
models	O
would	O
be	O
replaced	O
by	O
two	O
unidirectional	O
DDR	O
links	O
,	O
a	O
64-bit	O
multiplexed	B-Architecture
address	O
and	O
write	O
path	O
and	O
a	O
128-bit	O
read	O
path	O
.	O
</s>
<s>
The	O
paths	O
could	O
be	O
shared	O
with	O
another	O
R18000	B-General_Concept
through	O
multiplexing	B-Architecture
.	O
</s>
<s>
The	O
bus	B-General_Concept
could	O
also	O
be	O
configured	O
in	O
the	O
SysAD	O
or	O
Avalanche	O
configuration	O
for	O
backwards	O
compatibility	O
with	O
R10000	B-General_Concept
systems	O
.	O
</s>
<s>
The	O
R18000	B-General_Concept
would	O
have	O
a	O
1MB	O
four-way	O
set-associative	O
secondary	B-General_Concept
cache	I-General_Concept
to	O
be	O
included	O
on-die	O
;	O
supplemented	O
by	O
an	O
optional	O
tertiary	O
cache	B-General_Concept
built	O
from	O
single	O
data	O
rate	O
(	O
SDR	O
)	O
or	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
SSRAM	O
or	O
DDR	O
SDRAM	O
with	O
capacities	O
of	O
2	O
to	O
64MB	O
.	O
</s>
<s>
The	O
L3	O
cache	B-General_Concept
would	O
have	O
its	O
cache	B-General_Concept
tags	O
,	O
equivalent	O
to	O
400KB	O
,	O
located	O
on-die	O
to	O
reduce	O
latency	O
.	O
</s>
<s>
The	O
L3	O
cache	B-General_Concept
would	O
be	O
accessed	O
via	O
a	O
144-bit	O
bus	B-General_Concept
,	O
of	O
which	O
128	O
bits	O
are	O
for	O
data	O
and	O
16	O
bits	O
for	O
ECC	O
.	O
</s>
<s>
The	O
L3	O
cache	B-General_Concept
's	O
clock	O
rate	O
would	O
be	O
programmable	O
.	O
</s>
<s>
The	O
R18000	B-General_Concept
was	O
to	O
be	O
fabricated	O
in	O
NEC	O
's	O
UX5	O
process	O
,	O
a	O
0.13µm	O
CMOS	B-Device
process	O
with	O
nine	O
levels	O
of	O
copper	O
interconnect	B-General_Concept
.	O
</s>
