<s>
Quilt	B-Algorithm
Packaging	I-Algorithm
(	O
QP	O
)	O
is	O
an	O
integrated	B-Algorithm
circuit	I-Algorithm
packaging	I-Algorithm
and	O
chip-to-chip	O
interconnect	O
packaging	B-Algorithm
technology	O
that	O
utilizes	O
“	O
nodule	O
”	O
structures	O
that	O
extend	O
out	O
horizontally	O
from	O
the	O
edges	O
of	O
microchips	O
to	O
make	O
electrically	O
and	O
mechanically	O
robust	O
chip-to-chip	O
interconnections	O
.	O
</s>
<s>
QP	O
nodules	O
are	O
created	O
as	O
an	O
integral	O
part	O
of	O
the	O
microchip	O
using	O
standard	O
back	B-Algorithm
end	I-Algorithm
of	I-Algorithm
the	I-Algorithm
line	I-Algorithm
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
techniques	O
.	O
</s>
<s>
Small	O
high	O
yielding	O
“	O
chiplets	B-Algorithm
”	O
made	O
from	O
any	O
semiconductor	O
material	O
(	O
Silicon	O
,	O
Gallium	O
Arsenide	O
,	O
Silicon	O
Carbide	O
,	O
Gallium	O
Nitride	O
,	O
etc	O
.	O
</s>
<s>
)	O
,	O
can	O
be	O
“	O
quilted	O
”	O
together	O
to	O
create	O
larger	O
multi-function	O
meta-chip	B-Algorithm
.	O
</s>
<s>
Thus	O
,	O
QP	O
technology	O
can	O
integrate	O
multiple	B-Algorithm
chips	I-Algorithm
with	O
dissimilar	O
technologies	O
or	O
substrate	O
materials	O
in	O
planar	O
,	O
2.5D	B-Architecture
and	I-Architecture
3D	I-Architecture
configurations	O
.	O
</s>
<s>
Loss	O
rapidly	O
improves	O
as	O
the	O
gap	O
approaches	O
zero	O
,	O
which	O
is	O
achievable	O
with	O
Quilt	B-Algorithm
Packaging	I-Algorithm
assembly	O
tolerances	O
.	O
</s>
