<s>
Hexagon	B-General_Concept
is	O
the	O
brand	O
name	O
for	O
a	O
family	O
of	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
products	O
by	O
Qualcomm	O
.	O
</s>
<s>
Hexagon	B-General_Concept
is	O
also	O
known	O
as	O
QDSP6	O
,	O
standing	O
for	O
“	O
sixth	O
generation	O
digital	O
signal	O
processor.	O
”	O
According	O
to	O
Qualcomm	O
,	O
the	O
Hexagon	B-General_Concept
architecture	O
is	O
designed	O
to	O
deliver	O
performance	O
with	O
low	O
power	O
over	O
a	O
variety	O
of	O
applications	O
.	O
</s>
<s>
Each	O
version	O
of	O
Hexagon	B-General_Concept
has	O
an	O
instruction	B-General_Concept
set	I-General_Concept
and	O
a	O
micro-architecture	B-General_Concept
.	O
</s>
<s>
Hexagon	B-General_Concept
is	O
used	O
in	O
Qualcomm	B-Architecture
Snapdragon	I-Architecture
chips	O
,	O
for	O
example	O
in	O
smartphones	O
,	O
cars	O
,	O
wearable	O
devices	O
and	O
other	O
mobile	O
devices	O
and	O
is	O
also	O
used	O
in	O
components	O
of	O
cellular	O
phone	O
networks	O
.	O
</s>
<s>
Computing	O
devices	O
have	O
instruction	B-General_Concept
sets	I-General_Concept
,	O
which	O
are	O
their	O
lowest	O
,	O
most	O
primitive	O
languages	O
.	O
</s>
<s>
Hexagon	B-General_Concept
supports	O
privilege	O
levels	O
.	O
</s>
<s>
Originally	O
,	O
Hexagon	B-General_Concept
instructions	O
operated	O
on	O
integer	O
numbers	O
but	O
not	O
floating	O
point	O
numbers	O
,	O
but	O
in	O
v5	O
floating	O
point	O
support	O
was	O
added	O
.	O
</s>
<s>
The	O
processing	O
unit	O
which	O
handles	O
execution	O
of	O
instructions	O
is	O
capable	O
of	O
in-order	O
dispatching	O
up	O
to	O
4	O
instructions	O
(	O
the	O
packet	O
)	O
to	O
4	O
Execution	B-General_Concept
Units	I-General_Concept
every	O
clock	O
.	O
</s>
<s>
Micro-architecture	B-General_Concept
is	O
the	O
physical	O
structure	O
of	O
a	O
chip	O
or	O
chip	O
component	O
that	O
makes	O
it	O
possible	O
for	O
a	O
device	O
to	O
carry	O
out	O
the	O
instructions	O
.	O
</s>
<s>
A	O
given	O
instruction	B-General_Concept
set	I-General_Concept
can	O
be	O
implemented	O
by	O
a	O
variety	O
of	O
micro-architectures	B-General_Concept
.	O
</s>
<s>
The	O
buses	O
–	O
data	O
transfer	O
channels	O
–	O
for	O
Hexagon	B-General_Concept
devices	O
are	O
32	O
bits	O
wide	O
.	O
</s>
<s>
The	O
Hexagon	B-General_Concept
micro-architecture	B-General_Concept
is	O
multi-threaded	O
,	O
which	O
means	O
that	O
it	O
can	O
simultaneously	O
process	O
more	O
than	O
one	O
stream	O
of	O
instructions	O
,	O
enhancing	O
data	O
processing	O
speed	O
.	O
</s>
<s>
Hexagon	B-General_Concept
supports	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
words	I-General_Concept
,	O
which	O
are	O
groupings	O
of	O
four	O
instructions	O
that	O
can	O
be	O
executed	O
“	O
in	O
parallel.	O
”	O
Parallel	O
execution	O
means	O
that	O
multiple	O
instructions	O
can	O
run	O
simultaneously	O
without	O
one	O
instruction	O
having	O
to	O
complete	O
before	O
the	O
next	O
one	O
starts	O
.	O
</s>
<s>
The	O
Hexagon	B-General_Concept
micro-architecture	B-General_Concept
supports	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
operations	O
,	O
which	O
means	O
that	O
when	O
a	O
Hexagon	B-General_Concept
device	O
receives	O
an	O
instruction	O
,	O
it	O
can	O
carry	O
out	O
the	O
operation	O
on	O
more	O
than	O
one	O
piece	O
of	O
data	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
According	O
to	O
2012	O
estimation	O
,	O
Qualcomm	O
shipped	O
1.2	O
billion	O
DSP	O
cores	B-Architecture
inside	O
its	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoCs	O
)	O
(	O
average	O
2.3	O
DSP	O
core	O
per	O
SoC	O
)	O
in	O
2011	O
,	O
and	O
1.5	O
billion	O
cores	B-Architecture
were	O
planned	O
for	O
2012	O
,	O
making	O
the	O
QDSP6	O
the	O
most	O
shipped	O
architecture	O
of	O
DSP	O
(	O
CEVA	O
had	O
around	O
1	O
billion	O
of	O
DSP	O
cores	B-Architecture
shipped	O
in	O
2011	O
with	O
90%	O
of	O
IP-licensable	O
DSP	O
market	O
)	O
.	O
</s>
<s>
The	O
Hexagon	B-General_Concept
architecture	O
is	O
designed	O
to	O
deliver	O
performance	O
with	O
low	O
power	O
over	O
a	O
variety	O
of	O
applications	O
.	O
</s>
<s>
It	O
has	O
features	O
such	O
as	O
hardware	O
assisted	O
multithreading	B-General_Concept
,	O
privilege	O
levels	O
,	O
Very	B-General_Concept
Long	I-General_Concept
Instruction	I-General_Concept
Word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
,	O
Single	B-Device
Instruction	I-Device
Multiple	I-Device
Data	I-Device
(	O
SIMD	B-Device
)	O
,	O
and	O
instructions	O
geared	O
toward	O
efficient	O
signal	O
processing	O
.	O
</s>
<s>
Hardware	O
multithreading	B-General_Concept
is	O
implemented	O
as	O
barrel	B-Operating_System
temporal	B-Operating_System
multithreading	I-Operating_System
-	O
threads	O
are	O
switched	O
in	O
round-robin	O
fashion	O
each	O
cycle	O
,	O
so	O
the	O
600MHz	O
physical	O
core	O
is	O
presented	O
as	O
three	O
logical	O
200MHz	O
cores	B-Architecture
before	O
V5	O
.	O
</s>
<s>
Hexagon	B-General_Concept
V5	O
switched	O
to	O
dynamic	O
multithreading	B-General_Concept
(	O
DMT	O
)	O
with	O
thread	O
switch	O
on	O
L2	O
misses	O
,	O
interrupt	O
waiting	O
or	O
on	O
special	O
instructions	O
.	O
</s>
<s>
At	O
Hot	O
Chips	O
2013	O
Qualcomm	O
announced	O
details	O
of	O
their	O
Hexagon	B-General_Concept
680	O
DSP	O
.	O
</s>
<s>
Qualcomm	O
announced	O
Hexagon	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
HVX	O
)	O
.	O
</s>
<s>
In	O
March	O
2015	O
Qualcomm	O
announced	O
their	O
Snapdragon	B-Architecture
Neural	O
Processing	O
Engine	O
SDK	O
which	O
allow	O
AI	B-General_Concept
acceleration	I-General_Concept
using	O
the	O
CPU	O
,	O
GPU	O
and	O
Hexagon	B-General_Concept
DSP	O
.	O
</s>
<s>
Qualcomm	O
's	O
Snapdragon	B-Architecture
855	O
contains	O
their	O
4th	O
generation	O
on-device	O
AI	O
engine	O
,	O
which	O
includes	O
the	O
Hexagon	B-General_Concept
690	O
DSP	O
and	O
Hexagon	B-General_Concept
Tensor	O
Accelerator	O
(	O
HTA	O
)	O
for	O
AI	B-General_Concept
acceleration	I-General_Concept
.	O
</s>
<s>
The	O
port	O
of	O
Linux	B-Application
for	O
Hexagon	B-General_Concept
runs	O
under	O
a	O
hypervisor	B-Operating_System
layer	O
(	O
"	O
Hexagon	B-General_Concept
Virtual	O
Machine	O
"	O
)	O
and	O
was	O
merged	O
with	O
the	O
3.2	O
release	O
of	O
the	O
kernel	B-Operating_System
.	O
</s>
<s>
The	O
original	O
hypervisor	B-Operating_System
is	O
closed-source	O
,	O
and	O
in	O
April	O
2013	O
a	O
minimal	O
open-source	O
hypervisor	B-Operating_System
implementation	O
for	O
QDSP6	O
V2	O
and	O
V3	O
,	O
the	O
"	O
Hexagon	B-General_Concept
MiniVM	O
"	O
was	O
released	O
by	O
Qualcomm	O
under	O
a	O
BSD-style	B-Operating_System
license	I-Operating_System
.	O
</s>
<s>
Support	O
for	O
Hexagon	B-General_Concept
was	O
added	O
in	O
3.1	O
release	O
of	O
LLVM	B-Application
by	O
Tony	O
Linthicum	O
.	O
</s>
<s>
Hexagon/HVX	O
V66	O
ISA	O
support	O
was	O
added	O
in	O
8.0.0	O
release	O
of	O
LLVM	B-Application
.	O
</s>
<s>
There	O
is	O
also	O
a	O
non-FSF	O
maintained	O
branch	O
of	O
GCC	B-Application
and	O
binutils	B-Application
.	O
</s>
<s>
Qualcomm	B-General_Concept
Hexagon	I-General_Concept
DSPs	O
have	O
been	O
available	O
in	O
Qualcomm	B-Architecture
Snapdragon	I-Architecture
SoC	I-Architecture
since	O
2006	O
.	O
</s>
<s>
In	O
Snapdragon	B-Architecture
S4	O
(	O
MSM8960	O
and	O
newer	O
)	O
there	O
are	O
three	O
QDSP	O
cores	B-Architecture
,	O
two	O
in	O
the	O
Modem	O
subsystem	O
and	O
one	O
Hexagon	B-General_Concept
core	O
in	O
the	O
Multimedia	O
subsystem	O
.	O
</s>
<s>
Modem	O
cores	B-Architecture
are	O
programmed	O
by	O
Qualcomm	O
only	O
,	O
and	O
only	O
Multimedia	O
core	O
is	O
allowed	O
to	O
be	O
programmed	O
by	O
user	O
.	O
</s>
<s>
In	O
March	O
2016	O
,	O
it	O
was	O
announced	O
that	O
semiconductor	O
company	O
Conexant	O
's	O
AudioSmart	O
audio	O
processing	O
software	O
was	O
being	O
integrated	O
into	O
Qualcomm	O
's	O
Hexagon	B-General_Concept
.	O
</s>
<s>
In	O
May	O
2018	O
wolfSSL	B-Protocol
added	O
support	O
for	O
using	O
Qualcomm	B-General_Concept
Hexagon	I-General_Concept
.	O
</s>
<s>
This	O
is	O
support	O
for	O
running	O
wolfSSL	B-Protocol
crypto	O
operations	O
on	O
the	O
DSP	O
.	O
</s>
<s>
There	O
are	O
six	O
versions	O
of	O
QDSP6	O
architecture	O
released	O
:	O
V1	O
(	O
2006	O
)	O
,	O
V2	O
(	O
2007	O
–	O
2008	O
)	O
,	O
V3	O
(	O
2009	O
)	O
,	O
V4	O
(	O
2010	O
–	O
2011	O
)	O
,	O
QDSP6	O
V5	O
(	O
2013	O
,	O
in	O
Snapdragon	B-Architecture
800	O
)	O
;	O
and	O
QDSP6	O
V6	O
(	O
2016	O
,	O
in	O
Snapdragon	B-Architecture
820	O
)	O
.	O
</s>
<s>
Clock	O
speed	O
of	O
Hexagon	B-General_Concept
varies	O
in	O
400	O
–	O
2000MHz	O
for	O
QDSP6	O
and	O
in	O
256	O
–	O
350MHz	O
for	O
previous	O
generation	O
of	O
the	O
architecture	O
,	O
the	O
QDSP5	O
.	O
</s>
<s>
Both	O
Hexagon	B-General_Concept
(	O
QDSP6	O
)	O
and	O
pre-Hexagon	O
(	O
QDSP5	O
)	O
cores	B-Architecture
are	O
used	O
in	O
modern	O
Qualcomm	O
SoCs	O
,	O
QDSP5	O
mostly	O
in	O
low-end	O
products	O
.	O
</s>
<s>
Modem	O
QDSPs	O
(	O
often	O
pre-Hexagon	O
)	O
are	O
not	O
shown	O
in	O
the	O
table	O
.	O
</s>
<s>
QDSP6	O
(	O
Hexagon	B-General_Concept
)	O
usage	O
:	O
</s>
<s>
Snapdragon	B-Architecture
generation	O
Chipset	O
(	O
SoC	O
)	O
ID	O
QDSP6	O
version	O
DSP	O
frequency	O
,	O
MHz	O
Process	O
node	O
,	O
nm	O
S1	O
QSD8650	O
,	O
QSD8250	O
QDSP6	O
600	O
65	O
S3	O
MSM8660	O
,	O
MSM8260	O
,	O
APQ8060	O
QDSP6	O
(	O
V3	O
?	O
)	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
SoCs	I-Architecture
.	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
200	O
series	O
.	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
400	O
series	O
.	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
600	O
series	O
.	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
700	O
series	O
.	O
</s>
<s>
The	O
different	O
video	O
codecs	B-General_Concept
supported	O
by	O
the	O
Snapdragon	B-Architecture
800	O
series	O
.	O
</s>
<s>
recording	O
colspan	O
=	O
"	O
6	O
"	O
HDR10	B-Device
,	O
</s>
<s>
HDR10+HDR10	O
,	O
HLG	O
,	O
</s>
<s>
This	O
is	O
a	O
single	O
instruction	B-General_Concept
packet	I-General_Concept
from	O
the	O
inner	O
loop	O
of	O
a	O
FFT	O
:	O
</s>
