<s>
Quad	B-Device
data	I-Device
rate	I-Device
(	O
QDR	O
,	O
or	O
quad	O
pumping	B-General_Concept
)	O
is	O
a	O
communication	O
signaling	O
technique	O
wherein	O
data	O
are	O
transmitted	O
at	O
four	O
points	O
in	O
the	O
clock	O
cycle	O
:	O
on	O
the	O
rising	O
and	O
falling	O
edges	O
,	O
and	O
at	O
two	O
intermediate	O
points	O
between	O
them	O
.	O
</s>
<s>
In	O
a	O
quad	B-Device
data	I-Device
rate	I-Device
system	O
,	O
the	O
data	O
lines	O
operate	O
at	O
twice	O
the	O
frequency	O
of	O
the	O
clock	O
signal	O
.	O
</s>
<s>
Quad	B-Device
data	I-Device
rate	I-Device
technology	O
was	O
introduced	O
by	O
Intel	O
in	O
its	O
Willamette-core	O
Pentium	O
4	O
processor	O
,	O
and	O
was	O
subsequently	O
employed	O
in	O
its	O
Atom	B-Device
,	O
Pentium4	O
,	O
Celeron	B-Device
,	O
Pentium	O
D	O
and	O
Core	O
2	O
processor	O
ranges	O
.	O
</s>
<s>
This	O
technology	O
has	O
allowed	O
Intel	O
to	O
produce	O
chipsets	O
and	O
processors	B-General_Concept
that	O
can	O
communicate	O
with	O
each	O
other	O
at	O
data	O
rates	O
expected	O
of	O
the	O
traditional	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
technology	O
running	O
from	O
400MT/s	O
to	O
1600MT/s	O
,	O
while	O
maintaining	O
a	O
lower	O
and	O
thus	O
more	O
stable	O
actual	O
clock	O
frequency	O
of	O
100MHz	O
to	O
400MHz	O
.	O
</s>
<s>
On	O
a	O
modern	O
computer	O
,	O
there	O
may	O
be	O
several	O
CPUs	O
and	O
several	O
I/O	B-General_Concept
devices	I-General_Concept
,	O
all	O
competing	O
for	O
accesses	O
to	O
the	O
memory	O
.	O
</s>
