<s>
Quad	O
Data	O
Rate	O
(	O
QDR	O
)	O
SRAM	O
is	O
a	O
type	O
of	O
static	B-Architecture
RAM	I-Architecture
computer	B-General_Concept
memory	I-General_Concept
that	O
can	O
transfer	O
up	O
to	O
four	O
words	O
of	O
data	O
in	O
each	O
clock	O
cycle	O
.	O
</s>
<s>
Like	O
Double	O
Data-Rate	O
(	O
DDR	O
)	O
SDRAM	O
,	O
QDR	B-General_Concept
SRAM	I-General_Concept
transfers	O
data	O
on	O
both	O
rising	O
and	O
falling	O
edges	O
of	O
the	O
clock	O
signal	O
.	O
</s>
<s>
QDR	B-General_Concept
SRAM	I-General_Concept
uses	O
two	O
clocks	O
,	O
one	O
for	O
read	O
data	O
and	O
one	O
for	O
write	O
data	O
and	O
has	O
separate	O
read	O
and	O
write	O
data	O
buses	O
(	O
also	O
known	O
as	O
Separate	O
I/O	O
)	O
,	O
whereas	O
DDR	O
SRAM	O
uses	O
a	O
single	O
clock	O
and	O
has	O
a	O
single	O
common	O
data	O
bus	O
used	O
for	O
both	O
reads	O
and	O
writes	O
(	O
also	O
known	O
as	O
Common	O
I/O	O
)	O
.	O
</s>
<s>
When	O
all	O
data	O
I/O	O
signals	O
are	O
accounted	O
,	O
QDR	B-General_Concept
SRAM	I-General_Concept
is	O
not	O
2x	O
faster	O
than	O
DDR	O
SRAM	O
but	O
is	O
100%	O
efficient	O
when	O
reads	O
and	O
writes	O
are	O
interleaved	O
.	O
</s>
<s>
QDR	B-General_Concept
SRAM	I-General_Concept
was	O
designed	O
for	O
high-speed	O
communications	O
and	O
networking	B-Architecture
applications	O
,	O
where	O
data	O
throughput	O
is	O
more	O
important	O
than	O
cost	O
,	O
power	O
efficiency	O
or	O
density	O
.	O
</s>
<s>
The	O
technology	O
was	O
created	O
by	O
Micron	O
and	O
Cypress	O
,	O
later	O
followed	O
by	O
IDT	O
,	O
then	O
NEC	O
,	O
Samsung	B-Application
and	O
Renesas	O
.	O
</s>
