<s>
Quadrics	O
was	O
a	O
supercomputer	B-Architecture
company	O
formed	O
in	O
1996	O
as	O
a	O
joint	O
venture	O
between	O
Alenia	O
Spazio	O
and	O
the	O
technical	O
team	O
from	O
Meiko	B-Device
Scientific	I-Device
.	O
</s>
<s>
They	O
produced	O
hardware	O
and	O
software	O
for	O
clustering	B-Architecture
commodity	O
computer	O
systems	O
into	O
massively	B-Operating_System
parallel	I-Operating_System
systems	O
.	O
</s>
<s>
Their	O
highpoint	O
was	O
in	O
June	O
2003	O
when	O
six	O
out	O
of	O
the	O
ten	O
fastest	O
supercomputers	B-Architecture
in	O
the	O
world	O
were	O
based	O
on	O
Quadrics	O
 '	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
Quadrics	O
name	O
was	O
first	O
used	O
in	O
1993	O
for	O
a	O
commercialized	O
version	O
of	O
the	O
APE100	B-Device
SIMD	B-Device
parallel	B-Operating_System
computer	I-Operating_System
produced	O
by	O
Alenia	O
Spazio	O
and	O
originally	O
developed	O
by	O
INFN	O
,	O
the	O
Italian	O
National	O
Institute	O
of	O
Nuclear	O
Physics	O
.	O
</s>
<s>
In	O
1996	O
,	O
a	O
new	O
Alenia	O
subsidiary	O
,	O
Quadrics	O
Supercomputers	B-Architecture
World	O
(	O
QSW	O
)	O
was	O
formed	O
,	O
based	O
in	O
Bristol	O
,	O
UK	O
and	O
Rome	O
,	O
Italy	O
,	O
inheriting	O
the	O
Quadrics	O
SIMD	B-Device
product	O
line	O
and	O
the	O
Meiko	B-Device
CS-2	I-Device
massively	B-Operating_System
parallel	I-Operating_System
supercomputer	B-Architecture
architecture	O
.	O
</s>
<s>
Initially	O
,	O
the	O
new	O
company	O
focussed	O
on	O
the	O
development	O
potential	O
of	O
the	O
CS-2	O
'	O
s	O
processor	O
interconnect	B-General_Concept
technology	O
.	O
</s>
<s>
Their	O
first	O
design	O
was	O
the	O
Elan2	O
network	O
ASIC	O
,	O
intended	O
for	O
use	O
with	O
the	O
UltraSPARC	B-General_Concept
CPU	O
,	O
attached	O
to	O
it	O
using	O
the	O
Ultra	B-Architecture
Port	I-Architecture
Architecture	I-Architecture
(	O
UPA	O
)	O
system	O
bus	O
.	O
</s>
<s>
Plans	O
to	O
introduce	O
the	O
Elan2	O
were	O
later	O
dropped	O
,	O
and	O
a	O
new	O
Elan3	O
hosted	O
on	O
PCI	B-Protocol
introduced	O
instead	O
.	O
</s>
<s>
By	O
the	O
time	O
of	O
its	O
release	O
Elan3	O
had	O
been	O
re-aimed	O
at	O
the	O
Alpha/PCI	O
market	O
instead	O
,	O
after	O
Quadrics	O
had	O
formed	O
a	O
relationship	O
with	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
.	O
</s>
<s>
The	O
combination	O
of	O
Quadrics	O
and	O
Alpha	B-General_Concept
21264	I-General_Concept
(	O
EV6	O
)	O
microprocessors	O
proved	O
very	O
successful	O
,	O
and	O
Digital/Compaq	O
rapidly	O
became	O
one	O
of	O
the	O
world	O
's	O
largest	O
suppliers	O
of	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
machine	O
consisted	O
of	O
2,048	O
AlphaServer	B-Device
SC	O
nodes	O
(	O
which	O
are	O
based	O
on	O
AlphaServer	B-Device
ES45	O
)	O
,	O
each	O
with	O
four	O
1.25GHz	O
Alpha	B-Device
21264A	O
(	O
EV67	O
)	O
microprocessors	O
and	O
two	O
rails	O
of	O
the	O
Quadrics	O
QsNet	B-Architecture
network	O
.	O
</s>
<s>
Quadrics	O
also	O
had	O
success	O
in	O
selling	O
Linux	B-Application
based	O
systems	O
.	O
</s>
<s>
Quadrics	O
 '	O
first	O
Linux	B-Application
based	O
system	O
was	O
installed	O
in	O
June/July	O
2001	O
at	O
SHARCNET	O
.	O
</s>
<s>
Another	O
high-profile	O
Quadrics	O
system	O
was	O
the	O
fastest	O
Linux	B-Architecture
cluster	I-Architecture
in	O
the	O
world	O
called	O
Thunder	O
installed	O
at	O
Lawrence	O
Livermore	O
National	O
Laboratory	O
in	O
2003/2004	O
.	O
</s>
<s>
In	O
2004	O
,	O
Quadrics	O
was	O
selected	O
by	O
Bull	O
for	O
what	O
was	O
the	O
fastest	O
supercomputer	B-Architecture
in	O
Europe	O
:	O
TERA-10	B-Device
at	O
the	O
French	O
CEA	O
:	O
544	O
Bull	O
NovaScale	O
6160	O
computing	O
nodes	O
,	O
each	O
including	O
eight	O
Itanium	O
2	O
processors	O
.	O
</s>
<s>
Quadrics	O
was	O
selected	O
by	O
HP	O
for	O
the	O
upgrade	O
of	O
SHARCNET	O
,	O
the	O
Canadian	O
Cluster	O
of	O
Clusters	O
,	O
with	O
four	O
new	O
high-performance	B-Architecture
computing	I-Architecture
clusters	O
that	O
would	O
increase	O
the	O
network	O
's	O
capacity	O
from	O
1,000	O
to	O
6,000	O
processors	O
.	O
</s>
<s>
The	O
cooperation	O
was	O
to	O
cover	O
the	O
design	O
of	O
a	O
future	O
generations	O
of	O
Quadrics	O
high	O
speed	O
multi	O
gigabit	O
interconnect	B-General_Concept
,	O
and	O
the	O
exploitation	O
of	O
the	O
products	O
in	O
a	O
range	O
of	O
high	O
volume	O
applications	O
.	O
</s>
<s>
Many	O
of	O
Quadrics	O
 '	O
technical	O
staff	O
have	O
since	O
found	O
similar	O
employment	O
in	O
developing	O
HPC	O
networking	O
products	O
with	O
Gnodal	O
,	O
one	O
of	O
the	O
many	O
fabless	B-Algorithm
semiconductor	I-Algorithm
companies	I-Algorithm
based	O
in	O
Bristol	O
in	O
the	O
UK	O
.	O
</s>
<s>
QsNet	B-Architecture
III	O
-	O
HPC	O
interconnect	B-General_Concept
based	O
on	O
the	O
elan5/elite5	O
ASICs	O
(	O
approximately	O
2GB/s	O
each	O
direction	O
and	O
1.3us	O
MPI	O
latency	O
)	O
.	O
</s>
<s>
QsNet	B-Architecture
was	O
a	O
high	O
speed	O
interconnect	B-General_Concept
designed	O
by	O
Quadrics	O
used	O
in	O
high-performance	B-Architecture
computing	I-Architecture
computer	B-Architecture
clusters	I-Architecture
,	O
particularly	O
Linux	B-Application
Beowulf	B-Operating_System
clusters	I-Operating_System
.	O
</s>
<s>
Although	O
it	O
can	O
be	O
used	O
with	O
TCP/IP	O
;	O
like	O
SCI	B-General_Concept
,	O
Myrinet	B-General_Concept
and	O
InfiniBand	B-Architecture
it	O
is	O
usually	O
used	O
with	O
a	O
communication	O
API	B-General_Concept
such	O
as	O
Message	B-Application
Passing	I-Application
Interface	I-Application
(	O
MPI	O
)	O
or	O
SHMEM	B-Operating_System
called	O
from	O
a	O
parallel	B-Operating_System
program	I-Operating_System
.	O
</s>
<s>
The	O
interconnect	B-General_Concept
consists	O
of	O
a	O
PCI	B-Protocol
card	I-Protocol
in	O
each	O
compute	O
node	O
and	O
one	O
or	O
more	O
dedicated	O
switch	O
chassis	O
.	O
</s>
<s>
These	O
are	O
internally	O
linked	O
to	O
form	O
a	O
fat	B-Protocol
tree	I-Protocol
topology	O
.	O
</s>
<s>
Like	O
other	O
interconnects	B-General_Concept
such	O
as	O
Myrinet	B-General_Concept
very	O
large	O
systems	O
can	O
be	O
built	O
by	O
using	O
multiple	O
switch	O
chassis	O
arranged	O
as	O
spine	O
(	O
top-level	O
)	O
and	O
leaf	O
(	O
node-level	O
)	O
switches	O
.	O
</s>
<s>
It	O
was	O
announced	O
in	O
1998	O
and	O
used	O
PCI	B-Protocol
66-64	O
cards	O
that	O
had	O
'	O
elan3	O
 '	O
Custom	O
ASIC	O
on	O
them	O
.	O
</s>
<s>
QsNet	B-Architecture
II	I-Architecture
was	O
the	O
fourth	O
and	O
penultimate	O
generation	O
of	O
Quadrics	O
interconnect	B-General_Concept
family	O
products	O
,	O
and	O
was	O
launched	O
in	O
2003	O
.	O
</s>
<s>
QsNetII	O
interfaced	O
to	O
the	O
host	O
computer	O
through	O
the	O
standard	O
IO	O
PCI-X	O
bus	O
.	O
</s>
<s>
Later	O
versions	O
of	O
the	O
card	O
had	O
PCIe	O
physical	O
interfaces	O
although	O
this	O
was	O
bridged	O
on	O
the	O
card	O
to	O
PCI-X	O
with	O
a	O
performance	O
penalty	O
.	O
</s>
<s>
QsNetII	O
is	O
designed	O
for	O
use	O
within	O
SMP	B-Operating_System
systems	O
multiple	O
,	O
concurrent	B-Operating_System
processes	O
can	O
utilise	O
the	O
network	O
interface	O
without	O
any	O
task	O
switching	O
overhead	O
.	O
</s>
<s>
Local	O
memory	O
on	O
the	O
PCI	B-Protocol
card	I-Protocol
provides	O
storage	O
for	O
buffers	O
,	O
translation	O
tables	O
and	O
I/O	O
adapter	O
code	O
.	O
</s>
<s>
All	O
the	O
PCI	B-Protocol
bandwidth	O
is	O
available	O
to	O
data	O
communication	O
.	O
</s>
<s>
Quadrics	O
QsNetII	O
interconnect	B-General_Concept
like	O
its	O
predecessor	O
QsNet	B-Architecture
uses	O
a	O
'	O
fat	B-Protocol
tree	I-Protocol
 '	O
topology	O
,	O
QsNetII	O
scales	O
up	O
to	O
4096	O
nodes	O
,	O
each	O
node	O
might	O
have	O
multiple	O
CPUs	O
so	O
that	O
systems	O
of	O
>10	O
,	O
000	O
CPUs	O
can	O
be	O
constructed	O
.	O
</s>
<s>
Multiple	O
,	O
parallel	O
QsNet	B-Architecture
networks	O
can	O
be	O
employed	O
in	O
a	O
system	O
to	O
maintain	O
the	O
compute	O
to	O
communications	O
ratio	O
where	O
high	O
CPU	O
count	O
SMP	B-Operating_System
nodes	O
are	O
employed	O
.	O
</s>
<s>
The	O
fat	B-Protocol
tree	I-Protocol
topology	O
is	O
resilient	O
with	O
large	O
amounts	O
of	O
redundancy	O
in	O
the	O
higher	O
levels	O
of	O
the	O
switch	O
.	O
</s>
<s>
Performance	O
depends	O
on	O
platform	O
used	O
and	O
configuration	O
of	O
the	O
system	O
,	O
QsNetII	O
MPI	O
latency	O
on	O
standard	O
AMD	B-General_Concept
Opteron	I-General_Concept
starts	O
at	O
1.22μs	O
;	O
Bandwidth	O
on	O
Intel	O
Xeon	O
Intel	O
64	O
is	O
912MB/s	O
.	O
</s>
<s>
Each	O
line	O
card	O
also	O
had	O
four	O
internal	O
ports	O
that	O
connected	O
the	O
line	O
cards	O
together	O
into	O
a	O
fat	B-Protocol
tree	I-Protocol
configuration	O
.	O
</s>
<s>
Late	O
in	O
2007	O
,	O
the	O
Quadrics	O
management	O
decided	O
to	O
cancel	O
the	O
QsTenG	O
Ethernet	O
developments	O
and	O
concentrate	O
efforts	O
on	O
the	O
QsNet	B-Architecture
product	O
line	O
.	O
</s>
