<s>
QorIQ	B-General_Concept
is	O
a	O
brand	O
of	O
ARM-based	O
and	O
Power	O
ISAbased	O
communications	O
microprocessors	B-Architecture
from	O
NXP	O
Semiconductors	O
(	O
formerly	O
Freescale	O
)	O
.	O
</s>
<s>
It	O
is	O
the	O
evolutionary	O
step	O
from	O
the	O
PowerQUICC	B-General_Concept
platform	O
,	O
and	O
initial	O
products	O
were	O
built	O
around	O
one	O
or	O
more	O
e500mc	B-General_Concept
cores	O
and	O
came	O
in	O
five	O
different	O
product	O
platforms	O
,	O
P1	O
,	O
P2	O
,	O
P3	O
,	O
P4	O
,	O
and	O
P5	O
,	O
segmented	O
by	O
performance	O
and	O
functionality	O
.	O
</s>
<s>
The	O
platform	O
keeps	O
software	O
compatibility	O
with	O
older	O
PowerPC	B-Architecture
products	O
such	O
as	O
the	O
PowerQUICC	B-General_Concept
platform	O
.	O
</s>
<s>
In	O
2012	O
Freescale	O
announced	O
ARM-based	O
QorIQ	B-General_Concept
offerings	O
beginning	O
in	O
2013	O
.	O
</s>
<s>
The	O
QorIQ	B-General_Concept
brand	O
and	O
the	O
P1	O
,	O
P2	O
and	O
P4	O
product	O
families	O
were	O
announced	O
in	O
June	O
2008	O
.	O
</s>
<s>
QorIQ	B-General_Concept
P	O
Series	O
processors	O
were	O
manufactured	O
on	O
a	O
45	B-Algorithm
nm	I-Algorithm
fabrication	B-Architecture
process	I-Architecture
and	O
was	O
available	O
in	O
the	O
end	O
of	O
2008	O
(	O
P1	O
and	O
P2	O
)	O
,	O
mid-2009	O
(	O
P4	O
)	O
and	O
2010	O
(	O
P5	O
)	O
.	O
</s>
<s>
QorIQ	B-General_Concept
T	O
Series	O
is	O
based	O
on	O
a	O
28	O
nm	O
process	O
and	O
is	O
pushing	O
a	O
very	O
aggressive	O
power	O
envelope	O
target	O
,	O
capping	O
at	O
30	O
W	O
.	O
These	O
are	O
using	O
the	O
e6500	B-General_Concept
core	I-General_Concept
with	O
AltiVec	B-General_Concept
and	O
are	O
expected	O
to	O
be	O
shipping	O
in	O
2013	O
.	O
</s>
<s>
QorIQ	B-General_Concept
LS-1	O
and	O
LS-2	O
families	O
are	O
ARM	B-Architecture
based	O
processors	O
using	O
the	O
Cortex	B-Application
A7	I-Application
,	O
Cortex	B-Application
A9	I-Application
,	O
A15	O
,	O
A53	O
and	O
A72	O
cores	O
upon	O
the	O
ISA	B-General_Concept
agnostic	O
Layerscape	O
architecture	O
.	O
</s>
<s>
target	O
low	O
and	O
mid	O
range	O
networking	O
and	O
wireless	B-General_Concept
infrastructure	I-General_Concept
applications	O
.	O
</s>
<s>
The	O
Layerscape	O
(	O
LS	O
)	O
architecture	O
is	O
the	O
latest	O
evolution	O
of	O
the	O
QorIQ	B-General_Concept
family	O
,	O
in	O
that	O
features	O
previously	O
provided	O
by	O
DPAA	B-Protocol
(	O
like	O
compression	O
)	O
may	O
be	O
implemented	O
in	O
software	O
or	O
hardware	O
,	O
depending	O
on	O
the	O
specific	O
chip	O
,	O
but	O
transparent	O
to	O
application	O
programmers	O
.	O
</s>
<s>
LS-1	O
and	O
LS-2	O
are	O
announced	O
to	O
use	O
Cortex	B-Application
A7	I-Application
,	O
A9	B-Application
,	O
A15	O
,	O
A53	O
and	O
A72	O
cores	O
.	O
</s>
<s>
The	O
initial	O
LS-1	O
series	O
does	O
not	O
include	O
any	O
accelerated	O
packet	O
processing	O
layer	O
,	O
focusing	O
typical	O
power	O
consumption	O
of	O
less	O
than	O
3W	O
using	O
two	O
Cortex	B-Application
A7	I-Application
with	O
providing	O
ECC	B-Error_Name
for	O
caches	O
and	O
DDR3/4	O
at	O
1000	O
to	O
1600	O
MT/s	O
,	O
dual	O
PCI	O
Express	O
Controllers	O
in	O
x1/x2/x4	O
operation	O
,	O
SD/MMC	O
,	O
SATA	O
1/2/3	O
,	O
USB	O
2/3	O
with	O
integrated	O
PHY	O
,	O
and	O
virtualized	O
dTSEC	O
Gigabit	O
Ethernet	O
Controllers	O
.	O
</s>
<s>
“	O
A	O
”	O
at	O
the	O
end	O
indicates	O
the	O
Arm	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
The	O
LS1	O
family	O
is	O
built	O
on	O
the	O
Layerscape	O
architecture	O
is	O
a	O
programmable	O
data-plane	O
engine	O
networking	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
Both	O
LS1	O
and	O
LS2	O
families	O
of	O
processors	O
offer	O
the	O
advanced	O
,	O
high-performance	O
datapath	B-General_Concept
and	O
network	O
peripheral	O
interfaces	O
.	O
</s>
<s>
These	O
features	O
are	O
frequently	O
required	O
for	O
networking	O
,	O
telecom/datacom	O
,	O
wireless	B-General_Concept
infrastructure	I-General_Concept
,	O
military	O
and	O
aerospace	O
applications	O
.	O
</s>
<s>
The	O
QorIQ	B-General_Concept
P	O
Series	O
processors	O
are	O
based	O
on	O
e500	O
or	O
e5500	B-General_Concept
cores	O
.	O
</s>
<s>
The	O
P10xx	O
series	O
,	O
P2010	O
and	O
P2020	O
are	O
based	O
on	O
the	O
e500v2	O
core	O
,	O
P204x	O
,	O
P30xx	O
and	O
P40xx	O
on	O
the	O
e500mc	B-General_Concept
core	O
,	O
and	O
P50xx	O
on	O
the	O
e5500	B-General_Concept
core	O
.	O
</s>
<s>
Features	O
include	O
32/32	O
kB	O
data/instruction	O
L1	O
cache	O
,	O
36-bit	O
physical	O
memory	O
addressing	O
[	O
appended	O
to	O
the	O
top	O
of	O
the	O
virtual	O
address	O
in	O
the	O
process	O
context	O
,	O
each	O
process	O
is	O
still	O
32bit ]	O
,	O
a	O
double	O
precision	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
is	O
present	O
on	O
some	O
cores	O
(	O
not	O
all	O
)	O
and	O
support	O
for	O
virtualization	B-Architecture
through	O
a	O
hypervisor	B-Operating_System
layer	O
is	O
present	O
in	O
products	O
featuring	O
the	O
e500mc	B-General_Concept
or	O
the	O
e5500	B-General_Concept
.	O
</s>
<s>
The	O
dual	O
and	O
multi-core	O
devices	O
supports	O
both	O
symmetric	B-Operating_System
and	O
asymmetric	B-Operating_System
multiprocessing	I-Operating_System
,	O
and	O
can	O
run	O
multiple	O
operating	O
systems	O
in	O
parallel	O
.	O
</s>
<s>
The	O
P1	O
series	O
is	O
tailored	O
for	O
gateways	O
,	O
Ethernet	B-Protocol
switches	I-Protocol
,	O
wireless	O
LAN	O
access	O
points	O
,	O
and	O
general-purpose	O
control	O
applications	O
.	O
</s>
<s>
It	O
is	O
designed	O
to	O
replace	O
the	O
PowerQUICC	B-General_Concept
II	O
Pro	O
and	O
PowerQUICC	B-General_Concept
III	O
platforms	O
.	O
</s>
<s>
The	O
chips	O
include	O
among	O
other	O
integrated	O
functionality	O
,	O
Gigabit	O
Ethernet	O
controllers	O
,	O
two	O
USB	O
2.0	O
controllers	O
,	O
a	O
security	O
engine	O
,	O
a	O
32-bit	O
DDR2	O
and	O
DDR3	O
memory	O
controller	O
with	O
ECC	B-Error_Name
support	O
,	O
dual	O
four-channel	O
DMA	B-General_Concept
controllers	I-General_Concept
,	O
a	O
SD/MMC	O
host	O
controller	O
and	O
high	O
speed	O
interfaces	O
which	O
can	O
be	O
configured	O
as	O
SerDes	O
lanes	O
,	O
PCIe	O
and	O
SGMII	B-Protocol
interfaces	O
.	O
</s>
<s>
P1011	O
–	O
Includes	O
one	O
800MHz	O
e500	O
core	O
,	O
256	O
kB	O
L2	O
cache	O
,	O
four	O
SerDes	O
lanes	O
,	O
three	O
Gbit	O
Ethernet	O
controllers	O
and	O
a	O
TDM	B-Protocol
engine	I-Protocol
for	O
legacy	O
phone	O
applications	O
.	O
</s>
<s>
P1020	O
–	O
includes	O
two	O
800MHz	O
e500	O
cores	O
,	O
256	O
kB	O
shared	O
L2	O
cache	O
,	O
four	O
SerDes	O
lanes	O
,	O
three	O
Gbit	O
Ethernet	O
controllers	O
and	O
a	O
TDM	B-Protocol
engine	I-Protocol
.	O
</s>
<s>
It	O
is	O
designed	O
to	O
replace	O
the	O
PowerQUICC	B-General_Concept
II	O
Pro	O
and	O
PowerQUICC	B-General_Concept
III	O
platforms	O
.	O
</s>
<s>
The	O
chips	O
include	O
,	O
among	O
other	O
integrated	O
functionality	O
,	O
a	O
512	O
kB	O
L2	O
cache	O
,	O
a	O
security	O
engine	O
,	O
three	O
Gigabit	O
Ethernet	O
controllers	O
,	O
a	O
USB	O
2.0	O
controller	O
,	O
a	O
64-bit	B-Device
DDR2	O
and	O
DDR3	O
memory	O
controller	O
with	O
ECC	B-Error_Name
support	O
,	O
dual	O
four-channel	O
DMA	B-General_Concept
controllers	I-General_Concept
,	O
a	O
SD/MMC	O
host	O
controller	O
and	O
high	O
speed	O
SerDes	O
lanes	O
which	O
can	O
be	O
configured	O
as	O
three	O
PCIe	O
interfaces	O
,	O
two	O
RapidIO	B-General_Concept
interfaces	O
and	O
two	O
SGMII	B-Protocol
interfaces	O
.	O
</s>
<s>
The	O
P3	O
series	O
is	O
a	O
mid	O
performance	O
networking	O
platform	O
,	O
designed	O
for	O
switching	B-Protocol
and	O
routing	B-Protocol
.	O
</s>
<s>
The	O
P3	O
family	O
offers	O
a	O
multi-core	O
platform	O
,	O
with	O
support	O
for	O
up	O
to	O
four	O
e500mc	B-General_Concept
cores	O
at	O
frequencies	O
up	O
to	O
1.5GHz	O
on	O
the	O
same	O
chip	O
,	O
connected	O
by	O
the	O
CoreNet	O
coherency	O
fabric	O
.	O
</s>
<s>
The	O
chips	O
include	O
among	O
other	O
integrated	O
functionality	O
,	O
integrated	O
L3	O
caches	O
,	O
memory	O
controller	O
,	O
multiple	O
I/O	O
-devices	O
such	O
as	O
DUART	O
,	O
GPIO	B-Architecture
and	O
USB	O
2.0	O
,	O
security	O
and	O
encryption	O
engines	O
,	O
a	O
queue	O
manager	O
scheduling	O
on-chip	O
events	O
and	O
a	O
SerDes	O
based	O
on-chip	O
high	O
speed	O
network	O
configurable	O
as	O
multiple	O
Gigabit	O
Ethernet	O
,	O
10	O
Gigabit	O
Ethernet	O
,	O
RapidIO	B-General_Concept
or	O
PCIe	O
interfaces	O
.	O
</s>
<s>
The	O
P3	O
processors	O
have	O
1.3GHz	O
64-bit	B-Device
DDR3	O
memory	O
controllers	O
,	O
18	O
SerDes	O
lanes	O
for	O
networking	O
,	O
hardware	O
accelerators	O
for	O
packet	O
handling	O
and	O
scheduling	O
,	O
regular	B-Language
expressions	I-Language
,	O
RAID	O
,	O
security	O
,	O
cryptography	O
and	O
RapidIO	B-General_Concept
.	O
</s>
<s>
The	O
cores	O
are	O
supported	O
by	O
a	O
hardware	O
hypervisor	B-Operating_System
and	O
can	O
be	O
run	O
in	O
symmetric	B-Operating_System
or	O
asymmetric	B-Operating_System
mode	O
meaning	O
that	O
the	O
cores	O
can	O
run	O
and	O
boot	O
operating	O
systems	O
together	O
or	O
separately	O
,	O
resetting	O
and	O
partitioning	O
cores	O
and	O
datapaths	B-General_Concept
independently	O
without	O
disturbing	O
other	O
operating	O
systems	O
and	O
applications	O
.	O
</s>
<s>
P3041	O
–	O
Quad	O
1.5GHz	O
cores	O
,	O
128	O
kB	O
L2	O
cache	O
per	O
core	O
,	O
single	O
1.3GHz	O
64-bit	B-Device
DDR3	O
controller	O
.	O
</s>
<s>
Manufactured	O
on	O
a	O
45nm	B-Algorithm
process	O
operating	O
in	O
a	O
12	O
W	O
envelope	O
.	O
</s>
<s>
The	O
P4	O
series	O
is	O
a	O
high	O
performance	O
networking	O
platform	O
,	O
designed	O
for	O
backbone	O
networking	O
and	O
enterprise	O
level	O
switching	B-Protocol
and	O
routing	B-Protocol
.	O
</s>
<s>
The	O
P4	O
family	O
offers	O
an	O
extreme	O
multi-core	O
platform	O
,	O
with	O
support	O
for	O
up	O
to	O
eight	O
e500mc	B-General_Concept
cores	O
at	O
frequencies	O
up	O
to	O
1.5GHz	O
on	O
the	O
same	O
chip	O
,	O
connected	O
by	O
the	O
CoreNet	O
coherency	O
fabric	O
.	O
</s>
<s>
The	O
chips	O
include	O
among	O
other	O
integrated	O
functionality	O
,	O
integrated	O
L3	O
caches	O
,	O
memory	O
controllers	O
,	O
multiple	O
I/O	O
-devices	O
such	O
as	O
DUART	O
,	O
GPIO	B-Architecture
and	O
USB	O
2.0	O
,	O
security	O
and	O
encryption	O
engines	O
,	O
a	O
queue	O
manager	O
scheduling	O
on-chip	O
events	O
and	O
a	O
SerDes	O
based	O
on-chip	O
high	O
speed	O
network	O
configurable	O
as	O
multiple	O
Gigabit	O
Ethernet	O
,	O
10	O
Gigabit	O
Ethernet	O
,	O
RapidIO	B-General_Concept
or	O
PCIe	O
interfaces	O
.	O
</s>
<s>
The	O
cores	O
are	O
supported	O
by	O
a	O
hardware	O
hypervisor	B-Operating_System
and	O
can	O
be	O
run	O
in	O
symmetric	B-Operating_System
or	O
asymmetric	B-Operating_System
mode	O
meaning	O
that	O
the	O
cores	O
can	O
run	O
and	O
boot	O
operating	O
systems	O
together	O
or	O
separately	O
,	O
resetting	O
and	O
partitioning	O
cores	O
and	O
datapaths	B-General_Concept
independently	O
without	O
disturbing	O
other	O
operating	O
systems	O
and	O
applications	O
.	O
</s>
<s>
P4080	O
–	O
Includes	O
eight	O
e500mc	B-General_Concept
cores	O
,	O
each	O
with	O
32/32kB	O
instruction/data	O
L1	O
caches	O
and	O
a	O
128kB	O
L2	O
cache	O
.	O
</s>
<s>
The	O
chip	O
has	O
dual	O
1MB	O
L3	O
caches	O
,	O
each	O
connected	O
to	O
a	O
64-bit	B-Device
DDR2/DDR3	O
memory	O
controller	O
.	O
</s>
<s>
The	O
chip	O
contains	O
a	O
security	O
and	O
encryption	O
module	O
,	O
capable	O
of	O
packet	O
parsing	O
and	O
classification	O
,	O
and	O
acceleration	O
of	O
encryption	O
and	O
regexp	B-Language
pattern	O
matching	O
.	O
</s>
<s>
The	O
chip	O
can	O
be	O
configured	O
with	O
up	O
to	O
eight	O
Gigabit	O
and	O
two	O
10	O
Gigabit	O
Ethernet	O
controllers	O
,	O
three	O
5GHz	O
PCIe	O
ports	O
and	O
two	O
RapidIO	B-General_Concept
interfaces	O
.	O
</s>
<s>
The	O
processor	O
is	O
manufactured	O
on	O
a	O
45nm	B-Algorithm
SOI	O
process	O
and	O
begun	O
sampling	O
to	O
customers	O
in	O
August	O
2009	O
.	O
</s>
<s>
To	O
help	O
software	O
developers	O
and	O
system	O
designers	O
get	O
started	O
with	O
the	O
QorIQ	B-General_Concept
P4080	O
,	O
Freescale	O
worked	O
with	O
Virtutech	O
to	O
create	O
a	O
virtual	B-Architecture
platform	I-Architecture
for	O
the	O
P4080	O
that	O
can	O
be	O
used	O
prior	O
to	O
silicon	O
availability	O
to	O
develop	O
,	O
test	O
,	O
and	O
debug	O
software	O
for	O
the	O
chip	O
.	O
</s>
<s>
The	O
P5	O
series	O
is	O
based	O
on	O
the	O
high	O
performance	O
64-bit	B-Device
e5500	B-General_Concept
core	O
scaling	O
up	O
to	O
2.5GHz	O
and	O
allowing	O
numerous	O
auxiliary	O
application	O
processing	O
units	O
as	O
well	O
as	O
multi	O
core	O
operation	O
via	O
the	O
CoreNet	O
fabric	O
.	O
</s>
<s>
The	O
P5	O
processors	O
have	O
1.3GHz	O
64-bit	B-Device
DDR3	O
memory	O
controllers	O
,	O
18	O
SerDes	O
lanes	O
for	O
networking	O
,	O
hardware	O
accelerators	O
for	O
packet	O
handling	O
and	O
scheduling	O
,	O
regular	B-Language
expressions	I-Language
,	O
RAID	O
,	O
security	O
,	O
cryptography	O
and	O
RapidIO	B-General_Concept
.	O
</s>
<s>
P5010	O
–	O
Single	O
e5500	B-General_Concept
2.2GHz	O
core	O
,	O
1	O
MB	O
L3	O
cache	O
,	O
single	O
1.333	O
lGHz	O
DDR3	O
controller	O
,	O
manufactured	O
on	O
a	O
45nm	B-Algorithm
process	O
and	O
operating	O
in	O
a	O
30W	O
envelope	O
.	O
</s>
<s>
P5020	O
–	O
Dual	O
e5500	B-General_Concept
2.2GHz	O
cores	O
,	O
dual	O
1	O
MB	O
L3	O
caches	O
,	O
dual	O
1.333	O
lGHz	O
DDR3	O
controllers	O
,	O
manufactured	O
on	O
a	O
45nm	B-Algorithm
process	O
and	O
operating	O
in	O
a	O
30W	O
envelope	O
.	O
</s>
<s>
P5021	O
–	O
Dual	O
e5500	B-General_Concept
2.4GHz	O
cores	O
,	O
1.6GHz	O
DDR3/3L	O
.	O
</s>
<s>
P5040	O
–	O
Quad	O
e5500	B-General_Concept
2.4GHz	O
cores	O
,	O
1.6GHz	O
DDR3/3L	O
.	O
</s>
<s>
In	O
February	O
2011	O
Freescale	O
introduced	O
the	O
QorIQ	B-General_Concept
Qonverge	O
platform	O
which	O
is	O
a	O
series	O
of	O
combined	O
CPU	O
and	O
DSP	B-Architecture
SoC	O
processors	O
targeting	O
wireless	B-General_Concept
infrastructure	I-General_Concept
applications	O
.	O
</s>
<s>
The	O
PSC913x	O
family	O
chips	O
uses	O
an	O
e500	O
core	O
based	O
CPU	O
and	O
StarCore	O
SC3850	O
DSPs	O
will	O
be	O
available	O
in	O
2011	O
,	O
and	O
is	O
manufactured	O
on	O
a	O
45nm	B-Algorithm
process	O
,	O
with	O
e6500	O
and	O
CS3900	O
core	O
based	O
28nm	O
parts	O
available	O
in	O
2012	O
called	O
P4xxx	O
.	O
</s>
<s>
The	O
QorIQ	B-General_Concept
Advanced	O
Multiprocessing	B-Operating_System
,	O
AMP	O
Series	O
,	O
processors	O
are	O
all	O
based	O
on	O
the	O
multithreaded	O
64-bit	B-Device
e6500	B-General_Concept
core	I-General_Concept
with	O
integrated	O
AltiVec	B-General_Concept
SIMD	B-Device
processing	O
units	O
except	O
the	O
lowest	O
end	O
T1	O
family	O
that	O
uses	O
the	O
older	O
e5500	B-General_Concept
core	O
.	O
</s>
<s>
The	O
T4	O
family	O
uses	O
the	O
e6500	O
64-bit	B-Device
dual	O
threaded	O
core	O
.	O
</s>
<s>
The	O
T2	O
family	O
uses	O
the	O
e6500	O
64-bit	B-Device
dual	O
threaded	O
core	O
.	O
</s>
<s>
The	O
T1	O
family	O
uses	O
the	O
e5500	B-General_Concept
64-bit	B-Device
single	O
threaded	O
core	O
at	O
1.2	O
to	O
1.5GHz	O
with	O
256	O
kB	O
L2	O
cache	O
per	O
core	O
and	O
256kB	O
shared	O
CoreNet	O
L3	O
cache	O
.	O
</s>
<s>
T1042	O
–	O
Quad-core	O
,	O
five	O
Gbit	O
Ethernet	O
ports	O
,	O
no	O
Ethernet	B-Protocol
switch	I-Protocol
.	O
</s>
<s>
T1022	O
–	O
Dual-core	O
,	O
five	O
Gbit	O
Ethernet	O
ports	O
,	O
no	O
Ethernet	B-Protocol
switch	I-Protocol
.	O
</s>
<s>
The	O
QorIQ	B-General_Concept
products	O
bring	O
some	O
new	O
challenges	O
in	O
order	O
to	O
design	O
some	O
control	O
planes	O
of	O
telecommunication	O
systems	O
and	O
their	O
data	B-Protocol
plane	I-Protocol
.	O
</s>
<s>
Some	O
cores	O
are	O
used	O
for	O
the	O
control	O
plane	O
while	O
some	O
others	O
are	O
used	O
for	O
a	O
re-designed	O
data	B-Protocol
plane	I-Protocol
based	O
on	O
a	O
Fast	O
Path	O
.	O
</s>
<s>
Freescale	O
has	O
partnered	O
with	O
networking	O
company	O
6WIND	O
to	O
provide	O
software	O
developers	O
with	O
a	O
high-performance	O
commercial	O
packet	O
processing	O
solution	O
for	O
the	O
QorIQ	B-General_Concept
platform	O
.	O
</s>
