<s>
QPACE	B-General_Concept
2	O
(	O
QCD	O
Parallel	O
Computing	O
Engine	O
)	O
is	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
and	O
scalable	O
supercomputer	B-Architecture
.	O
</s>
<s>
QPACE	B-General_Concept
2	O
is	O
a	O
follow-up	O
to	O
the	O
QPACE	B-General_Concept
supercomputer	B-Architecture
and	O
the	O
iDataCool	B-Device
hot-water	O
cooling	O
project	O
.	O
</s>
<s>
QPACE	B-General_Concept
2	O
uses	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
processors	O
(	O
a.k.a.	O
</s>
<s>
KNC	O
)	O
,	O
interconnected	O
by	O
a	O
combination	O
of	O
PCI	O
Express	O
(	O
abbreviated	O
PCIe	O
)	O
and	O
FDR	O
InfiniBand	B-Architecture
.	O
</s>
<s>
In	O
November	O
2015	O
,	O
QPACE	B-General_Concept
2	O
was	O
ranked	O
#500	O
on	O
the	O
Top500	B-Operating_System
list	O
of	O
the	O
most	O
powerful	O
supercomputers	B-Architecture
and	O
#15	O
on	O
the	O
Green	B-Application
500	I-Application
list	O
of	O
the	O
most	O
energy-efficient	O
supercomputers	B-Architecture
of	O
the	O
world	O
.	O
</s>
<s>
QPACE	B-General_Concept
2	O
was	O
funded	O
by	O
the	O
German	O
Research	O
Foundation	O
(	O
DFG	O
)	O
in	O
the	O
framework	O
of	O
SFB/TRR	O
-55	O
and	O
by	O
Eurotech	O
.	O
</s>
<s>
Many	O
current	O
supercomputers	B-Architecture
are	O
hybrid	O
architectures	O
that	O
use	O
accelerator	O
cards	O
with	O
a	O
PCIe	O
interface	O
to	O
boost	O
the	O
compute	O
performance	O
.	O
</s>
<s>
In	O
general	O
,	O
server	O
processors	O
support	O
only	O
a	O
limited	O
number	O
of	O
accelerators	O
due	O
to	O
the	O
limited	O
number	O
of	O
PCIe	O
lanes	O
(	O
typically	O
40	O
for	O
the	O
Intel	B-Device
Haswell	I-Device
architecture	I-Device
)	O
.	O
</s>
<s>
The	O
common	O
approach	O
to	O
integrate	O
multiple	O
accelerators	O
cards	O
into	O
the	O
host	O
system	O
is	O
to	O
arrange	O
multiple	O
server	O
processors	O
,	O
typically	O
two	O
or	O
four	O
,	O
as	O
distributed	B-Operating_System
shared	I-Operating_System
memory	I-Operating_System
systems	O
.	O
</s>
<s>
The	O
server	O
processors	O
,	O
their	O
interconnects	O
(	O
QPI	B-Architecture
for	O
Intel	O
processors	O
)	O
and	O
memory	O
chips	O
significantly	O
increase	O
the	O
foot-print	O
of	O
the	O
host	O
system	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
2	O
architecture	O
addresses	O
these	O
disadvantages	O
by	O
a	O
node	O
design	O
in	O
which	O
a	O
single	O
low-power	O
Intel	B-Device
Haswell	I-Device
E3	I-Device
host	O
CPU	B-Device
accommodates	O
four	O
Xeon	B-General_Concept
Phi	I-General_Concept
7120X	O
accelerator	O
cards	O
for	O
computational	O
power	O
and	O
one	O
dual-port	O
FDR	O
InfiniBand	B-Architecture
network	O
interface	O
card	O
for	O
external	O
communication	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
2	O
rack	O
contains	O
64	O
compute	O
nodes	O
(	O
and	O
thus	O
256	O
Xeon	B-General_Concept
Phi	I-General_Concept
accelerators	O
in	O
total	O
)	O
.	O
</s>
<s>
QPACE	B-General_Concept
2	O
relies	O
on	O
a	O
warm-water	O
cooling	O
solution	O
to	O
achieve	O
this	O
packaging	O
and	O
power	O
density	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
2	O
node	O
consists	O
of	O
commodity	O
hardware	O
interconnected	O
by	O
PCIe	O
.	O
</s>
<s>
One	O
slot	O
is	O
used	O
for	O
the	O
CPU	B-Device
card	O
,	O
which	O
is	O
a	O
PCIe	O
form	O
factor	O
card	O
containing	O
one	O
Intel	B-Device
Haswell	I-Device
E3-1230L	I-Device
v3	I-Device
server	O
processor	O
with	O
16	O
GB	O
DDR3	O
memory	O
as	O
well	O
as	O
a	O
microcontroller	B-Architecture
to	O
monitor	O
and	O
control	O
the	O
node	O
.	O
</s>
<s>
Four	O
slots	O
are	O
used	O
for	O
Xeon	B-General_Concept
Phi	I-General_Concept
7120X	O
cards	O
with	O
16	O
GB	O
GDDR5	O
each	O
,	O
and	O
one	O
slot	O
for	O
a	O
dual-port	O
FDR	O
InfiniBand	B-Architecture
network	O
interface	O
card	O
(	O
Connect-IB	O
by	O
Mellanox	O
)	O
.	O
</s>
<s>
The	O
midplane	O
and	O
the	O
CPU	B-Device
card	O
were	O
designed	O
for	O
the	O
QPACE	B-General_Concept
2	O
project	O
but	O
can	O
be	O
reused	O
for	O
other	O
projects	O
or	O
products	O
.	O
</s>
<s>
The	O
low-power	O
Intel	O
E3-1230L	O
v3	O
server	O
CPU	B-Device
is	O
energy-efficient	O
,	O
but	O
weak	O
in	O
computational	O
power	O
compared	O
to	O
other	O
server	O
processors	O
available	O
around	O
2015	O
(	O
and	O
in	O
particular	O
weaker	O
than	O
most	O
accelerator	O
cards	O
)	O
.	O
</s>
<s>
The	O
CPU	B-Device
does	O
not	O
contribute	O
significantly	O
to	O
the	O
compute	O
power	O
of	O
the	O
node	O
.	O
</s>
<s>
Technically	O
,	O
the	O
CPU	B-Device
serves	O
as	O
a	O
root	B-Architecture
complex	I-Architecture
for	O
the	O
PCIe	O
fabric	O
.	O
</s>
<s>
The	O
PCIe	O
switch	O
extends	O
the	O
host	O
CPU	B-Device
's	O
limited	O
number	O
of	O
PCIe	O
lanes	O
to	O
a	O
total	O
of	O
80	O
lanes	O
,	O
therefore	O
enabling	O
a	O
multitude	O
of	O
components	O
(	O
4x	O
Xeon	B-General_Concept
Phi	I-General_Concept
and	O
1x	O
InfiniBand	B-Architecture
,	O
each	O
x16	O
PCIe	O
)	O
to	O
be	O
connected	O
to	O
the	O
CPU	B-Device
as	O
PCIe	O
endpoints	O
.	O
</s>
<s>
This	O
architecture	O
also	O
allows	O
the	O
Xeon	B-General_Concept
Phis	I-General_Concept
to	O
do	O
peer-to-peer	O
communication	O
via	O
PCIe	O
and	O
to	O
directly	O
access	O
the	O
external	O
network	O
without	O
having	O
to	O
go	O
through	O
the	O
host	O
CPU	B-Device
.	O
</s>
<s>
Each	O
QPACE	B-General_Concept
2	O
node	O
comprises	O
248	O
physical	O
cores	O
(	O
host	O
CPU	B-Device
:	O
4	O
,	O
Xeon	B-General_Concept
Phi	I-General_Concept
:	O
61	O
each	O
)	O
.	O
</s>
<s>
Host	O
processor	O
and	O
accelerators	O
support	O
multithreading	B-General_Concept
.	O
</s>
<s>
The	O
design	O
of	O
the	O
node	O
is	O
not	O
limited	O
to	O
the	O
components	O
used	O
in	O
QPACE	B-General_Concept
2	O
.	O
</s>
<s>
In	O
principle	O
,	O
any	O
cards	O
supporting	O
PCIe	O
,	O
e.g.	O
,	O
accelerators	O
such	O
as	O
GPUs	B-Architecture
and	O
other	O
network	O
technologies	O
than	O
InfiniBand	B-Architecture
,	O
can	O
be	O
used	O
as	O
long	O
as	O
form	O
factor	O
and	O
power	O
specifications	O
are	O
met	O
.	O
</s>
<s>
The	O
intra-node	O
communication	O
proceeds	O
via	O
the	O
PCIe	O
switch	O
without	O
host	O
CPU	B-Device
involvement	O
.	O
</s>
<s>
The	O
inter-node	O
communication	O
is	O
based	O
on	O
FDR	O
InfiniBand	B-Architecture
.	O
</s>
<s>
The	O
topology	O
of	O
the	O
InfiniBand	B-Architecture
network	O
is	O
a	O
two-dimensional	O
hyper-crossbar	O
.	O
</s>
<s>
This	O
means	O
that	O
a	O
two-dimensional	O
mesh	O
of	O
InfiniBand	B-Architecture
switches	O
is	O
built	O
,	O
and	O
the	O
two	O
InfiniBand	B-Architecture
ports	O
of	O
a	O
node	O
are	O
connected	O
to	O
one	O
switch	O
in	O
each	O
of	O
the	O
dimensions	O
.	O
</s>
<s>
The	O
InfiniBand	B-Architecture
network	O
is	O
also	O
used	O
for	O
I/O	O
to	O
a	O
Lustre	B-Application
file	I-Application
system	I-Application
.	O
</s>
<s>
The	O
CPU	B-Device
card	O
provides	O
two	O
Gigabit	O
Ethernet	O
interfaces	O
that	O
are	O
used	O
to	O
control	O
the	O
nodes	O
and	O
to	O
boot	O
the	O
operating	O
system	O
.	O
</s>
<s>
The	O
nodes	O
of	O
the	O
QPACE	B-General_Concept
2	O
supercomputer	B-Architecture
are	O
cooled	O
by	O
water	O
using	O
an	O
innovative	O
concept	O
based	O
on	O
roll-bond	O
technology	O
.	O
</s>
<s>
The	O
diskless	O
nodes	O
are	O
operated	O
using	O
a	O
standard	O
Linux	B-Application
distribution	O
(	O
CentOS	O
7	O
)	O
,	O
which	O
is	O
booted	O
over	O
the	O
Ethernet	O
network	O
.	O
</s>
<s>
The	O
Xeon	B-General_Concept
Phis	I-General_Concept
are	O
running	O
the	O
freely	O
available	O
Intel	O
Manycore	O
Platform	O
Software	O
Stack	O
(	O
MPSS	O
)	O
.	O
</s>
<s>
The	O
InfiniBand	B-Architecture
communication	O
is	O
based	O
on	O
the	O
OFED	O
stack	O
,	O
which	O
is	O
freely	O
available	O
as	O
well	O
.	O
</s>
