<s>
QPACE	B-General_Concept
(	O
QCD	O
Parallel	O
Computing	O
on	O
the	O
Cell	B-General_Concept
Broadband	I-General_Concept
Engine	I-General_Concept
)	O
is	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
and	O
scalable	O
supercomputer	B-Architecture
designed	O
for	O
applications	O
in	O
lattice	O
quantum	O
chromodynamics	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
supercomputer	B-Architecture
is	O
a	O
research	O
project	O
carried	O
out	O
by	O
several	O
academic	O
institutions	O
in	O
collaboration	O
with	O
the	O
IBM	O
Research	O
and	O
Development	O
Laboratory	O
in	O
Böblingen	O
,	O
Germany	O
,	O
and	O
other	O
industrial	O
partners	O
including	O
Eurotech	O
,	O
Knürr	O
,	O
and	O
Xilinx	O
.	O
</s>
<s>
Since	O
then	O
QPACE	B-General_Concept
is	O
used	O
for	O
calculations	O
of	O
lattice	O
QCD	O
.	O
</s>
<s>
The	O
system	O
architecture	O
is	O
also	O
suitable	O
for	O
other	O
applications	O
that	O
mainly	O
rely	O
on	O
nearest-neighbor	O
communication	O
,	O
e.g.	O
,	O
lattice	B-Algorithm
Boltzmann	I-Algorithm
methods	I-Algorithm
.	O
</s>
<s>
In	O
November	O
2009	O
QPACE	B-General_Concept
was	O
the	O
leading	O
architecture	O
on	O
the	O
Green500	O
list	O
of	O
the	O
most	O
energy-efficient	O
supercomputers	B-Architecture
in	O
the	O
world	O
.	O
</s>
<s>
The	O
title	O
was	O
defended	O
in	O
June	O
2010	O
,	O
when	O
the	O
architecture	O
achieved	O
an	O
energy	O
signature	O
of	O
773	O
MFLOPS	O
per	O
Watt	O
in	O
the	O
Linpack	B-Device
benchmark	I-Device
.	O
</s>
<s>
In	O
the	O
Top500	B-Operating_System
list	O
of	O
most	O
powerful	O
supercomputers	B-Architecture
,	O
QPACE	B-General_Concept
ranked	O
#110	O
-	O
#112	O
in	O
November	O
2009	O
,	O
and	O
#131	O
-	O
#133	O
in	O
June	O
2010	O
.	O
</s>
<s>
QPACE	B-General_Concept
was	O
funded	O
by	O
the	O
German	O
Research	O
Foundation	O
(	O
DFG	O
)	O
in	O
the	O
framework	O
of	O
SFB/TRR	O
-55	O
and	O
by	O
IBM	O
.	O
</s>
<s>
In	O
2008	O
IBM	O
released	O
the	O
PowerXCell	O
8i	O
multi-core	B-Architecture
processor	I-Architecture
,	O
an	O
enhanced	O
version	O
of	O
the	O
IBM	O
Cell	B-General_Concept
Broadband	I-General_Concept
Engine	I-General_Concept
used	O
,	O
e.g.	O
,	O
in	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
.	O
</s>
<s>
It	O
is	O
one	O
of	O
the	O
building	O
blocks	O
of	O
the	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
cluster	O
,	O
which	O
was	O
the	O
first	O
supercomputer	B-Architecture
architecture	O
to	O
break	O
the	O
PFLOPS	O
barrier	O
.	O
</s>
<s>
Cluster	O
architectures	O
based	O
on	O
the	O
PowerXCell	O
8i	O
typically	O
rely	O
on	O
IBM	B-General_Concept
BladeCenter	I-General_Concept
blade	B-Architecture
servers	I-Architecture
interconnected	O
by	O
industry-standard	O
networks	O
such	O
as	O
Infiniband	B-Architecture
.	O
</s>
<s>
For	O
QPACE	B-General_Concept
an	O
entirely	O
different	O
approach	O
was	O
chosen	O
.	O
</s>
<s>
A	O
custom-designed	O
network	O
co-processor	O
implemented	O
on	O
Xilinx	O
Virtex-5	O
FPGAs	B-Architecture
is	O
used	O
to	O
connect	O
the	O
compute	O
nodes	O
.	O
</s>
<s>
FPGAs	B-Architecture
are	O
re-programmable	O
semiconductor	O
devices	O
that	O
allow	O
for	O
a	O
customized	O
specification	O
of	O
the	O
functional	O
behavior	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
network	O
processor	O
is	O
tightly	O
coupled	O
to	O
the	O
PowerXCell	O
8i	O
via	O
a	O
Rambus-proprietary	O
I/O	B-General_Concept
interface	I-General_Concept
.	O
</s>
<s>
The	O
smallest	O
building	O
block	O
of	O
QPACE	B-General_Concept
is	O
the	O
node	O
card	O
,	O
which	O
hosts	O
the	O
PowerXCell	O
8i	O
and	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
Node	O
cards	O
are	O
mounted	O
on	O
backplanes	B-Architecture
,	O
each	O
of	O
which	O
can	O
host	O
up	O
to	O
32	O
node	O
cards	O
.	O
</s>
<s>
One	O
QPACE	B-General_Concept
rack	O
houses	O
up	O
to	O
eight	O
backplanes	B-Architecture
,	O
with	O
four	O
backplanes	B-Architecture
each	O
mounted	O
to	O
the	O
front	O
and	O
back	O
side	O
.	O
</s>
<s>
QPACE	B-General_Concept
relies	O
on	O
a	O
water-cooling	O
solution	O
to	O
achieve	O
this	O
packaging	O
density	O
.	O
</s>
<s>
The	O
heart	O
of	O
QPACE	B-General_Concept
is	O
the	O
IBM	O
PowerXCell	O
8i	O
multi-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Each	O
node	O
card	O
hosts	O
one	O
PowerXCell	O
8i	O
,	O
4	O
GB	O
of	O
DDR2	O
SDRAM	O
with	O
ECC	B-General_Concept
,	O
one	O
Xilinx	O
Virtex-5	O
FPGA	B-Architecture
and	O
seven	O
network	O
transceivers	O
.	O
</s>
<s>
A	O
single	O
1	O
Gigabit	O
Ethernet	O
transceiver	O
connects	O
the	O
node	O
card	O
to	O
the	O
I/O	B-General_Concept
network	O
.	O
</s>
<s>
Six	O
10	O
Gigabit	O
transceivers	O
are	O
used	O
for	O
passing	O
messages	O
between	O
neighboring	O
nodes	O
in	O
a	O
three-dimensional	B-Operating_System
toroidal	I-Operating_System
mesh	I-Operating_System
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
network	O
co-processor	O
is	O
implemented	O
on	O
a	O
Xilinx	O
Virtex-5	O
FPGA	B-Architecture
,	O
which	O
is	O
directly	O
connected	O
to	O
the	O
I/O	B-General_Concept
interface	I-General_Concept
of	O
the	O
PowerXCell	O
8i	O
.	O
</s>
<s>
The	O
functional	O
behavior	O
of	O
the	O
FPGA	B-Architecture
is	O
defined	O
by	O
a	O
hardware	O
description	O
language	O
and	O
can	O
be	O
changed	O
at	O
any	O
time	O
at	O
the	O
cost	O
of	O
rebooting	O
the	O
node	O
card	O
.	O
</s>
<s>
Most	O
entities	O
of	O
the	O
QPACE	B-General_Concept
network	O
co-coprocessor	O
are	O
coded	O
in	O
VHDL	B-Language
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
network	O
co-processor	O
connects	O
the	O
PowerXCell	O
8i	O
to	O
three	O
communications	O
networks	O
:	O
</s>
<s>
The	O
torus	O
network	O
is	O
a	O
high-speed	O
communication	O
path	O
that	O
allows	O
for	O
nearest-neighbor	O
communication	O
in	O
a	O
three-dimensional	B-Operating_System
toroidal	I-Operating_System
mesh	I-Operating_System
.	O
</s>
<s>
The	O
torus	O
network	O
relies	O
on	O
the	O
physical	B-Application
layer	I-Application
of	O
10	O
Gigabit	O
Ethernet	O
,	O
while	O
a	O
custom-designed	O
communications	O
protocol	O
optimized	O
for	O
small	O
message	O
sizes	O
is	O
used	O
for	O
message	O
passing	O
.	O
</s>
<s>
A	O
unique	O
feature	O
of	O
the	O
torus	O
network	O
design	O
is	O
the	O
support	O
for	O
zero-copy	O
communication	O
between	O
the	O
private	O
memory	O
areas	O
,	O
called	O
the	O
Local	O
Stores	O
,	O
of	O
the	O
Synergistic	O
Processing	O
Elements	O
(	O
SPEs	O
)	O
by	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
.	O
</s>
<s>
Switched	O
1	O
Gigabit	O
Ethernet	O
is	O
used	O
for	O
file	O
I/O	B-General_Concept
and	O
maintenance	O
.	O
</s>
<s>
The	O
compute	O
nodes	O
of	O
the	O
QPACE	B-General_Concept
supercomputer	B-Architecture
are	O
cooled	O
by	O
water	O
.	O
</s>
<s>
The	O
QPACE	B-General_Concept
cooling	O
solution	O
also	O
influenced	O
other	O
supercomputer	B-Architecture
designs	O
such	O
as	O
SuperMUC	B-Device
.	O
</s>
<s>
Two	O
identical	O
installations	O
of	O
QPACE	B-General_Concept
with	O
four	O
racks	O
have	O
been	O
operating	O
since	O
2009	O
:	O
</s>
