<s>
The	O
Q-bus	B-Architecture
,	O
also	O
known	O
as	O
the	O
LSI-11	B-Architecture
Bus	I-Architecture
,	O
is	O
one	O
of	O
several	O
bus	B-General_Concept
technologies	O
used	O
with	O
PDP	B-Device
and	O
MicroVAX	B-Device
computer	O
systems	O
previously	O
manufactured	O
by	O
the	O
Digital	O
Equipment	O
Corporation	O
of	O
Maynard	O
,	O
Massachusetts	O
.	O
</s>
<s>
The	O
Q-bus	B-Architecture
is	O
a	O
less	O
expensive	O
version	O
of	O
Unibus	B-Device
using	O
multiplexing	O
so	O
that	O
address	O
and	O
data	O
signals	O
share	O
the	O
same	O
wires	O
.	O
</s>
<s>
Over	O
time	O
,	O
the	O
physical	O
address	O
range	O
of	O
the	O
Q-bus	B-Architecture
was	O
expanded	O
from	O
16	O
to	O
18	O
and	O
then	O
22	O
bits	O
.	O
</s>
<s>
Block	O
transfer	O
modes	O
were	O
also	O
added	O
to	O
the	O
Q-bus	B-Architecture
.	O
</s>
<s>
Like	O
the	O
Unibus	B-Device
before	O
it	O
,	O
the	O
Q-bus	B-Architecture
uses	O
:	O
</s>
<s>
Memory-mapped	B-Architecture
I/O	I-Architecture
means	O
that	O
data	O
cycles	O
between	O
any	O
two	O
devices	O
,	O
whether	O
CPU	O
,	O
memory	O
,	O
or	O
I/O	O
devices	O
,	O
use	O
the	O
same	O
protocols	O
.	O
</s>
<s>
On	O
the	O
Unibus	B-Device
,	O
a	O
range	O
of	O
physical	O
addresses	O
are	O
dedicated	O
for	O
I/O	O
devices	O
.	O
</s>
<s>
The	O
Q-bus	B-Architecture
simplifies	O
this	O
design	O
by	O
providing	O
a	O
specific	O
signal	O
(	O
originally	O
called	O
BBS7	O
,	O
Bus	B-General_Concept
Bank	O
Select	O
7	O
but	O
later	O
generalized	O
to	O
be	O
called	O
BBSIO	O
,	O
Bus	B-General_Concept
Bank	O
Select	O
I/O	O
)	O
that	O
selects	O
the	O
range	O
of	O
addresses	O
used	O
by	O
the	O
I/O	O
devices	O
.	O
</s>
<s>
Byte	B-General_Concept
addressing	I-General_Concept
means	O
that	O
the	O
physical	O
address	O
passed	O
on	O
the	O
Unibus	B-Device
is	O
interpreted	O
as	O
the	O
address	O
of	O
a	O
byte-sized	O
quantity	O
of	O
data	O
.	O
</s>
<s>
Because	O
the	O
bus	B-General_Concept
actually	O
contains	O
a	O
data	O
path	O
that	O
is	O
two	O
bytes	O
wide	O
,	O
address	O
bit	O
 [ 0 ] 	O
is	O
subject	O
to	O
special	O
interpretation	O
and	O
data	O
on	O
the	O
bus	B-General_Concept
has	O
to	O
travel	O
in	O
the	O
correct	O
byte	O
lanes	O
.	O
</s>
<s>
A	O
strict	O
Master-Slave	B-Operating_System
relationship	O
means	O
that	O
at	O
any	O
point	O
in	O
time	O
,	O
only	O
one	O
device	O
can	O
be	O
the	O
Master	O
of	O
the	O
Q-bus	B-Architecture
.	O
</s>
<s>
(	O
This	O
had	O
no	O
effect	O
on	O
whether	O
a	O
given	O
bus	B-General_Concept
cycle	O
is	O
reading	O
or	O
writing	O
data	O
;	O
the	O
bus	B-Architecture
master	I-Architecture
can	O
command	O
either	O
type	O
of	O
transaction	O
.	O
)	O
</s>
<s>
At	O
the	O
end	O
of	O
the	O
bus	B-General_Concept
cycle	O
,	O
a	O
bus	B-Architecture
arbitration	I-Architecture
protocol	O
then	O
selects	O
the	O
next	O
device	O
to	O
be	O
given	O
mastery	O
of	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
Asynchronous	O
signaling	O
means	O
that	O
the	O
bus	B-General_Concept
has	O
no	O
fixed	O
cycle	O
time	O
;	O
the	O
duration	O
of	O
any	O
particular	O
data	O
transfer	O
cycle	O
on	O
the	O
bus	B-General_Concept
is	O
determined	O
solely	O
by	O
the	O
master	O
and	O
slave	O
devices	O
participating	O
in	O
the	O
current	O
data	O
cycle	O
.	O
</s>
<s>
These	O
devices	O
use	O
handshake	B-Protocol
signals	O
to	O
control	O
the	O
timing	O
of	O
the	O
data	O
cycle	O
.	O
</s>
<s>
Timeout	O
logic	O
within	O
the	O
master	O
device	O
limits	O
the	O
maximum	O
allowed	O
length	O
of	O
any	O
given	O
bus	B-General_Concept
cycle	O
.	O
</s>
<s>
Depending	O
on	O
its	O
generation	O
,	O
the	O
Q-bus	B-Architecture
contains	O
16	O
,	O
18	O
,	O
or	O
22	O
BDAL	O
(	O
Bus	B-General_Concept
Data/Address	O
Line	O
)	O
lines	O
.	O
</s>
<s>
16	O
,	O
18	O
,	O
or	O
22	O
BDAL	O
lines	O
are	O
used	O
for	O
the	O
physical	O
address	O
portion	O
of	O
each	O
bus	B-General_Concept
cycle	O
.	O
</s>
<s>
Eight	O
or	O
16	O
DBAL	O
lines	O
are	O
then	O
re-used	O
for	O
the	O
data	O
portion(s )	O
of	O
each	O
bus	B-General_Concept
cycle	O
.	O
</s>
<s>
Newer	O
generations	O
of	O
the	O
bus	B-General_Concept
allow	O
block	O
mode	O
transfer	O
where	O
a	O
single	O
bus	B-General_Concept
address	O
can	O
be	O
followed	O
by	O
more	O
than	O
one	O
data	O
cycle	O
(	O
with	O
the	O
transfers	O
taking	O
place	O
at	O
consecutive	O
bus	B-General_Concept
addresses	O
)	O
.	O
</s>
<s>
Because	O
the	O
address	O
portion	O
of	O
each	O
bus	B-General_Concept
cycle	O
can	O
not	O
transfer	O
data	O
,	O
the	O
use	O
of	O
block	O
mode	O
means	O
fewer	O
address	O
cycles	O
and	O
more	O
time	O
for	O
data	O
cycles	O
,	O
allowing	O
increased	O
bus	B-General_Concept
data	O
transfer	O
bandwidth	O
.	O
</s>
<s>
Bus	B-General_Concept
mastery	O
is	O
awarded	O
based	O
on	O
an	O
I/O	O
card	O
's	O
topological	O
proximity	O
to	O
the	O
bus	B-Architecture
arbitrator	I-Architecture
(	O
at	O
the	O
logical	O
front	O
of	O
the	O
bus	B-General_Concept
)	O
;	O
closer	O
cards	O
are	O
granted	O
priority	O
over	O
further	O
cards	O
.	O
</s>
<s>
Interrupts	O
can	O
be	O
delivered	O
to	O
the	O
Interrupt	O
Fielding	O
Processor	O
at	O
any	O
of	O
four	O
interrupt	B-Operating_System
priority	I-Operating_System
levels	I-Operating_System
.	O
</s>
<s>
Within	O
a	O
given	O
level	O
,	O
the	O
cards	O
closer	O
to	O
the	O
IFP	O
(	O
at	O
the	O
front	O
of	O
the	O
bus	B-General_Concept
)	O
take	O
priority	O
over	O
cards	O
further	O
back	O
on	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
Interrupts	B-Architecture
are	I-Architecture
vectored	I-Architecture
:	O
a	O
card	O
requesting	O
an	O
interrupt	O
has	O
its	O
interrupt	O
vector	O
read	O
by	O
the	O
IFP	O
.	O
</s>
<s>
As	O
with	O
the	O
Unibus	B-Device
,	O
the	O
signaling	O
was	O
carefully	O
optimized	O
so	O
that	O
the	O
minimum	O
amount	O
of	O
logic	O
is	O
required	O
across	O
the	O
entire	O
bus	B-General_Concept
system	O
.	O
</s>
<s>
Asynchronous	O
signaling	O
is	O
used	O
but	O
de-skewing	O
of	O
addresses	O
and	O
data	O
is	O
the	O
responsibility	O
of	O
the	O
current	O
bus	B-Architecture
master	I-Architecture
,	O
minimizing	O
the	O
complexity	O
of	O
the	O
bus	B-General_Concept
slave	O
devices	O
.	O
</s>
<s>
The	O
responsibility	O
for	O
timing-out	O
failed	O
bus	B-General_Concept
cycles	O
also	O
is	O
placed	O
in	O
the	O
master	O
devices	O
.	O
</s>
<s>
Similarly	O
,	O
the	O
complexities	O
of	O
handling	O
interrupt	O
transactions	O
are	O
concentrated	O
into	O
the	O
single	O
Interrupt-Fielding	O
Processor	O
(	O
the	O
PDP-11	O
or	O
VAX-11	O
computer	O
)	O
in	O
the	O
system	O
.	O
</s>
<s>
The	O
design	O
of	O
the	O
Q-bus	B-Architecture
was	O
very	O
closely	O
related	O
to	O
the	O
design	O
of	O
the	O
Unibus	B-Device
both	O
in	O
spirit	O
and	O
in	O
detailed	O
implementation	O
.	O
</s>
<s>
Adapters	O
were	O
available	O
from	O
Digital	O
and	O
from	O
third	O
parties	O
that	O
allow	O
Q-bus	B-Architecture
devices	O
to	O
be	O
connected	O
to	O
Unibus-based	O
computers	O
and	O
vice	O
versa	O
.	O
</s>
<s>
A	O
number	O
of	O
I/O	O
devices	O
were	O
available	O
in	O
either	O
Unibus	B-Device
or	O
Q-bus	B-Architecture
flavors	O
;	O
some	O
of	O
these	O
devices	O
have	O
minor	O
differences	O
while	O
many	O
others	O
were	O
essentially	O
identical	O
.	O
</s>
<s>
In	O
Soviet	O
systems	O
(	O
see	O
1801	B-General_Concept
series	I-General_Concept
CPU	I-General_Concept
)	O
,	O
the	O
Q-Bus	B-Architecture
architecture	O
is	O
called	O
МПИ	B-Architecture
( Магистральный	O
Параллельный	O
Интерфейс	O
,	O
or	O
parallel	O
bus	B-General_Concept
interface	O
)	O
.	O
</s>
<s>
Its	O
main	O
difference	O
is	O
that	O
it	O
supports	O
up	O
to	O
four	O
processors	O
on	O
the	O
same	O
bus	B-General_Concept
.	O
</s>
<s>
Otherwise	O
it	O
is	O
completely	O
binary	O
and	O
electrically	O
compatible	O
with	O
the	O
standard	O
Q-Bus	B-Architecture
,	O
except	O
for	O
the	O
physical	O
layout	O
of	O
connectors	O
.	O
</s>
<s>
A	O
wide	O
range	O
of	O
interface	O
cards	O
are	O
available	O
for	O
the	O
Q-Bus	B-Architecture
.	O
</s>
