<s>
Pumping	B-General_Concept
,	O
when	O
referring	O
to	O
computer	O
systems	O
,	O
is	O
an	O
informal	O
term	O
for	O
transmitting	O
a	O
data	O
signal	O
more	O
than	O
one	O
time	O
per	O
clock	O
signal	O
.	O
</s>
<s>
Early	O
types	O
of	O
system	O
memory	O
(	O
RAM	B-Architecture
)	O
,	O
such	O
as	O
SDRAM	O
,	O
transmitted	O
data	O
on	O
only	O
the	O
rising	O
edge	O
of	O
the	O
clock	O
signal	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
double	O
data	O
rate	O
synchronous	O
dynamic	O
RAM	B-Architecture
or	O
DDR	O
SDRAM	O
,	O
the	O
data	O
was	O
transmitted	O
on	O
both	O
rising	O
and	O
falling	O
edges	O
.	O
</s>
<s>
However	O
,	O
quad-pumping	O
has	O
been	O
used	O
for	O
a	O
while	O
for	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
of	O
a	O
computer	O
system	O
.	O
</s>
<s>
The	O
FSB	O
is	O
known	O
to	O
be	O
quad-pumped	B-Device
,	O
so	O
its	O
clock	O
frequency	O
is	O
1066/4	O
=	O
266MHz	O
.	O
</s>
<s>
The	O
DDR2	O
RAM	B-Architecture
that	O
it	O
is	O
compatible	O
with	O
is	O
known	O
to	O
be	O
double-pumped	O
and	O
to	O
have	O
an	O
Input/Output	O
Bus	O
twice	O
that	O
of	O
the	O
true	O
FSB	O
frequency	O
(	O
effectively	O
transferring	O
data	O
4	O
times	O
a	O
clock	O
cycle	O
)	O
,	O
so	O
to	O
run	O
the	O
system	O
synchronously	O
(	O
see	O
front-side	B-Architecture
bus	I-Architecture
)	O
the	O
type	O
of	O
RAM	B-Architecture
that	O
is	O
appropriate	O
is	O
quadruple	O
266MHz	O
,	O
or	O
DDR2-1066	O
(	O
PC2-8400	O
or	O
PC2-8500	O
,	O
depending	O
on	O
the	O
manufacturer	O
's	O
labeling	O
.	O
</s>
