<s>
Programmed	B-General_Concept
input	I-General_Concept
–	I-General_Concept
output	I-General_Concept
(	O
also	O
programmable	O
input/output	B-General_Concept
,	O
programmed	B-General_Concept
input/output	I-General_Concept
,	O
programmed	B-General_Concept
I/O	I-General_Concept
,	O
PIO	O
)	O
is	O
a	O
method	O
of	O
data	O
transmission	O
,	O
via	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
,	O
between	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
a	O
peripheral	O
device	O
,	O
such	O
as	O
a	O
Parallel	B-Protocol
ATA	I-Protocol
storage	O
device	O
.	O
</s>
<s>
In	O
contrast	O
,	O
in	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	B-General_Concept
)	O
operations	O
,	O
the	O
CPU	O
is	O
uninvolved	O
in	O
the	O
data	O
transfer	O
.	O
</s>
<s>
The	O
term	O
can	O
refer	O
to	O
either	O
memory-mapped	B-Architecture
I/O	I-Architecture
(	O
MMIO	B-Architecture
)	O
or	O
port-mapped	B-General_Concept
I/O	I-General_Concept
(	O
PMIO	B-Architecture
)	O
.	O
</s>
<s>
PMIO	B-Architecture
refers	O
to	O
transfers	O
using	O
a	O
special	O
address	B-General_Concept
space	I-General_Concept
outside	O
of	O
normal	O
memory	O
,	O
usually	O
accessed	O
with	O
dedicated	O
instructions	O
,	O
such	O
as	O
IN	O
and	O
OUT	O
in	O
x86	B-Operating_System
architectures	I-Operating_System
.	O
</s>
<s>
MMIO	B-Architecture
refers	O
to	O
transfers	O
to	O
I/O	B-General_Concept
devices	I-General_Concept
that	O
are	O
mapped	O
into	O
the	O
normal	O
address	B-General_Concept
space	I-General_Concept
available	O
to	O
the	O
program	O
.	O
</s>
<s>
PMIO	B-Architecture
was	O
very	O
useful	O
for	O
early	O
microprocessors	O
with	O
small	O
address	B-General_Concept
spaces	I-General_Concept
,	O
since	O
the	O
valuable	O
resource	O
was	O
not	O
consumed	O
by	O
the	O
I/O	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
The	O
best	O
known	O
example	O
of	O
a	O
PC	O
device	O
that	O
uses	O
programmed	B-General_Concept
I/O	I-General_Concept
is	O
the	O
Parallel	O
AT	B-Protocol
Attachment	I-Protocol
(	O
PATA	B-Protocol
)	O
interface	O
;	O
however	O
,	O
the	O
AT	B-Protocol
Attachment	I-Protocol
interface	I-Protocol
can	O
also	O
be	O
operated	O
in	O
any	O
of	O
several	O
DMA	B-General_Concept
modes	O
.	O
</s>
<s>
Many	O
older	O
devices	O
in	O
a	O
PC	O
also	O
use	O
PIO	O
,	O
including	O
legacy	O
serial	O
ports	O
,	O
legacy	O
parallel	O
ports	O
when	O
not	O
in	O
ECP	O
mode	O
,	O
keyboard	O
and	O
mouse	O
PS/2	B-Protocol
ports	I-Protocol
,	O
legacy	O
MIDI	O
and	O
joystick	B-Device
ports	O
,	O
the	O
interval	O
timer	O
,	O
and	O
older	O
network	O
interfaces	O
.	O
</s>
<s>
By	O
accessing	O
the	O
information	O
registers	O
(	O
using	O
Mode	O
0	O
)	O
on	O
an	O
ATA	B-Protocol
drive	I-Protocol
,	O
the	O
CPU	O
is	O
able	O
to	O
determine	O
the	O
maximum	O
transfer	O
rate	O
for	O
the	O
device	O
and	O
configure	O
the	O
ATA	O
controller	O
for	O
optimal	O
performance	O
.	O
</s>
<s>
The	O
PIO	B-General_Concept
modes	I-General_Concept
require	O
a	O
great	O
deal	O
of	O
CPU	O
overhead	O
to	O
configure	O
a	O
data	O
transaction	O
and	O
transfer	O
the	O
data	O
.	O
</s>
<s>
Because	O
of	O
this	O
inefficiency	O
,	O
the	O
DMA	B-General_Concept
(	O
and	O
eventually	O
Ultra	O
Direct	B-General_Concept
Memory	I-General_Concept
Access	I-General_Concept
(	O
UDMA	O
)	O
interface	O
was	O
created	O
to	O
increase	O
performance	O
.	O
</s>
<s>
The	O
simple	O
digital	O
logic	O
needed	O
to	O
implement	O
a	O
PIO	O
transfer	O
still	O
makes	O
this	O
transfer	O
method	O
useful	O
today	O
,	O
especially	O
if	O
high	O
transfer	O
rates	O
are	O
unneeded	O
as	O
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
or	O
with	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
chips	O
,	O
where	O
PIO	B-General_Concept
mode	I-General_Concept
can	O
be	O
used	O
with	O
no	O
significant	O
performance	O
loss	O
.	O
</s>
<s>
Two	O
additional	O
advanced	O
timing	O
modes	O
have	O
been	O
defined	O
in	O
the	O
CompactFlash	B-Device
specification	O
2.0	O
.	O
</s>
<s>
Those	O
are	O
PIO	B-General_Concept
modes	I-General_Concept
5	O
and	O
6	O
.	O
</s>
<s>
They	O
are	O
specific	O
to	O
CompactFlash	B-Device
.	O
</s>
<s>
A	O
PIO	B-General_Concept
Mode	I-General_Concept
5	O
was	O
proposed	O
with	O
operation	O
at	O
22MB/s	O
,	O
but	O
was	O
never	O
implemented	O
on	O
hard	B-Device
disks	I-Device
because	O
CPUs	O
of	O
the	O
time	O
would	O
have	O
been	O
crippled	O
waiting	O
for	O
the	O
hard	B-Device
disk	I-Device
at	O
the	O
proposed	O
PIO	O
5	O
timings	O
,	O
and	O
the	O
DMA	B-General_Concept
standard	O
ultimately	O
obviated	O
it	O
.	O
</s>
<s>
While	O
no	O
hard	B-Device
disk	I-Device
drive	I-Device
was	O
ever	O
manufactured	O
to	O
support	O
this	O
mode	O
,	O
some	O
motherboard	B-Device
manufacturers	O
preemptively	O
provided	O
BIOS	B-Operating_System
support	O
for	O
it	O
.	O
</s>
<s>
PIO	B-General_Concept
Mode	I-General_Concept
5	O
can	O
be	O
used	O
with	O
CompactFlash	B-Device
cards	I-Device
connected	O
to	O
ATA	O
via	O
CF-to-ATA	O
adapters	O
.	O
</s>
