<s>
In	O
computing	O
,	O
a	O
programmable	B-Architecture
interrupt	I-Architecture
controller	I-Architecture
(	O
PIC	O
)	O
is	O
an	O
integrated	O
circuit	O
that	O
helps	O
a	O
microprocessor	B-Architecture
(	O
or	O
CPU	B-Device
)	O
handle	O
interrupt	B-General_Concept
requests	I-General_Concept
(	O
IRQ	B-General_Concept
)	O
coming	O
from	O
multiple	O
different	O
sources	O
(	O
like	O
external	O
I/O	O
devices	O
)	O
which	O
may	O
occur	O
simultaneously	O
.	O
</s>
<s>
It	O
helps	O
prioritize	O
IRQs	B-General_Concept
so	O
that	O
the	O
CPU	B-Device
switches	O
execution	O
to	O
the	O
most	O
appropriate	O
interrupt	B-General_Concept
handler	I-General_Concept
(	O
ISR	O
)	O
after	O
the	O
PIC	O
assesses	O
the	O
IRQ	B-General_Concept
's	O
relative	O
priorities	O
.	O
</s>
<s>
PICs	B-Architecture
often	O
allow	O
mapping	O
input	O
to	O
outputs	O
in	O
a	O
configurable	O
way	O
.	O
</s>
<s>
On	O
the	O
PC	O
architecture	O
PIC	O
are	O
typically	O
embedded	O
into	O
a	O
southbridge	B-Device
chip	I-Device
whose	O
internal	O
architecture	O
is	O
defined	O
by	O
the	O
chipset	O
vendor	O
's	O
standards	O
.	O
</s>
<s>
PICs	B-Architecture
typically	O
have	O
a	O
common	O
set	O
of	O
registers	O
:	O
interrupt	B-Architecture
request	I-Architecture
register	I-Architecture
(	O
IRR	O
)	O
,	O
in-service	B-Architecture
register	I-Architecture
(	O
ISR	O
)	O
,	O
and	O
interrupt	B-Architecture
mask	I-Architecture
register	I-Architecture
(	O
IMR	O
)	O
.	O
</s>
<s>
The	O
ISR	O
register	O
specifies	O
which	O
interrupts	O
have	O
been	O
acknowledged	O
,	O
but	O
are	O
still	O
waiting	O
for	O
an	O
end	B-Device
of	I-Device
interrupt	I-Device
(	O
EOI	O
)	O
.	O
</s>
<s>
A	O
simple	O
register	O
schema	O
such	O
as	O
this	O
allows	O
up	O
to	O
two	O
distinct	O
interrupt	B-General_Concept
requests	I-General_Concept
to	O
be	O
outstanding	O
at	O
one	O
time	O
,	O
one	O
waiting	O
for	O
acknowledgement	O
,	O
and	O
one	O
waiting	O
for	O
EOI	O
.	O
</s>
<s>
There	O
are	O
a	O
number	O
of	O
common	O
priority	O
schemas	O
in	O
PICs	B-Architecture
including	O
hard	O
priorities	O
,	O
specific	O
priorities	O
,	O
and	O
rotating	O
priorities	O
.	O
</s>
<s>
One	O
of	O
the	O
best	O
known	O
PICs	B-Architecture
,	O
the	O
8259A	B-Device
,	O
was	O
included	O
in	O
the	O
x86	B-Operating_System
PC	O
.	O
</s>
<s>
In	O
modern	O
times	O
,	O
this	O
is	O
not	O
included	O
as	O
a	O
separate	O
chip	O
in	O
an	O
x86	B-Operating_System
PC	O
,	O
but	O
rather	O
as	O
part	O
of	O
the	O
motherboard	O
's	O
southbridge	B-Device
chipset	O
.	O
</s>
<s>
In	O
other	O
cases	O
,	O
it	O
has	O
been	O
replaced	O
by	O
the	O
newer	O
Advanced	B-Device
Programmable	I-Device
Interrupt	I-Device
Controllers	I-Device
which	O
support	O
more	O
interrupt	O
outputs	O
and	O
more	O
flexible	O
priority	O
schemas	O
.	O
</s>
