<s>
Processor	B-General_Concept
Consistency	I-General_Concept
is	O
one	O
of	O
the	O
consistency	B-General_Concept
models	I-General_Concept
used	O
in	O
the	O
domain	O
of	O
concurrent	B-Architecture
computing	I-Architecture
(	O
e.g.	O
</s>
<s>
in	O
distributed	B-Operating_System
shared	I-Operating_System
memory	I-Operating_System
,	O
distributed	B-General_Concept
transactions	I-General_Concept
,	O
etc	O
.	O
</s>
<s>
A	O
system	O
exhibits	O
Processor	B-General_Concept
Consistency	I-General_Concept
if	O
the	O
order	O
in	O
which	O
other	O
processors	O
see	O
the	O
writes	O
from	O
any	O
individual	O
processor	O
is	O
the	O
same	O
as	O
the	O
order	O
they	O
were	O
issued	O
.	O
</s>
<s>
Because	O
of	O
this	O
,	O
Processor	B-General_Concept
Consistency	I-General_Concept
is	O
only	O
applicable	O
to	O
systems	O
with	O
multiple	O
processors	O
.	O
</s>
<s>
It	O
is	O
weaker	O
than	O
the	O
Causal	B-General_Concept
Consistency	I-General_Concept
model	O
because	O
it	O
does	O
not	O
require	O
writes	O
from	O
all	O
processors	O
to	O
be	O
seen	O
in	O
the	O
same	O
order	O
,	O
but	O
stronger	O
than	O
the	O
PRAM	B-General_Concept
Consistency	I-General_Concept
model	O
because	O
it	O
requires	O
Cache	B-General_Concept
Coherence	I-General_Concept
.	O
</s>
<s>
Another	O
difference	O
between	O
Causal	B-General_Concept
Consistency	I-General_Concept
and	O
Processor	B-General_Concept
Consistency	I-General_Concept
is	O
that	O
Processor	B-General_Concept
Consistency	I-General_Concept
removes	O
the	O
requirements	O
for	O
loads	O
to	O
wait	O
for	O
stores	O
to	O
complete	O
,	O
and	O
for	O
Write	O
Atomicity	B-General_Concept
.	O
</s>
<s>
Processor	B-General_Concept
Consistency	I-General_Concept
is	O
also	O
stronger	O
than	O
Cache	B-General_Concept
Consistency	I-General_Concept
because	O
Processor	B-General_Concept
Consistency	I-General_Concept
requires	O
all	O
writes	O
by	O
a	O
processor	O
to	O
be	O
seen	O
in	O
order	O
,	O
not	O
just	O
writes	O
to	O
the	O
same	O
memory	O
location	O
.	O
</s>
<s>
In	O
Example	O
1	O
to	O
the	O
right	O
,	O
the	O
simple	O
system	O
follows	O
Processor	B-General_Concept
Consistency	I-General_Concept
,	O
as	O
all	O
the	O
writes	O
by	O
each	O
processor	O
are	O
seen	O
in	O
the	O
order	O
they	O
occurred	O
in	O
by	O
the	O
other	O
processors	O
,	O
and	O
the	O
transactions	O
are	O
coherent	O
.	O
</s>
<s>
Example	O
3	O
is	O
Processor	O
Consistent	O
and	O
not	O
Causally	O
Consistent	O
because	O
in	O
P3	O
:	O
for	O
Causal	B-General_Concept
Consistency	I-General_Concept
it	O
should	O
be	O
since	O
W(x )	O
2	O
in	O
P1	O
causally	O
precedes	O
W(y )	O
3	O
in	O
P2	O
.	O
</s>
<s>
Example	O
4	O
is	O
not	O
Processor	O
Consistent	O
because	O
in	O
P2	O
:	O
for	O
Processor	B-General_Concept
Consistency	I-General_Concept
it	O
should	O
be	O
because	O
W(x )	O
2	O
is	O
the	O
latest	O
write	O
to	O
x	O
preceding	O
W(y )	O
3	O
in	O
P1	O
.	O
</s>
<s>
Processor	B-General_Concept
Consistency	I-General_Concept
(	O
PC	O
)	O
relaxes	O
the	O
ordering	O
between	O
older	O
stores	O
and	O
younger	O
loads	O
that	O
is	O
enforced	O
in	O
Sequential	B-General_Concept
consistency	I-General_Concept
(	O
SC	O
)	O
.	O
</s>
<s>
The	O
prefetching	B-General_Concept
optimization	O
that	O
SC	O
systems	O
employ	O
is	O
also	O
applicable	O
to	O
PC	O
systems	O
.	O
</s>
<s>
Prefetching	B-General_Concept
is	O
the	O
act	O
of	O
fetching	O
data	O
in	O
advance	O
for	O
upcoming	O
loads	O
and	O
stores	O
before	O
it	O
is	O
actually	O
needed	O
,	O
to	O
cut	O
down	O
on	O
load/store	O
latency	O
.	O
</s>
<s>
Since	O
PC	O
reduces	O
load	O
latency	O
by	O
allowing	O
loads	O
to	O
be	O
re-ordered	O
before	O
corresponding	O
stores	O
,	O
the	O
need	O
for	O
prefetching	B-General_Concept
is	O
somewhat	O
reduced	O
,	O
as	O
the	O
prefetched	O
data	O
will	O
be	O
used	O
more	O
for	O
stores	O
than	O
for	O
loads	O
.	O
</s>
<s>
This	O
operation	O
,	O
however	O
,	O
is	O
usually	O
implemented	O
with	O
a	O
store	O
conditional	O
or	O
atomic	B-General_Concept
instruction	I-General_Concept
,	O
so	O
that	O
if	O
the	O
operation	O
fails	O
it	O
will	O
be	O
repeated	O
later	O
and	O
all	O
the	O
younger	O
loads	O
will	O
also	O
be	O
repeated	O
.	O
</s>
<s>
Processor	B-General_Concept
consistency	I-General_Concept
,	O
while	O
weaker	O
than	O
sequential	B-General_Concept
consistency	I-General_Concept
,	O
is	O
still	O
in	O
most	O
cases	O
a	O
stronger	O
consistency	B-General_Concept
model	I-General_Concept
than	O
is	O
needed	O
.	O
</s>
<s>
However	O
,	O
weak	O
ordering	O
does	O
impose	O
some	O
of	O
the	O
same	O
restrictions	O
as	O
processor	B-General_Concept
consistency	I-General_Concept
,	O
namely	O
that	O
the	O
system	O
must	O
remain	O
coherent	O
and	O
thus	O
all	O
writes	O
to	O
the	O
same	O
memory	O
location	O
must	O
be	O
seen	O
by	O
all	O
processors	O
in	O
the	O
same	O
order	O
.	O
</s>
<s>
Similar	O
to	O
weak	O
ordering	O
,	O
the	O
release	O
consistency	B-General_Concept
model	I-General_Concept
allows	O
reordering	O
of	O
all	O
memory	O
operations	O
,	O
but	O
it	O
gets	O
even	O
more	O
specific	O
and	O
breaks	O
down	O
synchronization	O
operations	O
to	O
allow	O
more	O
relaxation	O
of	O
reorders	O
.	O
</s>
<s>
Both	O
of	O
these	O
models	O
assume	O
proper	O
synchronization	O
of	O
code	O
and	O
in	O
some	O
cases	O
hardware	O
synchronization	O
support	O
,	O
and	O
so	O
processor	B-General_Concept
consistency	I-General_Concept
is	O
a	O
safer	O
model	O
to	O
adhere	O
to	O
if	O
one	O
is	O
unsure	O
about	O
the	O
reliability	O
of	O
the	O
programs	O
to	O
be	O
run	O
using	O
the	O
model	O
.	O
</s>
<s>
One	O
of	O
the	O
main	O
components	O
of	O
processor	B-General_Concept
consistency	I-General_Concept
is	O
that	O
if	O
a	O
write	O
followed	O
by	O
a	O
read	O
is	O
allowed	O
to	O
execute	O
out	O
of	O
program	O
order	O
.	O
</s>
<s>
Since	O
many	O
applications	O
function	O
correctly	O
with	O
this	O
structure	O
,	O
systems	O
that	O
implement	O
this	O
type	O
of	O
relaxed	O
ordering	O
typically	O
appear	O
sequentially	B-General_Concept
consistent	I-General_Concept
.	O
</s>
<s>
Two	O
other	O
models	O
that	O
conform	O
to	O
this	O
specification	O
are	O
the	O
SPARC	B-Architecture
V8	I-Architecture
TSO	O
(	O
Total	O
Store	O
Ordering	O
)	O
and	O
the	O
IBM-370	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
V8	I-Architecture
TSO	O
model	O
is	O
very	O
similar	O
to	O
the	O
IBM-370	O
model	O
with	O
the	O
key	O
difference	O
that	O
it	O
allows	O
operations	O
to	O
the	O
same	O
location	O
to	O
complete	O
out	O
of	O
program	O
order	O
.	O
</s>
<s>
These	O
models	O
are	O
similar	O
to	O
processor	B-General_Concept
consistency	I-General_Concept
,	O
but	O
whereas	O
these	O
models	O
only	O
have	O
one	O
copy	O
of	O
memory	O
,	O
processor	B-General_Concept
consistency	I-General_Concept
has	O
no	O
such	O
restriction	O
.	O
</s>
<s>
This	O
suggests	O
a	O
system	O
in	O
which	O
each	O
processor	O
has	O
its	O
own	O
memory	O
,	O
which	O
emphasizes	O
upon	O
processor	B-General_Concept
consistency	I-General_Concept
the	O
“	O
coherence	O
requirement.	O
"	O
</s>
<s>
The	O
total	O
store	O
model	O
,	O
as	O
the	O
name	O
suggests	O
,	O
is	O
very	O
similar	O
to	O
the	O
SPARC	B-Architecture
V8	I-Architecture
.	O
</s>
<s>
The	O
differences	O
in	O
the	O
x86	O
and	O
SPARC	B-Architecture
TSO	O
models	O
is	O
in	O
the	O
omission	O
of	O
some	O
instructions	O
and	O
inclusion	O
of	O
others	O
,	O
but	O
the	O
models	O
themselves	O
are	O
very	O
similar	O
.	O
</s>
