<s>
Fetching	O
the	O
instruction	B-Language
opcodes	I-Language
from	O
program	O
memory	B-General_Concept
well	O
in	O
advance	O
is	O
known	O
as	O
prefetching	B-General_Concept
and	O
it	O
is	O
served	O
by	O
using	O
prefetch	B-General_Concept
input	I-General_Concept
queue	I-General_Concept
(	O
PIQ	O
)	O
.The	O
pre-fetched	O
instructions	O
are	O
stored	O
in	O
data	B-Architecture
structure	O
-	O
namely	O
a	O
queue	B-Application
.	O
</s>
<s>
The	O
fetching	O
of	O
opcodes	B-Language
well	O
in	O
advance	O
,	O
prior	O
to	O
their	O
need	O
for	O
execution	O
increases	O
the	O
overall	O
efficiency	O
of	O
the	O
processor	B-Architecture
boosting	O
its	O
speed	O
.	O
</s>
<s>
The	O
processor	B-Architecture
no	O
longer	O
has	O
to	O
wait	O
for	O
the	O
memory	B-General_Concept
access	O
operations	O
for	O
the	O
subsequent	O
instruction	B-Language
opcode	I-Language
to	O
complete	O
.	O
</s>
<s>
This	O
architecture	O
was	O
prominently	O
used	O
in	O
the	O
Intel	B-General_Concept
8086	I-General_Concept
microprocessor	I-General_Concept
.	O
</s>
<s>
Pipelining	B-General_Concept
was	O
brought	O
to	O
the	O
forefront	O
of	O
computing	O
architecture	O
design	O
during	O
the	O
1960s	O
due	O
to	O
the	O
need	O
for	O
faster	O
and	O
more	O
efficient	O
computing	O
.	O
</s>
<s>
Pipelining	B-General_Concept
is	O
the	O
broader	O
concept	O
and	O
most	O
modern	O
processors	O
load	O
their	O
instructions	O
some	O
clock	O
cycles	O
before	O
they	O
execute	O
them	O
.	O
</s>
<s>
This	O
is	O
achieved	O
by	O
pre-loading	O
machine	B-Language
code	I-Language
from	O
memory	B-General_Concept
into	O
a	O
prefetch	B-General_Concept
input	I-General_Concept
queue	I-General_Concept
.	O
</s>
<s>
This	O
behavior	O
only	O
applies	O
to	O
von	B-Architecture
Neumann	I-Architecture
computers	I-Architecture
(	O
that	O
is	O
,	O
not	O
Harvard	B-Architecture
architecture	I-Architecture
computers	O
)	O
that	O
can	O
run	O
self-modifying	B-Application
code	I-Application
and	O
have	O
some	O
sort	O
of	O
instruction	B-General_Concept
pipelining	I-General_Concept
.	O
</s>
<s>
Usually	O
,	O
the	O
prefetching	B-General_Concept
behavior	O
of	O
the	O
PIQ	O
is	O
invisible	O
to	O
the	O
programming	O
model	O
of	O
the	O
CPU	O
.	O
</s>
<s>
When	O
the	O
x86-processor	O
changes	O
mode	O
from	O
realmode	B-Application
to	O
protected	B-Application
mode	I-Application
and	O
vice	O
versa	O
,	O
the	O
PIQ	O
has	O
to	O
be	O
flushed	O
,	O
or	O
else	O
the	O
CPU	O
will	O
continue	O
to	O
translate	O
the	O
machine	B-Language
code	I-Language
as	O
if	O
it	O
were	O
written	O
in	O
its	O
last	O
mode	O
.	O
</s>
<s>
If	O
the	O
PIQ	O
is	O
not	O
flushed	O
,	O
the	O
processor	B-Architecture
might	O
translate	O
its	O
codes	O
wrong	O
and	O
generate	O
an	O
invalid	O
instruction	O
exception	B-General_Concept
.	O
</s>
<s>
When	O
executing	O
self-modifying	B-Application
code	I-Application
,	O
a	O
change	O
in	O
the	O
processor	B-Architecture
code	O
immediately	O
in	O
front	O
of	O
the	O
current	O
location	O
of	O
execution	O
might	O
not	O
change	O
how	O
the	O
processor	B-Architecture
interprets	O
the	O
code	O
,	O
as	O
it	O
is	O
already	O
loaded	O
into	O
its	O
PIQ	O
.	O
</s>
<s>
It	O
simply	O
executes	O
its	O
old	O
copy	O
already	O
loaded	O
in	O
the	O
PIQ	O
instead	O
of	O
the	O
new	O
and	O
altered	O
version	O
of	O
the	O
code	O
in	O
its	O
RAM	B-Architecture
and/or	O
cache	B-General_Concept
.	O
</s>
<s>
This	O
behavior	O
of	O
the	O
PIQ	O
can	O
be	O
used	O
to	O
determine	O
if	O
code	O
is	O
being	O
executed	O
inside	O
an	O
emulator	B-Application
or	O
directly	O
on	O
the	O
hardware	O
of	O
a	O
real	O
CPU	O
.	O
</s>
<s>
Most	O
emulators	B-Application
will	O
probably	O
never	O
simulate	O
this	O
behavior	O
.	O
</s>
<s>
If	O
the	O
PIQ-size	O
is	O
zero	O
(	O
changes	O
in	O
the	O
code	O
always	O
affect	O
the	O
state	O
of	O
the	O
processor	B-Architecture
immediately	O
)	O
,	O
it	O
can	O
be	O
deduced	O
that	O
either	O
the	O
code	O
is	O
being	O
executed	O
in	O
an	O
emulator	B-Application
or	O
the	O
processor	B-Architecture
invalidates	O
the	O
PIQ	O
upon	O
writes	O
to	O
addresses	O
loaded	O
in	O
the	O
PIQ	O
.	O
</s>
<s>
It	O
was	O
A.K	O
Erlang	O
(	O
1878-1929	O
)	O
who	O
first	O
conceived	O
of	O
a	O
queue	B-Application
as	O
a	O
solution	O
to	O
congestion	O
in	O
telephone	O
traffic	O
.	O
</s>
<s>
M/M/1	O
Model	O
(	O
Single	O
Queue	B-Application
Single	O
Server/	O
Markovian	O
)	O
:	O
In	O
this	O
model	O
,	O
elements	O
of	O
queue	B-Application
are	O
served	O
on	O
a	O
first-come	O
,	O
first-served	O
basis	O
.	O
</s>
<s>
This	O
kind	O
of	O
model	O
can	O
also	O
model	O
scenarios	O
with	O
impatient	O
users	O
who	O
leave	O
the	O
queue	B-Application
immediately	O
if	O
they	O
are	O
not	O
receiving	O
service	O
.	O
</s>
<s>
Generally	O
in	O
applications	O
like	O
prefetch	B-General_Concept
input	I-General_Concept
queue	I-General_Concept
,	O
M/M/1	O
Model	O
is	O
popularly	O
used	O
because	O
of	O
limited	O
use	O
of	O
queue	B-Application
features	O
.	O
</s>
<s>
In	O
this	O
model	O
in	O
accordance	O
with	O
microprocessors	B-Architecture
,	O
the	O
user	O
takes	O
the	O
role	O
of	O
the	O
execution	B-General_Concept
unit	I-General_Concept
and	O
server	O
is	O
the	O
bus	O
interface	O
unit	O
.	O
</s>
<s>
The	O
processor	B-Architecture
executes	O
a	O
program	O
by	O
fetching	O
the	O
instructions	O
from	O
memory	B-General_Concept
and	O
executing	O
them	O
.	O
</s>
<s>
Usually	O
the	O
processor	B-Architecture
execution	O
speed	O
is	O
much	O
faster	O
than	O
the	O
memory	B-General_Concept
access	O
speed	O
.	O
</s>
<s>
Instruction	O
queue	B-Application
is	O
used	O
to	O
prefetch	O
the	O
next	O
instructions	O
in	O
a	O
separate	O
buffer	O
while	O
the	O
processor	B-Architecture
is	O
executing	O
the	O
current	O
instruction	O
.	O
</s>
<s>
With	O
a	O
four	B-General_Concept
stage	I-General_Concept
pipeline	I-General_Concept
,	O
the	O
rate	O
at	O
which	O
instructions	O
are	O
executed	O
can	O
be	O
up	O
to	O
four	O
times	O
that	O
of	O
sequential	O
execution	O
.	O
</s>
<s>
The	O
processor	B-Architecture
usually	O
has	O
two	O
separate	O
units	O
for	O
fetching	O
the	O
instructions	O
and	O
for	O
executing	O
the	O
instructions	O
.	O
</s>
<s>
The	O
implementation	O
of	O
a	O
pipeline	B-General_Concept
architecture	I-General_Concept
is	O
possible	O
only	O
if	O
the	O
bus	O
interface	O
unit	O
and	O
the	O
execution	B-General_Concept
unit	I-General_Concept
are	O
independent	O
.	O
</s>
<s>
While	O
the	O
execution	B-General_Concept
unit	I-General_Concept
is	O
decoding	O
or	O
executing	O
an	O
instruction	O
which	O
does	O
not	O
require	O
the	O
use	O
of	O
the	O
data	B-Architecture
and	O
address	O
buses	O
,	O
the	O
bus	O
interface	O
unit	O
fetches	O
instruction	B-Language
opcodes	I-Language
from	O
the	O
memory	B-General_Concept
.	O
</s>
<s>
This	O
process	O
is	O
much	O
faster	O
than	O
sending	O
out	O
an	O
address	O
,	O
reading	O
the	O
opcode	B-Language
and	O
then	O
decoding	O
and	O
executing	O
it	O
.	O
</s>
<s>
Fetching	O
the	O
next	O
instruction	O
while	O
the	O
current	O
instruction	O
is	O
being	O
decoded	O
or	O
executed	O
is	O
called	O
pipelining	B-General_Concept
.	O
</s>
<s>
The	O
8086	B-General_Concept
architecture	O
has	O
a	O
six-byte	O
prefetch	O
instruction	B-General_Concept
pipeline	I-General_Concept
,	O
while	O
the	O
8088	B-Device
has	O
a	O
four-byte	O
prefetch	O
.	O
</s>
<s>
As	O
the	O
Execution	B-General_Concept
Unit	I-General_Concept
is	O
executing	O
the	O
current	O
instruction	O
,	O
the	O
bus	O
interface	O
unit	O
reads	O
up	O
to	O
six	O
(	O
or	O
four	O
)	O
bytes	O
of	O
opcodes	B-Language
in	O
advance	O
from	O
the	O
memory	B-General_Concept
.	O
</s>
<s>
The	O
queue	B-Application
lengths	O
were	O
chosen	O
based	O
on	O
simulation	O
studies	O
.	O
</s>
<s>
An	O
exception	B-General_Concept
is	O
encountered	O
when	O
the	O
execution	B-General_Concept
unit	I-General_Concept
encounters	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
i.e.	O
</s>
<s>
In	O
this	O
case	O
,	O
the	O
entire	O
queue	B-Application
must	O
be	O
dumped	O
and	O
the	O
contents	O
pointed	O
to	O
by	O
the	O
instruction	O
pointer	O
must	O
be	O
fetched	O
from	O
memory	B-General_Concept
.	O
</s>
<s>
Processors	O
implementing	O
the	O
instruction	O
queue	B-Application
prefetch	O
algorithm	O
are	O
rather	O
technically	O
advanced	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
design	I-General_Concept
level	O
complexity	O
of	O
the	O
such	O
processors	O
is	O
much	O
higher	O
than	O
for	O
regular	O
processors	O
.	O
</s>
<s>
This	O
is	O
primarily	O
because	O
of	O
the	O
need	O
to	O
implement	O
two	O
separate	O
units	O
,	O
the	O
BIU	B-General_Concept
and	O
EU	B-General_Concept
,	O
operating	O
separately	O
.	O
</s>
<s>
These	O
processors	O
are	O
relatively	O
costlier	O
than	O
their	O
counterparts	O
without	O
the	O
prefetch	B-General_Concept
input	I-General_Concept
queue	I-General_Concept
.	O
</s>
<s>
However	O
,	O
these	O
disadvantages	O
are	O
greatly	O
offset	O
by	O
the	O
improvement	O
in	O
processor	B-Architecture
execution	O
time	O
.	O
</s>
<s>
After	O
the	O
introduction	O
of	O
prefetch	B-General_Concept
instruction	I-General_Concept
queue	I-General_Concept
in	O
the	O
8086	B-General_Concept
processor	B-Architecture
,	O
all	O
successive	O
processors	O
have	O
incorporated	O
this	O
feature	O
.	O
</s>
<s>
This	O
self-modifying	B-Application
program	I-Application
will	O
overwrite	O
the	O
jmp	O
to_the_end	O
with	O
two	O
NOPs	B-Language
(	O
which	O
is	O
encoded	O
as	O
0x9090	O
)	O
.	O
</s>
<s>
The	O
jump	O
jmp	O
near	O
to_the_end	O
is	O
assembled	O
into	O
two	O
bytes	O
of	O
machine	B-Language
code	I-Language
,	O
so	O
the	O
two	O
NOPs	B-Language
will	O
just	O
overwrite	O
this	O
jump	O
and	O
nothing	O
else	O
.	O
</s>
<s>
Because	O
the	O
machine	B-Language
code	I-Language
of	O
the	O
jump	O
is	O
already	O
read	O
into	O
the	O
PIQ	O
,	O
and	O
probably	O
also	O
already	O
executed	O
by	O
the	O
processor	B-Architecture
(	O
superscalar	B-General_Concept
processors	I-General_Concept
execute	O
several	O
instructions	O
at	O
once	O
,	O
but	O
they	O
"	O
pretend	O
"	O
that	O
they	O
do	O
n't	O
because	O
of	O
the	O
need	O
for	O
backward	B-General_Concept
compatibility	I-General_Concept
)	O
,	O
the	O
change	O
of	O
the	O
code	O
will	O
not	O
have	O
any	O
change	O
of	O
the	O
execution	O
flow	O
.	O
</s>
<s>
This	O
is	O
an	O
example	O
NASM-syntax	O
self-modifying	B-Application
x86-assembly	O
language	O
algorithm	O
that	O
determines	O
the	O
size	O
of	O
the	O
PIQ	O
:	O
</s>
<s>
What	O
this	O
code	O
does	O
is	O
basically	O
that	O
it	O
changes	O
the	O
execution	O
flow	O
,	O
and	O
determines	O
by	O
brute	B-Algorithm
force	I-Algorithm
how	O
large	O
the	O
PIQ	O
is	O
.	O
</s>
<s>
If	O
it	O
is	O
far	O
enough	O
,	O
the	O
change	O
of	O
the	O
code	O
will	O
affect	O
the	O
program	O
and	O
the	O
program	O
has	O
then	O
found	O
the	O
size	O
of	O
the	O
processor	B-Architecture
's	O
PIQ	O
.	O
</s>
<s>
If	O
this	O
code	O
is	O
being	O
executed	O
under	O
multitasking	O
OS	O
,	O
the	O
context	B-Operating_System
switch	I-Operating_System
may	O
lead	O
to	O
the	O
wrong	O
value	O
.	O
</s>
