<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
predication	B-General_Concept
is	O
a	O
feature	O
that	O
provides	O
an	O
alternative	O
to	O
conditional	B-Language
transfer	O
of	O
control	O
,	O
as	O
implemented	O
by	O
conditional	B-General_Concept
branch	I-General_Concept
machine	B-Language
instructions	I-Language
.	O
</s>
<s>
Predication	B-General_Concept
works	O
by	O
having	O
conditional	B-Language
(	O
predicated	O
)	O
non-branch	O
instructions	O
associated	O
with	O
a	O
predicate	O
,	O
a	O
Boolean	O
value	O
used	O
by	O
the	O
instruction	O
to	O
control	O
whether	O
the	O
instruction	O
is	O
allowed	O
to	O
modify	O
the	O
architectural	O
state	O
or	O
not	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
predicated	O
move	O
instruction	O
(	O
a	O
conditional	B-General_Concept
move	I-General_Concept
)	O
will	O
only	O
modify	O
the	O
destination	O
if	O
the	O
predicate	O
is	O
true	O
.	O
</s>
<s>
Thus	O
,	O
instead	O
of	O
using	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
to	O
select	O
an	O
instruction	O
or	O
a	O
sequence	O
of	O
instructions	O
to	O
execute	B-General_Concept
based	O
on	O
the	O
predicate	O
that	O
controls	O
whether	O
the	O
branch	B-General_Concept
occurs	O
,	O
the	O
instructions	O
to	O
be	O
executed	O
are	O
associated	O
with	O
that	O
predicate	O
,	O
so	O
that	O
they	O
will	O
be	O
executed	O
,	O
or	O
not	O
executed	O
,	O
based	O
on	O
whether	O
that	O
predicate	O
is	O
true	O
or	O
false	O
.	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
,	O
some	O
SIMD	B-Device
ISAs	O
(	O
such	O
as	O
AVX2	O
and	O
AVX-512	B-General_Concept
)	O
and	O
GPUs	B-Architecture
in	O
general	O
make	O
heavy	O
use	O
of	O
predication	B-General_Concept
,	O
applying	O
one	O
bit	O
of	O
a	O
conditional	B-Language
mask	O
vector	O
to	O
the	O
corresponding	O
elements	O
in	O
the	O
vector	O
registers	B-General_Concept
being	O
processed	O
,	O
whereas	O
scalar	O
predication	B-General_Concept
in	O
scalar	O
instruction	O
sets	O
only	O
need	O
the	O
one	O
predicate	O
bit	O
.	O
</s>
<s>
Where	O
predicate	O
masks	O
become	O
particularly	O
powerful	O
in	O
vector	B-Operating_System
processing	I-Operating_System
is	O
if	O
an	O
array	O
of	O
condition	O
codes	O
,	O
one	O
per	O
vector	O
element	O
,	O
may	O
feed	O
back	O
into	O
predicate	O
masks	O
that	O
are	O
then	O
applied	O
to	O
subsequent	O
vector	O
instructions	O
.	O
</s>
<s>
Most	O
computer	B-Application
programs	I-Application
contain	O
conditional	B-Language
code	O
,	O
which	O
will	O
be	O
executed	O
only	O
under	O
specific	O
conditions	O
depending	O
on	O
factors	O
that	O
cannot	O
be	O
determined	O
beforehand	O
,	O
for	O
example	O
depending	O
on	O
user	O
input	O
.	O
</s>
<s>
As	O
the	O
majority	O
of	O
processors	B-General_Concept
simply	O
execute	B-General_Concept
the	O
next	O
instruction	O
in	O
a	O
sequence	O
,	O
the	O
traditional	O
solution	O
is	O
to	O
insert	O
branch	B-General_Concept
instructions	I-General_Concept
that	O
allow	O
a	O
program	O
to	O
conditionally	O
branch	B-General_Concept
to	O
a	O
different	O
section	O
of	O
code	O
,	O
thus	O
changing	O
the	O
next	O
step	O
in	O
the	O
sequence	O
.	O
</s>
<s>
This	O
was	O
sufficient	O
until	O
designers	O
began	O
improving	O
performance	O
by	O
implementing	O
instruction	B-General_Concept
pipelining	I-General_Concept
,	O
a	O
method	O
which	O
is	O
slowed	O
down	O
by	O
branches	O
.	O
</s>
<s>
For	O
a	O
more	O
thorough	O
description	O
of	O
the	O
problems	O
which	O
arose	O
,	O
and	O
a	O
popular	O
solution	O
,	O
see	O
branch	B-General_Concept
predictor	I-General_Concept
.	O
</s>
<s>
Consider	O
the	O
following	O
pseudocode	B-Language
:	O
</s>
<s>
On	O
a	O
system	O
that	O
uses	O
conditional	B-Language
branching	I-Language
,	O
this	O
might	O
translate	O
to	O
machine	B-Language
instructions	I-Language
looking	O
similar	O
to	O
:	O
</s>
<s>
With	O
predication	B-General_Concept
,	O
all	O
possible	O
branch	B-General_Concept
paths	B-General_Concept
are	O
coded	O
inline	O
,	O
but	O
some	O
instructions	O
execute	B-General_Concept
while	O
others	O
do	O
not	O
.	O
</s>
<s>
The	O
basic	O
idea	O
is	O
that	O
each	O
instruction	O
is	O
associated	O
with	O
a	O
predicate	O
(	O
the	O
word	O
here	O
used	O
similarly	O
to	O
its	O
usage	O
in	O
predicate	O
logic	B-General_Concept
)	O
and	O
that	O
the	O
instruction	O
will	O
only	O
be	O
executed	O
if	O
the	O
predicate	O
is	O
true	O
.	O
</s>
<s>
The	O
machine	B-Language
code	I-Language
for	O
the	O
above	O
example	O
using	O
predication	B-General_Concept
might	O
look	O
something	O
like	O
this	O
:	O
</s>
<s>
Predication	B-General_Concept
's	O
simplest	O
form	O
is	O
partial	O
predication	B-General_Concept
,	O
where	O
the	O
architecture	O
has	O
conditional	B-General_Concept
move	I-General_Concept
or	O
conditional	B-Language
select	O
instructions	O
.	O
</s>
<s>
Conditional	B-General_Concept
move	I-General_Concept
instructions	O
write	O
the	O
contents	O
of	O
one	O
register	O
over	O
another	O
only	O
if	O
the	O
predicate	O
's	O
value	O
is	O
true	O
,	O
whereas	O
conditional	B-Language
select	O
instructions	O
choose	O
which	O
of	O
two	O
registers	B-General_Concept
has	O
its	O
contents	O
written	O
to	O
a	O
third	O
based	O
on	O
the	O
predicate	O
's	O
value	O
.	O
</s>
<s>
A	O
more	O
generalized	O
and	O
capable	O
form	O
is	O
full	O
predication	B-General_Concept
.	O
</s>
<s>
Full	O
predication	B-General_Concept
has	O
a	O
set	O
of	O
predicate	O
registers	B-General_Concept
for	O
storing	O
predicates	O
(	O
which	O
allows	O
multiple	O
nested	O
or	O
sequential	O
branches	O
to	O
be	O
simultaneously	O
eliminated	O
)	O
and	O
most	O
instructions	O
in	O
the	O
architecture	O
have	O
a	O
register	O
specifier	O
field	O
to	O
specify	O
which	O
predicate	O
register	O
supplies	O
the	O
predicate	O
.	O
</s>
<s>
The	O
main	O
purpose	O
of	O
predication	B-General_Concept
is	O
to	O
avoid	O
jumps	O
over	O
very	O
small	O
sections	O
of	O
program	O
code	O
,	O
increasing	O
the	O
effectiveness	O
of	O
pipelined	B-General_Concept
execution	O
and	O
avoiding	O
problems	O
with	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Elimination	O
of	O
unnecessary	O
branch	B-General_Concept
instructions	I-General_Concept
can	O
make	O
the	O
execution	O
of	O
necessary	O
branches	O
,	O
such	O
as	O
those	O
that	O
make	O
up	O
loops	O
,	O
faster	O
by	O
lessening	O
the	O
load	O
on	O
branch	B-General_Concept
prediction	I-General_Concept
mechanisms	O
.	O
</s>
<s>
Elimination	O
of	O
the	O
cost	O
of	O
a	O
branch	B-General_Concept
misprediction	I-General_Concept
which	O
can	O
be	O
high	O
on	O
deeply	O
pipelined	B-General_Concept
architectures	O
.	O
</s>
<s>
Instruction	O
sets	O
that	O
have	O
comprehensive	O
Condition	O
Codes	O
generated	O
by	O
instructions	O
may	O
reduce	O
code	O
size	O
further	O
by	O
directly	O
using	O
the	O
Condition	O
Registers	B-General_Concept
in	O
or	O
as	O
predication	B-General_Concept
.	O
</s>
<s>
Predication	B-General_Concept
's	O
primary	O
drawback	O
is	O
in	O
increased	O
encoding	O
space	O
.	O
</s>
<s>
When	O
available	O
memory	O
is	O
limited	O
,	O
as	O
on	O
embedded	B-Architecture
devices	I-Architecture
,	O
this	O
space	O
cost	O
can	O
be	O
prohibitive	O
.	O
</s>
<s>
Predication	B-General_Concept
complicates	O
the	O
hardware	O
by	O
adding	O
levels	O
of	O
logic	B-General_Concept
to	O
critical	O
paths	B-General_Concept
and	O
potentially	O
degrades	O
clock	O
speed	O
.	O
</s>
<s>
A	O
predicated	O
block	O
includes	O
cycles	O
for	O
all	O
operations	O
,	O
so	O
shorter	O
paths	B-General_Concept
may	O
take	O
longer	O
and	O
be	O
penalized	O
.	O
</s>
<s>
Predication	B-General_Concept
is	O
not	O
usually	O
speculated	O
and	O
causes	O
a	O
longer	O
dependency	O
chain	O
.	O
</s>
<s>
For	O
ordered	O
data	O
this	O
translates	O
to	O
a	O
performance	O
loss	O
compared	O
to	O
a	O
predictable	O
branch	B-General_Concept
.	O
</s>
<s>
Predication	B-General_Concept
is	O
most	O
effective	O
when	O
paths	B-General_Concept
are	O
balanced	O
or	O
when	O
the	O
longest	O
path	O
is	O
the	O
most	O
frequently	O
executed	O
,	O
but	O
determining	O
such	O
a	O
path	O
is	O
very	O
difficult	O
at	O
compile	O
time	O
,	O
even	O
in	O
the	O
presence	O
of	O
profiling	O
information	O
.	O
</s>
<s>
Predicated	O
instructions	O
were	O
popular	O
in	O
European	O
computer	B-General_Concept
designs	I-General_Concept
of	O
the	O
1950s	O
,	O
including	O
the	O
Mailüfterl	B-Device
(	O
1955	O
)	O
,	O
the	O
Zuse	B-Device
Z22	I-Device
(	O
1955	O
)	O
,	O
the	O
ZEBRA	B-Device
(	O
1958	O
)	O
,	O
and	O
the	O
Electrologica	B-Device
X1	I-Device
(	O
1958	O
)	O
.	O
</s>
<s>
The	O
IBM	B-Device
ACS-1	I-Device
design	O
of	O
1967	O
allocated	O
a	O
"	O
skip	O
"	O
bit	O
in	O
its	O
instruction	O
formats	O
,	O
and	O
the	O
CDC	O
Flexible	O
Processor	O
in	O
1976	O
allocated	O
three	O
conditional	B-Language
execution	O
bits	O
in	O
its	O
microinstruction	O
formats	O
.	O
</s>
<s>
Hewlett-Packard	O
'	O
s	O
PA-RISC	B-Device
architecture	O
(	O
1986	O
)	O
had	O
a	O
feature	O
called	O
nullification	O
,	O
which	O
allowed	O
most	O
instructions	O
to	O
be	O
predicated	O
by	O
the	O
previous	O
instruction	O
.	O
</s>
<s>
IBM	O
's	O
POWER	B-Architecture
architecture	I-Architecture
(	O
1990	O
)	O
featured	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
.	O
</s>
<s>
POWER	O
's	O
successor	O
,	O
PowerPC	B-Architecture
(	O
1993	O
)	O
,	O
dropped	O
these	O
instructions	O
.	O
</s>
<s>
Digital	O
Equipment	O
Corporation	O
's	O
Alpha	B-Device
architecture	O
(	O
1992	O
)	O
also	O
featured	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
.	O
</s>
<s>
MIPS	B-Device
gained	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
in	O
1994	O
with	O
the	O
MIPS	B-Device
IV	O
version	O
;	O
and	O
SPARC	B-Architecture
was	O
extended	O
in	O
Version	O
9	O
(	O
1994	O
)	O
with	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
for	O
both	O
integer	O
and	O
floating-point	O
registers	B-General_Concept
.	O
</s>
<s>
In	O
the	O
Hewlett-Packard/Intel	O
IA-64	B-General_Concept
architecture	O
,	O
most	O
instructions	O
are	O
predicated	O
.	O
</s>
<s>
The	O
predicates	O
are	O
stored	O
in	O
64	O
special-purpose	O
predicate	O
registers	B-General_Concept
;	O
and	O
one	O
of	O
the	O
predicate	O
registers	B-General_Concept
is	O
always	O
true	O
so	O
that	O
unpredicated	O
instructions	O
are	O
simply	O
instructions	O
predicated	O
with	O
the	O
value	O
true	O
.	O
</s>
<s>
The	O
use	O
of	O
predication	B-General_Concept
is	O
essential	O
in	O
IA-64	B-General_Concept
'	O
s	O
implementation	O
of	O
software	O
pipelining	B-General_Concept
because	O
it	O
avoids	O
the	O
need	O
for	O
writing	O
separated	O
code	O
for	O
prologs	O
and	O
epilogs	O
.	O
</s>
<s>
In	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
a	O
family	O
of	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
(	O
CMOV	O
and	O
FCMOV	O
)	O
were	O
added	O
to	O
the	O
architecture	O
by	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
(	O
1995	O
)	O
processor	O
.	O
</s>
<s>
In	O
the	O
ARM	B-Architecture
architecture	I-Architecture
,	O
the	O
original	O
32-bit	O
instruction	O
set	O
provides	O
a	O
feature	O
called	O
conditional	B-Language
execution	O
that	O
allows	O
most	O
instructions	O
to	O
be	O
predicated	O
by	O
one	O
of	O
13	O
predicates	O
that	O
are	O
based	O
on	O
some	O
combination	O
of	O
the	O
four	O
condition	O
codes	O
set	O
by	O
the	O
previous	O
instruction	O
.	O
</s>
<s>
ARM	O
's	O
Thumb	O
instruction	O
set	O
(	O
1994	O
)	O
dropped	O
conditional	B-Language
execution	O
to	O
reduce	O
the	O
size	O
of	O
instructions	O
so	O
they	O
could	O
fit	O
in	O
16	O
bits	O
,	O
but	O
its	O
successor	O
,	O
Thumb-2	O
(	O
2003	O
)	O
overcame	O
this	O
problem	O
by	O
using	O
a	O
special	O
instruction	O
which	O
has	O
no	O
effect	O
other	O
than	O
to	O
supply	O
predicates	O
for	O
the	O
following	O
four	O
instructions	O
.	O
</s>
<s>
The	O
64-bit	O
instruction	O
set	O
introduced	O
in	O
ARMv8-A	O
(	O
2011	O
)	O
replaced	O
conditional	B-Language
execution	O
with	O
conditional	B-Language
selection	O
instructions	O
.	O
</s>
<s>
Some	O
SIMD	B-Device
instruction	O
sets	O
,	O
like	O
AVX2	O
,	O
have	O
the	O
ability	O
to	O
use	O
a	O
logical	O
mask	O
to	O
conditionally	O
load/store	O
values	O
to	O
memory	O
,	O
a	O
parallel	O
form	O
of	O
the	O
conditional	B-General_Concept
move	I-General_Concept
,	O
and	O
may	O
also	O
apply	O
individual	O
mask	O
bits	O
to	O
individual	O
arithmetic	O
units	O
executing	O
a	O
parallel	O
operation	O
.	O
</s>
<s>
This	O
form	O
of	O
predication	B-General_Concept
is	O
also	O
used	O
in	O
vector	B-Operating_System
processors	I-Operating_System
and	O
single	B-General_Concept
instruction	I-General_Concept
,	I-General_Concept
multiple	I-General_Concept
threads	I-General_Concept
GPU	B-Architecture
computing	O
.	O
</s>
<s>
All	O
the	O
techniques	O
,	O
advantages	O
and	O
disadvantages	O
of	O
single	O
scalar	O
predication	B-General_Concept
apply	O
just	O
as	O
well	O
to	O
the	O
parallel	O
processing	O
case	O
.	O
</s>
