<s>
The	O
Power	B-General_Concept
Processing	I-General_Concept
Element	I-General_Concept
(	O
PPE	O
)	O
comprises	O
a	O
Power	B-General_Concept
Processing	I-General_Concept
Unit	I-General_Concept
(	O
PPU	O
)	O
and	O
a	O
512	O
KB	O
L2	O
cache	O
.	O
</s>
<s>
The	O
PPU	O
is	O
a	O
64-bit	B-Device
dual-threaded	B-General_Concept
in-order	B-General_Concept
PowerPC	B-Architecture
2.02	I-Architecture
microprocessor	B-Architecture
core	I-Architecture
designed	O
by	O
IBM	O
for	O
use	O
primarily	O
in	O
the	O
game	O
consoles	O
PlayStation	B-Operating_System
3	I-Operating_System
and	O
Xbox	B-Operating_System
360	I-Operating_System
,	O
but	O
has	O
also	O
found	O
applications	O
in	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
in	O
supercomputers	B-Architecture
such	O
as	O
the	O
record	O
setting	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
.	O
</s>
<s>
The	O
PPU	O
is	O
used	O
as	O
a	O
main	O
CPU	B-Architecture
core	I-Architecture
in	O
three	O
different	O
processor	O
designs	O
:	O
</s>
<s>
The	O
Cell	B-General_Concept
Broadband	I-General_Concept
Engine	I-General_Concept
(	O
Cell	B-General_Concept
BE	I-General_Concept
)	O
which	O
is	O
used	O
primarily	O
in	O
Sony	O
's	O
PlayStation	B-Operating_System
3	I-Operating_System
gaming	B-Device
console	I-Device
.	O
</s>
<s>
The	O
PowerXCell	O
8i	O
which	O
is	O
a	O
version	O
of	O
the	O
Cell	B-General_Concept
BE	I-General_Concept
with	O
enhanced	O
FPU	O
and	O
memory	O
subsystem	O
.	O
</s>
<s>
The	O
XCPU	B-Device
which	O
is	O
used	O
in	O
a	O
three	O
core	B-Architecture
configuration	O
and	O
a	O
unified	O
1	O
MB	O
L2	O
cache	O
inside	O
Microsoft	O
's	O
Xbox	B-Operating_System
360	I-Operating_System
.	O
</s>
<s>
It	O
comes	O
in	O
three	O
versions	O
,	O
the	O
90nm	O
and	O
65nm	O
versions	O
,	O
and	O
the	O
45nm	O
XCGPU	O
with	O
an	O
integrated	O
graphics	B-Architecture
processor	I-Architecture
from	O
ATI	O
.	O
</s>
<s>
The	O
PPU	O
is	O
an	O
in-order	B-General_Concept
processor	O
,	O
but	O
it	O
has	O
some	O
unique	O
traits	O
which	O
allow	O
it	O
to	O
achieve	O
some	O
benefits	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
without	O
expensive	O
re-ordering	O
hardware	O
.	O
</s>
<s>
It	O
has	O
an	O
instruction	O
delay	O
pipe	O
-	O
a	O
side	O
path	O
that	O
allows	O
it	O
to	O
execute	O
instructions	O
that	O
would	O
normally	O
cause	O
pipeline	B-General_Concept
stalls	I-General_Concept
without	O
holding	O
up	O
the	O
rest	O
of	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
instruction	O
delay	O
pipeline	B-General_Concept
is	O
used	O
for	O
the	O
Out-Of-Order	O
Load/Stores	O
:	O
cache	O
misses	O
are	O
put	O
there	O
while	O
it	O
moves	O
on	O
.	O
</s>
<s>
The	O
PPE	O
has	O
a	O
23	O
stage	O
general	O
pipeline	B-General_Concept
with	O
an	O
additional	O
11	O
stages	O
possible	O
for	O
microcode	O
and	O
an	O
additional	O
4	O
stages	O
possible	O
for	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
The	O
PPU	O
runs	O
two	O
hardware	B-Operating_System
threads	I-Operating_System
simultaneously	O
.	O
</s>
<s>
The	O
main	B-General_Concept
registers	I-General_Concept
for	O
code	O
execution	O
are	O
duplicated	O
,	O
as	O
are	O
the	O
exception	O
and	O
interrupt-handling	O
registers	B-General_Concept
,	O
and	O
several	O
essential	O
arrays	O
and	O
queues	O
.	O
</s>
<s>
They	O
can	O
generate	O
exceptions	O
simultaneously	O
,	O
and	O
perform	O
branch	B-General_Concept
prediction	I-General_Concept
on	O
their	O
individual	O
branch	O
histories	O
.	O
</s>
<s>
The	O
execution	O
engine	O
and	O
caches	O
are	O
not	O
duplicated	O
though	O
-	O
so	O
it	O
is	O
still	O
just	O
a	O
single-core	O
design	O
.	O
</s>
<s>
Its	O
64-bit	B-Device
double	O
precision	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
and	O
128-bit	O
VMX	O
unit	O
(	O
using	O
the	O
AltiVec	B-General_Concept
instruction	O
set	O
)	O
,	O
can	O
perform	O
a	O
theoretical	O
12	O
floating-point	O
operations	O
per	O
cycle	O
,	O
as	O
its	O
floating-point	B-General_Concept
unit	I-General_Concept
can	O
do	O
floating-point	O
multiply-adds	O
,	O
and	O
come	O
no	O
smaller	O
than	O
64-bits	B-Device
.	O
</s>
<s>
The	O
PPU	O
is	O
enhanced	O
in	O
the	O
PowerXCell	O
8i	O
processor	O
to	O
be	O
able	O
to	O
make	O
single	O
cycle	O
double	O
precision	O
floating	O
point	O
operations	O
,	O
tailored	O
for	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
in	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
VMX	O
unit	O
in	O
the	O
XCPU	B-Device
in	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
is	O
enhanced	O
with	O
128	O
registers	B-General_Concept
and	O
is	O
not	O
entirely	O
compatible	O
with	O
regular	O
AltiVec	B-General_Concept
.	O
</s>
