<s>
The	O
PowerPC	B-General_Concept
e6500	I-General_Concept
is	O
a	O
multithreaded	B-General_Concept
64-bit	B-Device
Power	O
ISA-based	O
microprocessor	B-Architecture
core	I-Architecture
from	O
Freescale	O
Semiconductor	O
(	O
now	O
part	O
of	O
NXP	O
)	O
.	O
</s>
<s>
e6500	O
will	O
power	O
the	O
entire	O
range	O
of	O
QorIQ	B-General_Concept
AMP	O
Series	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
processors	O
which	O
share	O
the	O
common	O
naming	O
scheme	O
:	O
"	O
Txxxx	O
"	O
.	O
</s>
<s>
It	O
has	O
a	O
revised	O
memory	O
subsystem	O
compared	O
to	O
the	O
previous	O
e5500	B-General_Concept
core	I-General_Concept
with	O
four	O
cores	O
combined	O
into	O
a	O
CPU	O
Cluster	O
,	O
sharing	O
a	O
large	O
L2	O
cache	O
and	O
the	O
e6500	O
cores	O
supports	O
up	O
to	O
eight	O
CPU	O
Clusters	O
for	O
very	O
large	O
multiprocessing	O
implementations	O
.	O
</s>
<s>
The	O
core	B-Architecture
is	O
the	O
first	O
multithreaded	B-General_Concept
core	B-Architecture
designed	O
by	O
Freescale	O
and	O
reintroduces	O
an	O
enhanced	O
version	O
of	O
AltiVec	B-General_Concept
to	O
their	O
products	O
.	O
</s>
<s>
The	O
multithreading	B-General_Concept
allows	O
for	O
two	O
virtual	O
cores	O
per	O
hard	O
core	B-Architecture
and	O
is	O
organized	O
as	O
2x2-way	O
superscalar	O
.	O
</s>
<s>
One	O
virtual	O
core	B-Architecture
in	O
an	O
e6500	O
can	O
often	O
perform	O
better	O
than	O
an	O
entire	O
e5500	B-General_Concept
core	I-General_Concept
since	O
Freescale	O
essentially	O
duplicated	O
a	O
lot	O
of	O
logic	O
instead	O
of	O
just	O
virtualizing	O
it	O
,	O
in	O
addition	O
to	O
other	O
enhancements	O
to	O
the	O
core	B-Architecture
.	O
</s>
<s>
Each	O
core	B-Architecture
has	O
five	O
integer	O
units	O
(	O
four	O
simple	O
and	O
one	O
complex	O
)	O
,	O
two	O
load-store	O
units	O
,	O
one	O
128-bit	O
AltiVec	B-General_Concept
unit	O
,	O
32+32	O
kB	O
instruction	O
and	O
data	O
L1	O
caches	O
.	O
</s>
<s>
Speeds	O
range	O
up	O
to	O
2.5GHz	O
,	O
and	O
the	O
core	B-Architecture
is	O
designed	O
to	O
be	O
highly	O
configurable	O
via	O
the	O
CoreNet	O
fabric	O
and	O
meet	O
the	O
specific	O
needs	O
of	O
embedded	B-Architecture
applications	O
with	O
features	O
like	O
multi-core	B-Architecture
operation	O
and	O
interface	O
for	O
auxiliary	O
application	O
processing	O
units	O
(	O
APU	O
)	O
.	O
</s>
<s>
The	O
e6501	O
core	B-Architecture
is	O
a	O
revision	O
introduced	O
in	O
2013	O
with	O
enhanced	O
virtualization	O
interrupt	O
support	O
.	O
</s>
<s>
QorIQ	B-General_Concept
AMP	O
Series	O
T4240	O
as	O
the	O
first	O
processor	O
revealed	O
with	O
12	O
cores	O
followed	O
by	O
T2080	O
and	O
T2081	O
with	O
four	O
cores	O
and	O
speeds	O
up	O
to	O
1.8GHz	O
.	O
</s>
<s>
QorIQ	B-General_Concept
Qonverge	O
B4420	O
and	O
B4860	O
-	O
with	O
a	O
mix	O
of	O
e6500	O
cores	O
and	O
StarCore	O
SC3900	O
DSPs	O
for	O
high	O
end	O
telecom	O
applications	O
such	O
as	O
4G/LTE	O
macrocells	O
running	O
at	O
1.6	O
and	O
1.8GHz	O
.	O
</s>
