<s>
The	O
PowerPC	B-Device
e600	I-Device
is	O
a	O
family	O
of	O
32-bit	O
PowerPC	B-Architecture
microprocessor	B-Architecture
cores	I-Architecture
developed	O
by	O
Freescale	O
for	O
primary	O
use	O
in	O
high	O
performance	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
with	O
speed	O
ranging	O
over	O
2GHz	O
,	O
thus	O
making	O
them	O
ideal	O
for	O
high	O
performance	O
routing	O
and	O
telecommunications	O
applications	O
.	O
</s>
<s>
The	O
e600	B-Device
is	O
the	O
continuation	O
of	O
the	O
PowerPC	B-Architecture
74xx	O
design	O
.	O
</s>
<s>
The	O
e600	B-Device
is	O
a	O
superscalar	B-General_Concept
out-of-order	B-General_Concept
RISC	B-Architecture
core	O
with	O
32/32	O
KB	O
L1	O
data/instruction	O
caches	B-General_Concept
,	O
a	O
seven-stage	O
,	O
three-issue	O
pipeline	B-General_Concept
with	O
load/store	O
,	O
system	O
register	O
,	O
powerful	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
integer	B-General_Concept
unit	I-General_Concept
,	O
a	O
double	O
precision	O
FPU	B-General_Concept
and	O
an	O
enhanced	O
128-bit	O
AltiVec	B-General_Concept
unit	O
with	O
limited	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
The	O
core	O
is	O
designed	O
to	O
work	O
in	O
multiprocessing	B-Operating_System
and	O
multi	B-Architecture
core	I-Architecture
designs	O
and	O
can	O
take	O
large	O
amounts	O
of	O
L2	O
caches	B-General_Concept
on	O
die	O
.	O
</s>
<s>
The	O
e600	B-Device
core	O
is	O
completely	O
backwards	O
compatible	O
with	O
the	O
PowerPC	B-Architecture
74xx	O
cores	O
from	O
which	O
it	O
derives	O
.	O
</s>
<s>
In	O
2004	O
Freescale	O
renamed	O
the	O
PowerPC	B-Architecture
74xx	O
core	O
e600	B-Device
and	O
changed	O
focus	O
from	O
general	O
CPUs	O
to	O
high	O
end	O
embedded	O
SoC	O
devices	O
,	O
and	O
introduced	O
a	O
new	O
naming	O
scheme	O
,	O
MPC86xx	O
.	O
</s>
<s>
The	O
7448	O
was	O
to	O
be	O
the	O
last	O
pure	O
74xx	O
and	O
it	O
formed	O
the	O
base	O
of	O
the	O
new	O
e600	B-Device
core	O
.	O
</s>
<s>
The	O
7448	O
is	O
an	O
evolution	O
of	O
the	O
PowerPC	B-Architecture
7447	O
and	O
is	O
essentially	O
a	O
faster	O
(	O
up	O
to	O
2GHz	O
)	O
and	O
more	O
power-efficient	O
version	O
of	O
the	O
7447B	O
manufactured	O
in	O
90nm	O
with	O
1	O
MB	O
L2	O
cache	O
and	O
up	O
to	O
200MHz	O
front	O
side	O
bus	O
and	O
it	O
features	O
Freescale	O
's	O
new	O
standard	O
core	O
,	O
the	O
e600	B-Device
.	O
</s>
<s>
The	O
problems	O
associated	O
with	O
the	O
bandwidth-constrained	O
external	O
MPX	O
bus	O
interface	O
found	O
on	O
the	O
74xx	O
series	O
are	O
relieved	O
with	O
single	O
(	O
MPC8641	O
)	O
or	O
dual	O
(	O
MPC8641D	O
)	O
e600	B-Device
cores	O
,	O
faster	O
system	O
interface	O
via	O
RapidIO	B-General_Concept
,	O
dual	O
x8	O
PCI	O
Express	O
and	O
an	O
on-die	O
667MHz	O
MPX	O
interconnect	O
between	O
I/O	O
,	O
the	O
cores	O
,	O
and	O
dual	O
64-bit	O
DDR2-memory	O
controllers	O
(	O
with	O
ECC	O
)	O
.	O
</s>
<s>
The	O
product	O
also	O
features	O
four	O
on-chip	O
Gigabit	O
Ethernet	O
controllers	O
with	O
TCP/UDP	O
offloading	O
features	O
.	O
</s>
<s>
The	O
dual	B-Architecture
core	I-Architecture
MPC8641D	O
has	O
support	O
for	O
asymmetric	B-Operating_System
multiprocessing	I-Operating_System
,	O
which	O
enables	O
two	O
operating	B-General_Concept
systems	I-General_Concept
to	O
run	O
on	O
the	O
same	O
device	O
simultaneously	O
,	O
sharing	O
resources	O
but	O
largely	O
unaware	O
of	O
each	O
other	O
.	O
</s>
<s>
The	O
MPC8641	O
(	O
single	O
core	O
)	O
and	O
MPC8641D	O
(	O
dual	B-Architecture
core	I-Architecture
)	O
are	O
manufactured	O
on	O
a	O
90nm	O
SOI	O
based	O
process	O
.	O
</s>
<s>
Introduced	O
in	O
2007	O
the	O
MPC8610	O
is	O
a	O
host	O
processor	O
with	O
integrated	O
graphics	B-Architecture
processor	I-Architecture
supporting	O
24-bit	O
screens	O
sizes	O
up	O
to	O
1280x1024	O
pixels	O
.	O
</s>
<s>
This	O
list	O
is	O
a	O
complete	O
list	O
of	O
known	O
core	O
e600	B-Device
based	O
designs	O
(	O
excluding	O
older	O
74xx	O
designs	O
)	O
.	O
</s>
