<s>
The	O
PowerPC	B-General_Concept
e5500	I-General_Concept
is	O
a	O
64-bit	B-Device
Power	O
ISA-based	O
microprocessor	B-Architecture
core	I-Architecture
from	O
Freescale	O
Semiconductor	O
.	O
</s>
<s>
The	O
core	B-Architecture
implements	O
most	O
of	O
the	O
core	B-Architecture
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.06	O
with	O
hypervisor	B-Operating_System
support	O
,	O
but	O
not	O
AltiVec	B-General_Concept
.	O
</s>
<s>
It	O
has	O
a	O
four	O
issue	O
,	O
seven-stage	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
with	O
a	O
double	O
precision	O
FPU	B-General_Concept
,	O
three	O
Integer	O
units	O
,	O
32/32	O
KB	O
data	O
and	O
instruction	O
L1	O
caches	B-General_Concept
,	O
512	O
KB	O
private	O
L2	O
cache	O
per	O
core	B-Architecture
and	O
up	O
to	O
2	O
MB	O
shared	O
L3	O
cache	O
.	O
</s>
<s>
Speeds	O
range	O
up	O
to	O
2.5GHz	O
,	O
and	O
the	O
core	B-Architecture
is	O
designed	O
to	O
be	O
highly	O
configurable	O
via	O
the	O
CoreNet	O
fabric	O
and	O
meet	O
the	O
specific	O
needs	O
of	O
embedded	B-Architecture
applications	O
with	O
features	O
like	O
multi-core	B-Architecture
operation	O
and	O
interface	O
for	O
auxiliary	O
application	O
processing	O
units	O
(	O
APU	O
)	O
.	O
</s>
<s>
The	O
e5500	O
is	O
based	O
on	O
the	O
e500mc	O
core	B-Architecture
and	O
adds	O
some	O
new	O
instructions	O
introduced	O
in	O
the	O
Power	B-Architecture
ISA	I-Architecture
2.06	O
specification	O
,	O
namely	O
some	O
byte	O
-	O
and	O
bit-level	O
acceleration	O
;	O
Parity	O
,	O
Population	O
count	O
,	O
Bit	O
permute	O
and	O
Compare	O
byte	O
.	O
</s>
<s>
The	O
FPU	B-General_Concept
is	O
taken	O
straight	O
from	O
the	O
PowerPC	B-Device
e600	I-Device
core	B-Architecture
,	O
which	O
is	O
a	O
classic	O
fully	O
pipelined	O
dual	O
precision	O
IEEE	O
754	O
unit	O
running	O
at	O
full	O
core	B-Architecture
speed	O
and	O
supports	O
conversion	O
between	O
64-bit	B-Device
floats	O
and	O
integers	O
,	O
effectively	O
twice	O
as	O
fast	O
as	O
the	O
FPU	B-General_Concept
in	O
e500mc	O
.	O
</s>
<s>
The	O
e5500	O
also	O
introduces	O
an	O
enhanced	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
with	O
an	O
8-entry	O
link	O
stack	O
.	O
</s>
<s>
The	O
e5500	O
core	B-Architecture
is	O
the	O
first	O
64-bit	B-Device
Power	B-Architecture
ISA	I-Architecture
core	B-Architecture
designed	O
solely	O
by	O
Freescale	O
and	O
was	O
introduced	O
at	O
Freescale	O
Technology	O
Forum	O
in	O
June	O
2010	O
.	O
</s>
<s>
Freescale	O
have	O
used	O
the	O
e700	O
and	O
NG-64	O
monikers	O
to	O
refer	O
to	O
a	O
very	O
similarly	O
specced	O
core	B-Architecture
since	O
2004	O
,	O
but	O
they	O
are	O
not	O
the	O
same	O
product	O
.	O
</s>
<s>
e5500	O
powers	O
the	O
high-performance	O
QorIQ	B-General_Concept
P5	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
family	O
which	O
share	O
the	O
common	O
naming	O
scheme	O
:	O
"	O
P50x0	O
"	O
.	O
</s>
<s>
BAE	O
Systems	O
has	O
built	O
a	O
radiation	O
hardened	O
computer	O
based	O
on	O
the	O
e5500	O
core	B-Architecture
for	O
devices	O
in	O
space	O
.	O
</s>
