<s>
The	O
PowerPC	B-Device
e300	I-Device
is	O
a	O
family	O
of	O
32-bit	O
PowerPC	B-Architecture
microprocessor	B-Architecture
cores	O
developed	O
by	O
Freescale	O
for	O
primary	O
use	O
in	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
with	O
speed	O
ranging	O
up	O
to	O
800MHz	O
,	O
thus	O
making	O
them	O
ideal	O
for	O
embedded	B-Architecture
applications	I-Architecture
.	O
</s>
<s>
The	O
e300	O
is	O
a	O
superscalar	B-General_Concept
RISC	B-Architecture
core	O
with	O
16/16	O
or	O
32/32	O
kB	O
L1	O
data/instruction	O
caches	O
,	O
a	O
four-stage	O
pipeline	B-General_Concept
with	O
load/store	O
,	O
system	O
register	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
integer	B-General_Concept
unit	I-General_Concept
with	O
optional	O
double	O
precision	O
FPU	B-General_Concept
.	O
</s>
<s>
The	O
e300	O
core	O
is	O
completely	O
backwards	O
compatible	O
with	O
the	O
G2	O
and	O
PowerPC	B-Architecture
603e	O
cores	O
from	O
which	O
it	O
derives	O
.	O
</s>
<s>
The	O
e300	O
core	O
is	O
the	O
CPU	B-Device
part	O
of	O
several	O
SoC	O
processors	O
from	O
Freescale	O
:	O
</s>
<s>
MSC7120	O
GPON	O
,	O
optical	O
network	O
processor	O
integrated	O
DSP	B-Architecture
unit	O
.	O
</s>
