<s>
The	O
PowerPC	B-Device
e200	I-Device
is	O
a	O
family	O
of	O
32-bit	O
Power	B-Architecture
ISA	I-Architecture
microprocessor	B-Architecture
cores	I-Architecture
developed	O
by	O
Freescale	O
for	O
primary	O
use	O
in	O
automotive	O
and	O
industrial	O
control	O
systems	O
.	O
</s>
<s>
The	O
cores	O
are	O
designed	O
to	O
form	O
the	O
CPU	B-Device
part	O
in	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
with	O
speed	O
ranging	O
up	O
to	O
600MHz	O
,	O
thus	O
making	O
them	O
ideal	O
for	O
embedded	B-Architecture
applications	I-Architecture
.	O
</s>
<s>
The	O
e200	O
core	O
is	O
developed	O
from	O
the	O
MPC5xx	B-General_Concept
family	O
processors	O
,	O
which	O
in	O
turn	O
is	O
derived	O
from	O
the	O
MPC8xx	O
core	O
in	O
the	O
PowerQUICC	B-General_Concept
SoC	O
processors	O
.	O
</s>
<s>
e200	O
adheres	O
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
as	O
well	O
as	O
the	O
previous	O
Book	O
E	O
specification	O
.	O
</s>
<s>
All	O
e200	O
core	O
based	O
microprocessors	B-Architecture
are	O
named	O
in	O
the	O
MPC55xx	O
and	O
MPC56xx/JPC56x	O
scheme	O
,	O
not	O
to	O
be	O
confused	O
with	O
the	O
MPC52xx	O
processors	O
which	O
is	O
based	O
on	O
the	O
PowerPC	B-Device
e300	I-Device
core	O
.	O
</s>
<s>
Continental	O
AG	O
and	O
Freescale	O
are	O
developing	O
SPACE	O
,	O
a	O
tri-core	B-Architecture
e200	O
based	O
processor	O
designed	O
for	O
electronic	O
brake	O
systems	O
in	O
cars	O
.	O
</s>
<s>
STMicroelectronics	O
and	O
Freescale	O
have	O
jointly	O
developed	O
microcontrollers	B-Architecture
for	O
automotive	O
applications	O
based	O
on	O
e200	O
in	O
the	O
MPC56xx/SPC56x	O
family	O
.	O
</s>
<s>
The	O
simplest	O
core	O
,	O
e200z0	O
features	O
an	O
in	B-General_Concept
order	I-General_Concept
,	O
four	O
stage	O
pipeline	B-General_Concept
.	O
</s>
<s>
It	O
has	O
no	O
MMU	B-General_Concept
,	O
no	O
cache	O
,	O
and	O
no	O
FPU	B-General_Concept
.	O
</s>
<s>
It	O
uses	O
the	O
variable	O
bit	O
length	O
(	O
VLE	O
)	O
part	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
,	O
which	O
uses	O
16-bit	O
versions	O
of	O
the	O
otherwise	O
standard	O
32-bit	O
PowerPC	B-Architecture
Book	O
E	O
ISA	O
,	O
thus	O
reducing	O
code	O
footprint	O
by	O
up	O
to	O
30%	O
.	O
</s>
<s>
It	O
has	O
a	O
single	O
32-bit	O
AMBA	B-Architecture
2.0v6	O
bus	O
interface	O
.	O
</s>
<s>
The	O
e200z0	O
is	O
used	O
in	O
the	O
MPC5510	O
as	O
an	O
optional	O
co-processor	O
alongside	O
an	O
e200z1	O
core	O
,	O
making	O
that	O
chip	O
a	O
multicore	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
The	O
e200z1	O
has	O
a	O
four-stage	O
,	O
single-issue	O
pipeline	B-General_Concept
with	O
a	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
and	O
an	O
8	O
entry	O
MMU	B-General_Concept
,	O
no	O
cache	O
and	O
no	O
FPU	B-General_Concept
.	O
</s>
<s>
It	O
can	O
use	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
ISA	O
as	O
well	O
as	O
the	O
VLE	O
instructions	O
.	O
</s>
<s>
It	O
uses	O
a	O
dual	O
32-bit	O
AMBA	B-Architecture
2.0v6	O
bus	O
interface	O
.	O
</s>
<s>
The	O
e200z3	O
has	O
a	O
four-stage	O
,	O
single-issue	O
pipeline	B-General_Concept
with	O
a	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
a	O
16	O
entry	O
MMU	B-General_Concept
and	O
a	O
SIMD	B-Device
capable	O
FPU	B-General_Concept
.	O
</s>
<s>
It	O
can	O
use	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
ISA	O
as	O
well	O
as	O
the	O
VLE	O
instructions	O
.	O
</s>
<s>
It	O
uses	O
a	O
dual	O
64-bit	O
AMBA	B-Architecture
2.0v6	O
bus	O
interface	O
.	O
</s>
<s>
The	O
e200z4	O
has	O
a	O
five-stage	O
,	O
dual-issue	O
pipeline	B-General_Concept
with	O
a	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
a	O
16	O
entry	O
MMU	B-General_Concept
,	O
signal	O
processing	O
extension	O
(	O
SPE	O
)	O
,	O
a	O
SIMD	B-Device
capable	O
single	O
precision	O
FPU	B-General_Concept
and	O
a	O
4	O
Kilobyte	O
2/4	O
-way	O
set	O
associative	O
instruction	O
L1	B-General_Concept
cache	I-General_Concept
(	O
Pseudo	O
round-robin	O
replacement	O
algorithm	O
)	O
.	O
</s>
<s>
It	O
has	O
no	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
can	O
use	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
ISA	O
as	O
well	O
as	O
the	O
VLE	O
instructions	O
.	O
</s>
<s>
It	O
uses	O
a	O
dual	O
64-bit	O
bus	O
AMBA	B-Architecture
2.0v6	O
interface	O
.	O
</s>
<s>
The	O
e200z6	O
has	O
a	O
seven-stage	O
,	O
single-issue	O
pipeline	B-General_Concept
with	O
a	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
a	O
32	O
entry	O
MMU	B-General_Concept
,	O
signal	O
processing	O
extensions	O
(	O
SPE	O
)	O
,	O
a	O
SIMD	B-Device
capable	O
single-precision	O
FPU	B-General_Concept
and	O
an	O
8-way	O
set	O
associative	O
32	O
KiB	O
unified	O
data/instruction	O
L1	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
can	O
use	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
ISA	O
as	O
well	O
as	O
the	O
VLE	O
instructions	O
.	O
</s>
<s>
It	O
uses	O
a	O
single	O
64-bit	O
bus	O
AMBA	B-Architecture
2.0v6	O
interface	O
.	O
</s>
<s>
The	O
e200z7	O
has	O
a	O
ten-stage	O
,	O
dual-issue	O
pipeline	B-General_Concept
with	O
a	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
a	O
32	O
entry	O
MMU	B-General_Concept
,	O
a	O
SIMD	B-Device
capable	O
single-precision	O
FPU	B-General_Concept
and	O
16-KB	O
,	O
4	O
way	O
set-associative	O
Harvard	O
instruction	O
and	O
data	O
L1	O
caches	O
.	O
</s>
<s>
It	O
can	O
use	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
ISA	O
as	O
well	O
as	O
the	O
VLE	O
instructions	O
.	O
</s>
<s>
It	O
uses	O
a	O
32-bit	O
bus	O
AMBA	B-Architecture
2.0v6	O
interface	O
for	O
the	O
address	O
bus	O
,	O
and	O
a	O
64-bit	O
data	O
bus	O
(	O
plus	O
attributes	O
and	O
control	O
on	O
each	O
bus	O
)	O
.	O
</s>
