<s>
The	O
PowerPC	B-General_Concept
600	I-General_Concept
family	O
was	O
the	O
first	O
family	O
of	O
PowerPC	B-Architecture
processors	I-Architecture
built	O
.	O
</s>
<s>
Somerset	O
was	O
opened	O
in	O
1992	O
and	O
its	O
goal	O
was	O
to	O
make	O
the	O
first	O
PowerPC	B-Architecture
processor	I-Architecture
and	O
then	O
keep	O
designing	O
general	O
purpose	O
PowerPC	B-Architecture
processors	I-Architecture
for	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
The	O
first	O
incarnation	O
became	O
the	O
PowerPC	B-Architecture
601	O
in	O
1993	O
,	O
and	O
the	O
second	O
generation	O
soon	O
followed	O
with	O
the	O
PowerPC	B-Architecture
603	O
,	O
PowerPC	B-Architecture
604	O
and	O
the	O
64-bit	B-Device
PowerPC	B-Architecture
620	O
.	O
</s>
<s>
CPUPipeline	O
stagesMiscPowerPC	O
60143	O
execution	O
units	O
,	O
static	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
SMP	B-Operating_System
support.PowerPC	O
60345	O
execution	O
units	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
No	O
SMP.PowerPC	O
6046Superscalar	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
6	O
execution	O
units	O
.	O
</s>
<s>
SMP	B-Operating_System
support.PowerPC	O
6205Out-of-order	O
execution	O
-	O
SMP	B-Operating_System
support	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
601	O
was	O
the	O
first	O
generation	O
of	O
microprocessors	B-Architecture
to	O
support	O
the	O
basic	O
32-bit	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
first	O
601	O
processors	B-Architecture
were	O
introduced	O
in	O
an	O
IBM	B-Device
RS/6000	I-Device
workstation	B-Device
in	O
October	O
1993	O
(	O
alongside	O
its	O
more	O
powerful	O
multichip	O
cousin	O
IBM	O
POWER2	B-General_Concept
line	O
of	O
processors	B-Architecture
)	O
and	O
the	O
first	O
Apple	B-Device
Power	I-Device
Macintoshes	I-Device
on	O
March	O
14	O
,	O
1994	O
.	O
</s>
<s>
The	O
601	O
was	O
the	O
first	O
advanced	O
single-chip	O
implementation	O
of	O
the	O
POWER/PowerPC	O
architecture	O
designed	O
on	O
a	O
crash	O
schedule	O
to	O
establish	O
PowerPC	B-Architecture
in	O
the	O
marketplace	O
and	O
cement	O
the	O
AIM	O
alliance	O
.	O
</s>
<s>
In	O
order	O
to	O
achieve	O
an	O
extremely	O
aggressive	O
schedule	O
while	O
including	O
substantially	O
new	O
functionality	O
(	O
such	O
as	O
substantial	O
performance	O
enhancements	O
,	O
new	O
instructions	O
and	O
importantly	O
POWER/PowerPC	O
'	O
s	O
first	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	B-Operating_System
)	O
implementation	O
)	O
the	O
design	O
leveraged	O
a	O
number	O
of	O
key	O
technologies	O
and	O
project	O
management	O
strategies	O
.	O
</s>
<s>
The	O
601	O
team	O
leveraged	O
much	O
of	O
the	O
basic	O
structure	O
and	O
portions	O
of	O
the	O
IBM	O
RISC	B-Device
Single	I-Device
Chip	I-Device
(	O
RSC	O
)	O
processor	O
,	O
but	O
also	O
included	O
support	O
for	O
the	O
vast	O
majority	O
of	O
the	O
new	O
PowerPC	B-Architecture
instructions	O
not	O
in	O
the	O
POWER	B-Architecture
instruction	I-Architecture
set	I-Architecture
.	O
</s>
<s>
While	O
nearly	O
every	O
portion	O
of	O
the	O
RSC	O
design	O
was	O
modified	O
,	O
and	O
many	O
design	O
blocks	O
were	O
substantially	O
modified	O
or	O
completely	O
redesigned	O
given	O
the	O
completely	O
different	O
unified	O
I/O	B-General_Concept
bus	I-General_Concept
structure	O
and	O
SMP/memory	O
coherency	O
support	O
.	O
</s>
<s>
New	O
PowerPC	B-Architecture
changes	O
,	O
leveraging	O
the	O
basic	O
RSC	O
structure	O
was	O
very	O
beneficial	O
to	O
reducing	O
the	O
uncertainty	O
in	O
chip	O
area/floorplanning	O
and	O
timing	O
analysis/tuning	O
.	O
</s>
<s>
Worth	O
noting	O
is	O
that	O
the	O
601	O
not	O
only	O
implemented	O
substantial	O
new	O
key	O
functions	O
such	O
as	O
SMP	B-Operating_System
,	O
but	O
it	O
also	O
acted	O
as	O
a	O
bridge	O
between	O
the	O
POWER	B-Architecture
and	O
the	O
future	O
PowerPC	B-Architecture
processors	I-Architecture
to	O
assist	O
IBM	O
and	O
software	O
developers	O
in	O
their	O
transitions	O
to	O
PowerPC	B-Architecture
.	O
</s>
<s>
From	O
start	O
of	O
design	O
to	O
tape-out	O
of	O
the	O
first	O
601	O
prototype	O
was	O
just	O
12	O
months	O
in	O
order	O
to	O
push	O
hard	O
to	O
establish	O
PowerPC	B-Architecture
on	O
the	O
market	O
early	O
.	O
</s>
<s>
In	O
order	O
to	O
help	O
the	O
effort	O
to	O
rapidly	O
incorporate	O
the	O
88110	B-Device
bus	B-General_Concept
architecture	O
to	O
the	O
601	O
for	O
the	O
benefit	O
of	O
the	O
alliance	O
and	O
its	O
customers	O
,	O
Motorola	O
management	O
provided	O
not	O
only	O
the	O
88110	B-Device
bus	B-General_Concept
architecture	O
specifications	O
,	O
but	O
also	O
a	O
handful	O
of	O
88110	B-Device
bus-literate	O
designers	O
to	O
help	O
with	O
the	O
60x	B-General_Concept
bus	B-General_Concept
logic	O
implementation	O
and	O
verification	O
.	O
</s>
<s>
Given	O
the	O
Apple	O
system	O
design	O
team	O
was	O
familiar	O
with	O
the	O
I/O	B-General_Concept
bus	I-General_Concept
structure	O
from	O
Motorola	O
's	O
88110	B-Device
and	O
this	O
I/O	B-General_Concept
bus	I-General_Concept
implementation	O
was	O
well	O
defined	O
and	O
documented	O
,	O
the	O
601	O
team	O
adopted	O
the	O
bus	B-General_Concept
technology	O
to	O
improve	O
time	O
to	O
market	O
.	O
</s>
<s>
The	O
bus	B-General_Concept
was	O
renamed	O
the	O
60x	B-General_Concept
bus	B-General_Concept
once	O
implemented	O
on	O
the	O
601	O
.	O
</s>
<s>
Using	O
the	O
88110	B-Device
bus	B-General_Concept
as	O
the	O
basis	O
for	O
the	O
60x	B-General_Concept
bus	B-General_Concept
helped	O
schedules	O
in	O
a	O
number	O
of	O
ways	O
.	O
</s>
<s>
It	O
helped	O
the	O
Apple	B-Device
Power	I-Device
Macintosh	I-Device
team	O
by	O
reducing	O
the	O
amount	O
of	O
redesign	O
of	O
their	O
support	O
ASICs	O
and	O
it	O
reduced	O
the	O
amount	O
of	O
time	O
required	O
for	O
the	O
processor	O
designers	O
and	O
architects	O
to	O
propose	O
,	O
document	O
,	O
negotiate	O
,	O
and	O
close	O
a	O
new	O
bus	B-General_Concept
interface	O
(	O
successfully	O
avoiding	O
the	O
"	O
Bus	B-General_Concept
Wars	O
"	O
expected	O
by	O
the	O
601	O
management	O
team	O
if	O
the	O
88110	B-Device
bus	B-General_Concept
or	O
the	O
previous	O
RSC	O
buses	O
had	O
n't	O
been	O
adopted	O
)	O
.	O
</s>
<s>
Worthy	O
to	O
note	O
is	O
that	O
accepting	O
the	O
88110	B-Device
bus	B-General_Concept
for	O
the	O
benefit	O
of	O
Apple	O
's	O
efforts	O
and	O
the	O
alliance	O
was	O
at	O
the	O
expense	O
of	O
the	O
first	O
IBM	B-Device
RS/6000	I-Device
system	O
design	O
team	O
's	O
efforts	O
who	O
had	O
their	O
support	O
ASICs	O
already	O
implemented	O
around	O
the	O
RSC	O
's	O
totally	O
different	O
bus	B-General_Concept
structure	O
.	O
</s>
<s>
This	O
60x	B-General_Concept
bus	B-General_Concept
later	O
became	O
a	O
fairly	O
long	O
lived	O
basic	O
interface	O
for	O
the	O
many	O
variants	O
of	O
the	O
601	O
,	O
603	O
,	O
604	O
,	O
G3	B-Device
,	O
G4	B-General_Concept
and	O
Motorola/Freescale	O
PowerQUICC	B-General_Concept
processors	B-Architecture
.	O
</s>
<s>
The	O
chip	O
was	O
designed	O
to	O
suit	O
a	O
wide	O
variety	O
of	O
applications	O
and	O
had	O
support	O
for	O
external	O
L2	B-General_Concept
cache	I-General_Concept
and	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
.	O
</s>
<s>
It	O
had	O
four	O
functional	O
units	O
,	O
including	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
an	O
integer	B-General_Concept
unit	I-General_Concept
,	O
a	O
branch	O
unit	O
and	O
a	O
sequencer	O
unit	O
.	O
</s>
<s>
The	O
processor	O
also	O
included	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
integer	O
pipeline	B-General_Concept
was	O
four	O
stages	O
long	O
,	O
the	O
branch	O
pipeline	B-General_Concept
two	O
stages	O
long	O
,	O
the	O
memory	O
pipeline	B-General_Concept
five	O
stages	O
long	O
,	O
and	O
the	O
floating-point	O
pipeline	B-General_Concept
six	O
stages	O
long	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
using	O
a	O
0.6μm	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
aluminum	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
601	O
has	O
a	O
32KB	O
unified	O
L1	B-General_Concept
cache	I-General_Concept
,	O
a	O
capacity	O
that	O
was	O
considered	O
large	O
at	O
the	O
time	O
for	O
an	O
on-chip	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Thanks	O
partly	O
to	O
the	O
large	O
cache	O
it	O
was	O
considered	O
a	O
high	O
performance	O
processor	O
in	O
its	O
segment	O
,	O
outperforming	O
the	O
competing	O
Intel	B-General_Concept
Pentium	I-General_Concept
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
601	O
was	O
used	O
in	O
the	O
first	O
Power	B-Device
Macintosh	I-Device
computers	O
from	O
Apple	O
,	O
and	O
in	O
a	O
variety	O
of	O
RS/6000	B-Device
workstations	B-Device
and	O
SMP	B-Operating_System
servers	O
from	O
IBM	O
and	O
Groupe	O
Bull	O
.	O
</s>
<s>
IBM	O
was	O
the	O
sole	O
manufacturer	O
of	O
the	O
601	O
and	O
601+	O
microprocessors	B-Architecture
in	O
its	O
Burlington	O
,	O
Vermont	O
and	O
East	O
Fishkill	O
,	O
New	O
York	O
production	O
facilities	O
.	O
</s>
<s>
The	O
601	O
used	O
the	O
IBM	O
CMOS-4s	O
process	O
and	O
the	O
601+	O
used	O
the	O
IBM	O
CMOS-5x	O
process	O
.	O
</s>
<s>
An	O
extremely	O
small	O
number	O
of	O
these	O
601	O
and	O
601+	O
processors	B-Architecture
were	O
relabeled	O
with	O
Motorola	O
logos	O
and	O
part	O
numbers	O
and	O
distributed	O
through	O
Motorola	O
.	O
</s>
<s>
An	O
updated	O
version	O
,	O
the	O
PowerPC	B-Architecture
601v	O
or	O
PowerPC	B-Architecture
601+	O
,	O
operating	O
at	O
90	O
to	O
120MHz	O
was	O
introduced	O
in	O
1994	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
newer	O
0.5μm	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
interconnect	B-General_Concept
,	O
resulting	O
in	O
a	O
die	O
measuring	O
74mm2	O
.	O
</s>
<s>
The	O
601+	O
design	O
was	O
remapped	O
from	O
CMOS-4s	O
to	O
CMOS-5x	O
by	O
an	O
IBM-only	O
team	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603	O
was	O
the	O
first	O
processor	O
implementing	O
the	O
complete	O
32-bit	O
PowerPC	B-Architecture
Architecture	I-Architecture
as	O
specified	O
.	O
</s>
<s>
Introduced	O
in	O
1994	O
,	O
it	O
was	O
an	O
advanced	O
design	O
for	O
its	O
day	O
,	O
being	O
one	O
of	O
the	O
first	O
microprocessors	B-Architecture
to	O
offer	O
dual	O
issue	O
(	O
up	O
to	O
three	O
with	O
branch	O
folding	O
)	O
and	O
out-of-order	B-General_Concept
execution	I-General_Concept
combined	O
with	O
low	O
power	B-Architecture
consumption	O
of	O
2.2	O
W	O
and	O
a	O
small	O
die	O
of	O
85	O
mm2	O
.	O
</s>
<s>
It	O
was	O
designed	O
to	O
be	O
a	O
low	O
cost	O
,	O
low	O
power	B-Architecture
processor	O
for	O
portable	O
applications	O
.	O
</s>
<s>
One	O
of	O
the	O
main	O
features	O
was	O
power	B-Architecture
saving	O
functions	O
(	O
doze	O
,	O
nap	O
and	O
sleep	O
mode	O
)	O
that	O
could	O
dramatically	O
reduce	O
power	B-Architecture
requirements	O
,	O
drawing	O
only	O
2mW	O
in	O
sleep	O
mode	O
.	O
</s>
<s>
The	O
603	O
has	O
a	O
four-stage	O
pipeline	B-General_Concept
and	O
five	O
execution	O
units	O
:	O
integer	B-General_Concept
unit	I-General_Concept
,	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
load/store	O
unit	O
and	O
a	O
system	O
registry	O
unit	O
.	O
</s>
<s>
It	O
has	O
separate	O
8KB	O
L1	O
caches	O
for	O
instructions	O
and	O
data	O
and	O
a	O
32/64	O
bit	O
60x	B-General_Concept
memory	O
bus	B-General_Concept
,	O
reaching	O
up	O
to	O
120MHz	O
at	O
3.8	O
V	O
.	O
The	O
603	O
core	O
did	O
not	O
have	O
hardware	O
support	O
for	O
SMP	B-Operating_System
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603	O
had	O
1.6	O
million	O
transistors	O
and	O
was	O
fabricated	O
by	O
IBM	O
and	O
Motorola	O
in	O
a	O
0.5μm	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
603	O
architecture	O
is	O
the	O
direct	O
ancestor	O
to	O
the	O
PowerPC	B-Device
750	I-Device
architecture	O
,	O
marketed	O
by	O
Apple	O
as	O
the	O
PowerPC	B-Architecture
"	O
G3	B-Device
"	O
.	O
</s>
<s>
The	O
603	O
was	O
intended	O
to	O
be	O
used	O
for	O
portable	O
Apple	O
Macintosh	O
computers	O
but	O
could	O
not	O
run	O
68K	B-Device
emulation	I-Device
software	I-Device
with	O
performance	O
Apple	O
considered	O
adequate	O
,	O
due	O
to	O
the	O
smaller	O
processor	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
This	O
caused	O
the	O
delay	O
of	O
the	O
Apple	O
PowerBook	B-Device
5300	I-Device
and	O
PowerBook	B-Device
Duo	I-Device
2300	I-Device
,	O
as	O
Apple	O
chose	O
to	O
wait	O
for	O
a	O
processor	O
revision	O
.	O
</s>
<s>
Aside	O
from	O
the	O
issue	O
of	O
68K	O
emulation	O
performance	O
,	O
the	O
Performa	O
machines	O
shipped	O
with	O
a	O
variety	O
of	O
design	O
flaws	O
,	O
some	O
of	O
them	O
severe	O
,	O
related	O
to	O
other	O
aspects	O
of	O
the	O
computers	O
 '	O
design	O
,	O
including	O
networking	O
performance	O
and	O
stability	O
,	O
bus	B-General_Concept
problems	O
(	O
width	O
,	O
speed	O
,	O
contention	O
,	O
and	O
complexity	O
)	O
,	O
ROM	O
bugs	O
,	O
and	O
hard	O
disk	O
performance	O
.	O
</s>
<s>
The	O
performance	O
issues	O
of	O
the	O
603	O
were	O
addressed	O
in	O
the	O
PowerPC	B-Architecture
603e	O
.	O
</s>
<s>
The	O
L1	B-General_Concept
cache	I-General_Concept
was	O
enlarged	O
and	O
enhanced	O
to	O
16KB	O
four-way	O
set-associative	O
data	O
and	O
instruction	O
caches	O
.	O
</s>
<s>
The	O
clock	O
speed	O
of	O
the	O
processors	B-Architecture
was	O
doubled	O
too	O
,	O
reaching	O
200MHz	O
.	O
</s>
<s>
This	O
part	O
is	O
sometimes	O
called	O
PowerPC	B-Architecture
603ev	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603e	O
was	O
the	O
first	O
mainstream	O
desktop	O
processor	O
to	O
reach	O
300MHz	O
,	O
as	O
used	O
in	O
the	O
Power	B-Device
Macintosh	I-Device
6500	I-Device
.	O
</s>
<s>
The	O
603e	O
was	O
also	O
used	O
in	O
accelerator	O
cards	O
from	O
Phase5	O
for	O
the	O
Amiga	B-Device
line	O
of	O
computers	O
,	O
with	O
CPUs	O
ranging	O
in	O
speeds	O
from	O
160	O
to	O
240MHz	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603e	O
is	O
still	O
sold	O
today	O
by	O
IBM	O
and	O
Freescale	O
,	O
and	O
others	O
like	O
Atmel	O
and	O
Honeywell	O
who	O
makes	O
the	O
radiation	O
hardened	O
variant	O
RHPPC	B-General_Concept
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603e	O
was	O
also	O
the	O
heart	O
of	O
the	O
BeBox	B-Device
from	O
Be	O
Inc	O
.	O
</s>
<s>
The	O
BeBox	B-Device
is	O
notable	O
since	O
it	O
is	O
a	O
multiprocessing	B-Operating_System
system	O
,	O
something	O
the	O
603	O
was	O
n't	O
designed	O
for	O
.	O
</s>
<s>
IBM	O
also	O
used	O
PowerPC	B-Architecture
603e	O
processors	B-Architecture
in	O
the	O
IBM	B-Device
ThinkPad	I-Device
800	I-Device
series	I-Device
.	O
</s>
<s>
In	O
certain	O
digital	O
oscilloscope	O
series	O
,	O
LeCroy	O
used	O
the	O
PowerPC	B-Architecture
603e	O
as	O
the	O
main	O
processor	O
.	O
</s>
<s>
The	O
603e	O
processors	B-Architecture
also	O
power	B-Architecture
all	O
66	O
satellites	O
in	O
the	O
Iridium	O
satellite	O
phone	O
fleet	O
.	O
</s>
<s>
The	O
satellites	O
each	O
contain	O
seven	O
Motorola/Freescale	O
PowerPC	B-Architecture
603e	O
processors	B-Architecture
running	O
at	O
roughly	O
200MHz	O
each	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
603e	O
core	O
,	O
renamed	O
G2	O
by	O
Freescale	O
,	O
is	O
the	O
basis	O
for	O
many	O
embedded	O
PowerQUICC	B-General_Concept
II	O
processors	B-Architecture
,	O
and	O
,	O
as	O
such	O
,	O
it	O
keeps	O
on	O
being	O
developed	O
.	O
</s>
<s>
Freescale	O
's	O
PowerQUICC	B-General_Concept
II	O
SoC	B-Architecture
processors	B-Architecture
bear	O
the	O
designation	O
MPC82xx	O
,	O
and	O
come	O
in	O
a	O
variety	O
of	O
configurations	O
reaching	O
450MHz	O
.	O
</s>
<s>
The	O
G2	O
name	O
is	O
also	O
used	O
as	O
a	O
retronym	O
for	O
the	O
603e	O
and	O
604	O
processors	B-Architecture
to	O
align	O
with	O
the	O
G3	B-Device
,	O
G4	B-General_Concept
,	O
and	O
the	O
G5	O
.	O
</s>
<s>
Freescale	O
has	O
enhanced	O
the	O
603e	O
core	O
,	O
calling	O
it	O
e300	O
,	O
in	O
the	O
PowerQUICC	B-General_Concept
II	O
Pro	O
embedded	O
processors	B-Architecture
.	O
</s>
<s>
Freescale	O
's	O
PowerQUICC	B-General_Concept
II	O
Pro	O
SoC	B-Architecture
processors	B-Architecture
bear	O
the	O
designation	O
MPC83xx	O
,	O
and	O
come	O
in	O
a	O
variety	O
of	O
configurations	O
reaching	O
speeds	O
up	O
to	O
667MHz	O
.	O
</s>
<s>
The	O
e300	O
is	O
also	O
the	O
core	O
of	O
the	O
MPC5200B	O
SoC	B-Architecture
processor	O
that	O
is	O
used	O
in	O
the	O
small	O
EFIKA	B-Device
computer	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
604	O
was	O
introduced	O
in	O
December	O
1994	O
alongside	O
the	O
603	O
and	O
was	O
designed	O
as	O
a	O
high-performance	O
chip	O
for	O
workstations	B-Device
and	O
entry-level	O
servers	O
and	O
as	O
such	O
had	O
support	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
in	O
hardware	O
.	O
</s>
<s>
The	O
604	O
was	O
used	O
extensively	O
in	O
Apple	O
's	O
high-end	O
systems	O
and	O
was	O
also	O
used	O
in	O
Macintosh	B-Device
clones	I-Device
,	O
IBM	O
's	O
low-end	O
RS/6000	B-Device
servers	O
and	O
workstations	B-Device
,	O
Amiga	B-Device
accelerator	O
boards	O
,	O
and	O
as	O
an	O
embedded	O
CPU	O
for	O
telecom	O
applications	O
.	O
</s>
<s>
The	O
604	O
is	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
capable	O
of	O
issuing	O
four	O
instructions	O
simultaneously	O
.	O
</s>
<s>
The	O
604	O
has	O
a	O
six-stage	O
pipeline	B-General_Concept
and	O
six	O
execution	O
units	O
that	O
can	O
work	O
in	O
parallel	O
,	O
finishing	O
up	O
to	O
six	O
instructions	O
every	O
cycle	O
.	O
</s>
<s>
Two	O
simple	O
and	O
one	O
complex	O
integer	B-General_Concept
units	I-General_Concept
,	O
one	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
one	O
branch-processing	O
unit	O
managing	O
out-of-order	B-General_Concept
execution	I-General_Concept
and	O
one	O
load/store	O
unit	O
.	O
</s>
<s>
The	O
external	O
interface	O
is	O
a	O
32	O
-	O
or	O
64-bit	B-Device
60x	B-General_Concept
bus	B-General_Concept
that	O
operates	O
at	O
clock	O
rates	O
up	O
to	O
50MHz	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
604	O
contains	O
3.6	O
million	O
transistors	O
and	O
was	O
fabricated	O
by	O
IBM	O
and	O
Motorola	O
with	O
a	O
0.5μm	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
604e	B-General_Concept
was	O
introduced	O
in	O
July	O
1996	O
and	O
added	O
a	O
condition	O
register	O
unit	O
and	O
separate	O
32KB	O
data	O
and	O
instruction	O
L1	O
caches	O
among	O
other	O
changes	O
to	O
its	O
memory	O
subsystem	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
resulting	O
in	O
a	O
25%	O
performance	O
increase	O
compared	O
to	O
its	O
predecessor	O
.	O
</s>
<s>
It	O
had	O
5.1	O
million	O
transistors	O
and	O
was	O
manufactured	O
by	O
IBM	O
and	O
Motorola	O
on	O
a	O
0.35μm	O
CMOS	B-Device
process	O
with	O
five	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
It	O
operated	O
at	O
speeds	O
between	O
166	O
and	O
233MHz	O
and	O
supported	O
a	O
memory	O
bus	B-General_Concept
up	O
to	O
66MHz	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
604ev	O
,	O
604r	O
or	O
"	O
Mach	O
5	O
"	O
was	O
introduced	O
in	O
August	O
1997	O
and	O
was	O
essentially	O
a	O
604e	B-General_Concept
fabricated	O
by	O
IBM	O
and	O
Motorola	O
with	O
a	O
newer	O
process	O
,	O
reaching	O
higher	O
speeds	O
with	O
a	O
lower	O
energy	O
consumption	O
.	O
</s>
<s>
The	O
die	O
was	O
47mm2	O
small	O
manufactured	O
on	O
a	O
0.25μm	O
CMOS	B-Device
process	O
with	O
five	O
levels	O
of	O
interconnect	B-General_Concept
,	O
and	O
drew	O
6W	O
at	O
250MHz	O
.	O
</s>
<s>
It	O
operated	O
at	O
speeds	O
between	O
250	O
and	O
400MHz	O
and	O
supported	O
a	O
memory	O
bus	B-General_Concept
up	O
to	O
100MHz	O
.	O
</s>
<s>
While	O
Apple	O
dropped	O
the	O
604ev	O
in	O
1998	O
in	O
favor	O
for	O
the	O
PowerPC	B-Device
750	I-Device
,	O
IBM	O
kept	O
using	O
it	O
in	O
entry-level	O
models	O
of	O
its	O
RS/6000	B-Device
computers	O
for	O
several	O
years	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
620	O
was	O
the	O
first	O
implementation	O
of	O
the	O
entire	O
64-bit	B-Device
PowerPC	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
It	O
was	O
a	O
second	O
generation	O
PowerPC	B-Architecture
alongside	O
the	O
603	O
and	O
604	O
,	O
but	O
geared	O
towards	O
the	O
high-end	O
workstation	B-Device
and	O
server	O
market	O
.	O
</s>
<s>
When	O
it	O
did	O
arrive	O
,	O
the	O
performance	O
was	O
comparably	O
poor	O
and	O
the	O
considerably	O
cheaper	O
604e	B-General_Concept
surpassed	O
it	O
.	O
</s>
<s>
The	O
sole	O
user	O
of	O
PowerPC	B-Architecture
620	O
was	O
Groupe	O
Bull	O
in	O
its	O
Escala	O
UNIX	B-Application
machines	O
,	O
but	O
they	O
did	O
n't	O
deliver	O
any	O
large	O
numbers	O
.	O
</s>
<s>
IBM	O
,	O
which	O
intended	O
to	O
use	O
it	O
in	O
workstations	B-Device
and	O
servers	O
,	O
decided	O
to	O
wait	O
for	O
the	O
even	O
more	O
powerful	O
RS64	B-Device
and	O
POWER3	B-General_Concept
64-bit	B-Device
processors	I-Device
instead	O
.	O
</s>
<s>
It	O
has	O
a	O
five-stage	O
pipeline	B-General_Concept
,	O
same	O
support	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
and	O
the	O
same	O
number	O
of	O
execution	O
units	O
;	O
a	O
load/store	O
unit	O
,	O
a	O
branch	O
unit	O
,	O
an	O
FPU	O
,	O
and	O
three	O
integer	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
With	O
larger	O
32KB	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
,	O
support	O
for	O
a	O
L2	B-General_Concept
cache	I-General_Concept
that	O
may	O
have	O
a	O
capacity	O
of	O
128MB	O
,	O
and	O
more	O
powerful	O
branch	O
and	O
load/store	O
units	O
that	O
had	O
more	O
buffers	O
,	O
the	O
620	O
was	O
very	O
powerful	O
.	O
</s>
<s>
The	O
branch	O
history	O
table	O
was	O
also	O
larger	O
and	O
could	O
dispatch	O
more	O
instructions	O
so	O
that	O
the	O
processor	O
can	O
handle	O
out-of-order	B-General_Concept
execution	I-General_Concept
more	O
efficiently	O
than	O
the	O
604	O
.	O
</s>
<s>
The	O
floating-point	B-General_Concept
unit	I-General_Concept
was	O
also	O
enhanced	O
compared	O
to	O
the	O
604	O
.	O
</s>
<s>
With	O
a	O
faster	O
fetch	O
cycle	O
and	O
support	O
for	O
several	O
key	O
instructions	O
in	O
hardware	O
(	O
like	O
sqrt	O
)	O
made	O
it	O
,	O
combined	O
with	O
faster	O
and	O
wider	O
data	B-General_Concept
buses	I-General_Concept
,	O
more	O
efficient	O
than	O
the	O
FPU	O
in	O
the	O
604	O
.	O
</s>
<s>
The	O
system	O
bus	B-General_Concept
was	O
a	O
wider	O
and	O
faster	O
128-bit	O
memory	O
bus	B-General_Concept
called	O
the	O
6XX	O
bus	B-General_Concept
.	O
</s>
<s>
It	O
was	O
designed	O
to	O
be	O
a	O
system	O
bus	B-General_Concept
for	O
multiprocessor	B-Operating_System
systems	O
where	O
processors	B-Architecture
,	O
caches	O
,	O
memory	O
and	O
I/O	B-General_Concept
was	O
to	O
be	O
connected	O
,	O
assisted	O
by	O
a	O
system	O
control	O
chip	O
.	O
</s>
<s>
It	O
supports	O
both	O
32	O
-	O
and	O
64-bit	B-Device
PowerPC	B-Architecture
processors	I-Architecture
,	O
memory	O
addresses	O
larger	O
than	O
32bits	O
,	O
and	O
NUMA	B-Operating_System
environments	O
.	O
</s>
<s>
It	O
was	O
also	O
used	O
in	O
POWER3	B-General_Concept
,	O
RS64	B-Device
and	O
601	O
,	O
as	O
well	O
as	O
604-based	O
RS/6000	B-Device
systems	O
(	O
with	O
a	O
bridge	O
chip	O
)	O
.	O
</s>
<s>
The	O
bus	B-General_Concept
later	O
evolved	O
into	O
the	O
GX	O
bus	B-General_Concept
of	O
the	O
POWER4	B-Device
,	O
and	O
later	O
GX+	O
and	O
GX++	O
in	O
POWER5	B-Device
and	O
POWER6	B-Device
respectively	O
.	O
</s>
<s>
The	O
GX	O
bus	B-General_Concept
is	O
also	O
used	O
in	O
IBM	O
's	O
z10	B-Device
and	O
z196	O
System	B-Device
z	I-Device
mainframes	O
.	O
</s>
<s>
(	O
Interesting	O
reading	O
concerning	O
the	O
use	O
of	O
PowerPC	B-Architecture
620	O
at	O
Bull	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
602	O
was	O
a	O
stripped-down	O
version	O
of	O
PowerPC	B-Architecture
603	O
,	O
specially	O
made	O
for	O
game	O
consoles	O
by	O
Motorola	O
and	O
IBM	O
,	O
introduced	O
in	O
February	O
1995	O
.	O
</s>
<s>
It	O
has	O
smaller	O
L1	O
caches	O
(	O
4KB	O
instruction	O
and	O
4KB	O
data	O
)	O
,	O
a	O
single-precision	O
floating-point	B-General_Concept
unit	I-General_Concept
and	O
a	O
scaled	O
back	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
It	O
consisted	O
of	O
1	O
million	O
transistors	O
and	O
it	O
was	O
50mm2	O
large	O
manufactured	O
in	O
a	O
0.5μm	O
,	O
CMOS	B-Device
process	O
with	O
four	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
3DO	O
developed	O
the	O
M2	B-Device
game	I-Device
console	I-Device
that	O
used	O
two	O
PowerPC	B-Architecture
602	O
,	O
but	O
it	O
was	O
never	O
marketed	O
.	O
</s>
<s>
On	O
October	O
21	O
,	O
1996	O
,	O
the	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
Quantum	O
Effect	O
Devices	O
(	O
QED	O
)	O
announced	O
a	O
PowerPC	B-Architecture
603-compatible	O
processor	O
named	O
"	O
PowerPC	B-General_Concept
603q	I-General_Concept
"	O
at	O
the	O
Microprocessor	B-Architecture
Forum	O
.	O
</s>
<s>
It	O
was	O
a	O
from	O
the	O
ground	O
up	O
implementation	O
of	O
the	O
32-bit	O
PowerPC	B-Architecture
architecture	I-Architecture
targeted	O
at	O
the	O
high-end	O
embedded	O
market	O
developed	O
over	O
two	O
years	O
.	O
</s>
<s>
As	O
such	O
,	O
it	O
was	O
small	O
,	O
simple	O
,	O
energy	O
efficient	O
,	O
but	O
powerful	O
;	O
equaling	O
the	O
more	O
expensive	O
603e	O
while	O
drawing	O
less	O
power	B-Architecture
.	O
</s>
<s>
It	O
had	O
an	O
in-order	O
,	O
five-stage	O
pipeline	B-General_Concept
with	O
a	O
single	O
integer	B-General_Concept
unit	I-General_Concept
,	O
a	O
double-precision	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
and	O
separate	O
16KB	O
instruction	O
and	O
8KB	O
data	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
While	O
the	O
integer	B-General_Concept
unit	I-General_Concept
was	O
a	O
brand	O
new	O
design	O
,	O
the	O
FPU	O
was	O
derived	O
from	O
the	O
R4600	B-Device
to	O
save	O
time	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
603q	O
was	O
canceled	O
as	O
QED	O
could	O
not	O
continue	O
to	O
market	O
the	O
processor	O
since	O
they	O
lacked	O
a	O
PowerPC	B-Architecture
license	O
of	O
their	O
own	O
.	O
</s>
<s>
"	O
PowerPC	B-Architecture
613	O
"	O
seems	O
to	O
be	O
a	O
name	O
Motorola	O
had	O
given	O
a	O
third	O
generation	O
PowerPC	B-Architecture
.	O
</s>
<s>
It	O
supposedly	O
was	O
renamed	O
"	O
PowerPC	B-Device
750	I-Device
"	O
in	O
response	O
to	O
Exponential	O
Technology	O
's	O
x704	O
processor	O
that	O
was	O
designed	O
to	O
outgun	O
the	O
604	O
by	O
a	O
wide	O
margin	O
.	O
</s>
<s>
Similar	O
to	O
PowerPC	B-Architecture
613	O
,	O
the	O
"	O
PowerPC	B-Architecture
614	O
"	O
might	O
have	O
been	O
a	O
name	O
given	O
by	O
Motorola	O
to	O
a	O
third	O
generation	O
PowerPC	B-Architecture
,	O
and	O
later	O
renamed	O
by	O
the	O
same	O
reason	O
as	O
613	O
.	O
</s>
<s>
It	O
's	O
been	O
suggested	O
that	O
the	O
part	O
was	O
renamed	O
"	O
PowerPC	B-General_Concept
7400	I-General_Concept
"	O
,	O
and	O
Motorola	O
even	O
bumped	O
it	O
to	O
the	O
fourth	O
generation	O
PowerPC	B-Architecture
even	O
though	O
the	O
architectural	O
differences	O
between	O
"	O
G3	B-Device
"	O
and	O
"	O
G4	B-General_Concept
"	O
was	O
small	O
.	O
</s>
<s>
The	O
"	O
PowerPC	B-Architecture
615	O
"	O
is	O
a	O
PowerPC	B-Architecture
processor	I-Architecture
announced	O
by	O
IBM	O
in	O
1994	O
,	O
but	O
which	O
never	O
reached	O
mass	O
production	O
.	O
</s>
<s>
Its	O
main	O
feature	O
was	O
to	O
incorporate	O
an	O
x86	B-Operating_System
core	O
on	O
die	O
,	O
thus	O
making	O
the	O
processor	O
able	O
to	O
natively	O
process	O
both	O
PowerPC	B-Architecture
and	O
x86	B-Operating_System
instructions	O
.	O
</s>
<s>
An	O
operating	O
system	O
running	O
on	O
PowerPC	B-Architecture
615	O
could	O
either	O
choose	O
to	O
execute	O
32-bit	O
or	O
64-bit	B-Device
PowerPC	B-Architecture
instructions	O
,	O
32-bit	O
x86	B-Operating_System
instructions	O
or	O
a	O
mix	O
of	O
three	O
.	O
</s>
<s>
The	O
only	O
operating	O
systems	O
that	O
supported	O
the	O
615	O
were	O
Minix	B-Operating_System
and	O
a	O
special	O
development	O
version	O
of	O
OS/2	B-Application
.	O
</s>
<s>
It	O
was	O
pin	O
compatible	O
with	O
Intel	O
's	O
Pentium	B-General_Concept
processors	B-Architecture
and	O
comparable	O
in	O
speed	O
.	O
</s>
<s>
Engineers	O
working	O
on	O
the	O
PowerPC	B-Architecture
615	O
would	O
later	O
find	O
their	O
way	O
to	O
Transmeta	O
,	O
where	O
they	O
worked	O
on	O
the	O
Crusoe	B-General_Concept
processor	O
.	O
</s>
<s>
With	O
progress	O
having	O
been	O
demonstrated	O
in	O
the	O
development	O
of	O
dynamic	O
translation	O
software	O
,	O
such	O
as	O
Digital	O
's	O
FX	B-Device
!	I-Device
32	I-Device
technology	O
,	O
skepticism	O
was	O
expressed	O
about	O
dedicating	O
hardware	O
resources	O
to	O
running	O
foreign	O
binaries	O
when	O
such	O
resources	O
could	O
be	O
used	O
to	O
improve	O
native	O
performance	O
instead	O
,	O
this	O
also	O
benefiting	O
the	O
performance	O
of	O
translated	O
binaries	O
.	O
</s>
<s>
"	O
PowerPC	B-Architecture
625	O
"	O
was	O
the	O
early	O
name	O
for	O
the	O
Apache	O
series	O
64-bit	B-Device
PowerPC	B-Architecture
processors	I-Architecture
,	O
designed	O
by	O
IBM	O
based	O
on	O
the	O
"	O
Amazon	O
"	O
PowerPC-AS	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
They	O
were	O
later	O
renamed	O
"	O
RS64	B-Device
"	O
.	O
</s>
<s>
The	O
designation	O
"	O
PowerPC	B-Architecture
625	O
"	O
was	O
never	O
used	O
for	O
the	O
final	O
processors	B-Architecture
.	O
</s>
<s>
"	O
PowerPC	B-Architecture
630	O
"	O
was	O
the	O
early	O
name	O
for	O
the	O
high	O
end	O
64-bit	B-Device
PowerPC	B-Architecture
processor	I-Architecture
,	O
designed	O
by	O
IBM	O
to	O
unify	O
the	O
POWER	B-Architecture
and	O
PowerPC	B-Architecture
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
It	O
was	O
later	O
renamed	O
"	O
POWER3	B-General_Concept
"	O
,	O
probably	O
to	O
distinguish	O
it	O
from	O
the	O
more	O
consumer	O
oriented	O
"	O
PowerPC	B-Architecture
"	O
processors	B-Architecture
used	O
by	O
Apple	O
.	O
</s>
<s>
"	O
PowerPC	B-Architecture
641	O
"	O
,	O
codename	O
Habanero	O
,	O
is	O
a	O
defunct	O
PowerPC	B-Architecture
project	O
by	O
IBM	O
in	O
the	O
1994	O
–	O
96	O
timeframe	O
.	O
</s>
<s>
It	O
has	O
been	O
suggested	O
that	O
was	O
the	O
third	O
generation	O
PowerPC	B-Architecture
based	O
on	O
the	O
604	O
processor	O
.	O
</s>
