<s>
The	O
PowerPC	B-General_Concept
400	I-General_Concept
family	O
is	O
a	O
line	O
of	O
32-bit	O
embedded	B-Architecture
RISC	B-Architecture
processor	I-Architecture
cores	O
based	O
on	O
the	O
PowerPC	B-Architecture
or	O
Power	B-Architecture
ISA	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
.	O
</s>
<s>
The	O
cores	O
are	O
designed	O
to	O
fit	O
inside	O
specialized	O
applications	O
ranging	O
from	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
microcontrollers	B-Architecture
,	O
network	O
appliances	O
,	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
and	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
to	O
set-top	O
boxes	O
,	O
storage	O
devices	O
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
IBM	O
continues	O
evolving	O
the	O
cores	O
while	O
supplying	O
design	O
and	O
foundry	B-Algorithm
services	O
around	O
the	O
cores	O
.	O
</s>
<s>
Introduced	O
in	O
1994	O
,	O
the	O
PowerPC	B-Architecture
403	O
was	O
one	O
of	O
the	O
first	O
PowerPC	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
It	O
was	O
the	O
first	O
one	O
targeted	O
strictly	O
to	O
the	O
embedded	B-Architecture
market	O
.	O
</s>
<s>
Compared	O
to	O
the	O
other	O
PowerPC	B-Architecture
processors	I-Architecture
of	O
the	O
era	O
(	O
PowerPC	B-Architecture
601	O
,	O
PowerPC	B-Architecture
603	O
and	O
PowerPC	B-Architecture
604	O
)	O
,	O
it	O
was	O
at	O
the	O
very	O
low	O
end	O
,	O
lacking	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
or	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	B-General_Concept
)	O
,	O
for	O
instance	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
403	O
is	O
used	O
in	O
,	O
among	O
other	O
appliances	O
,	O
thin	B-Device
clients	I-Device
,	O
set-top	O
boxes	O
,	O
RAID-controllers	O
,	O
network	B-Protocol
switches	I-Protocol
and	O
printers	O
.	O
</s>
<s>
The	O
first	O
TiVo	B-Application
used	O
a	O
54MHz	O
PowerPC	B-Architecture
403GCX	O
.	O
</s>
<s>
While	O
the	O
403	O
was	O
popular	O
,	O
it	O
was	O
also	O
too	O
high	O
performance	O
and	O
too	O
costly	O
for	O
some	O
applications	O
,	O
so	O
in	O
1996	O
IBM	O
released	O
a	O
bare	O
bones	O
PowerPC	B-Architecture
core	O
,	O
called	O
PowerPC	B-Architecture
401	O
.	O
</s>
<s>
It	O
has	O
a	O
single	O
issue	O
,	O
three-stage	O
pipeline	O
,	O
with	O
no	O
MMU	O
or	O
DMA	O
and	O
only	O
2	O
KB	O
instruction	O
and	O
1	O
KB	O
data	O
L1	O
caches	B-General_Concept
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
405	O
was	O
released	O
in	O
1998	O
and	O
was	O
designed	O
for	O
price	O
or	O
performance	O
sensitive	O
low-end	O
embedded	O
system-on-a-chip	O
(	O
SoC	O
)	O
designs	O
.	O
</s>
<s>
It	O
has	O
a	O
five-stage	O
pipeline	O
,	O
separate	O
16KB	O
instruction	O
and	O
data	O
L1	O
caches	B-General_Concept
,	O
a	O
CoreConnect	B-Architecture
bus	I-Architecture
,	O
an	O
Auxiliary	O
Processing	O
Unit	O
(	O
APU	O
)	O
interface	O
for	O
expandability	O
and	O
supports	O
clock	O
rates	O
exceeding	O
400MHz	O
.	O
</s>
<s>
The	O
405	O
core	O
adheres	O
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
using	O
the	O
Book	O
III-E	O
specification	O
.	O
</s>
<s>
IBM	O
has	O
announced	O
plans	O
to	O
make	O
the	O
specifications	O
of	O
the	O
PowerPC	B-Architecture
405	O
core	O
freely	O
available	O
to	O
the	O
academic	O
and	O
research	O
community	O
.	O
</s>
<s>
PowerPC-405-based	O
applications	O
include	O
digital	O
cameras	O
,	O
modems	O
,	O
set-top	O
boxes	O
(	O
IBM	O
's	O
STB04xxx	O
processors	O
)	O
,	O
cellphones	O
,	O
GPS-devices	O
,	O
printers	O
,	O
fax	O
machines	O
,	O
network	B-Protocol
cards	I-Protocol
,	O
network	B-Protocol
switches	I-Protocol
,	O
storage	O
devices	O
and	O
service	O
processors	O
for	O
servers	O
.	O
</s>
<s>
Up	O
to	O
two	O
405	O
cores	O
are	O
used	O
in	O
Xilinx	O
Virtex-II	O
Pro	O
and	O
Virtex-4	O
FPGAs	B-Architecture
.	O
</s>
<s>
In	O
2004	O
Hifn	O
bought	O
IBM	O
's	O
PowerNP	O
network	B-General_Concept
processors	I-General_Concept
that	O
uses	O
405	O
cores	O
.	O
</s>
<s>
Later	O
versions	O
of	O
the	O
PlayStation	O
2	O
slim	O
used	O
a	O
PowerPC	B-Architecture
405	O
chip	O
emulating	O
the	O
MIPS	O
R3000A	B-Device
that	O
was	O
used	O
as	O
the	O
I/O	O
processor	O
in	O
earlier	O
models	O
.	O
</s>
<s>
The	O
Chinese	O
company	O
Culturecom	O
uses	O
a	O
405	O
core	O
for	O
its	O
V-Dragon	O
processor	O
which	O
powers	O
Linux	B-Application
terminals	O
and	O
set-top-boxes	O
.	O
</s>
<s>
AppliedMicro	O
has	O
a	O
series	O
of	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
products	O
based	O
on	O
PowerPC	B-Architecture
405	O
core	O
,	O
under	O
a	O
new	O
name	O
:	O
APM801xx	O
.	O
</s>
<s>
These	O
are	O
the	O
most	O
energy	O
efficient	O
Power	B-Architecture
Architecture	I-Architecture
products	O
to	O
date	O
(	O
Fall	O
2010	O
)	O
,	O
and	O
supports	O
frequencies	O
up	O
to	O
800MHz	O
at	O
~	O
1	O
W	O
,	O
or	O
0.3	O
W	O
idling	O
.	O
</s>
<s>
The	O
POWER8	B-Device
processor	O
contains	O
an	O
embedded	B-Architecture
on-chip	O
power	O
and	O
thermal	O
management	O
microcontroller	B-Architecture
,	O
called	O
on-chip	O
controller	O
(	O
OCC	O
)	O
.	O
</s>
<s>
Based	O
on	O
a	O
PowerPC405	O
processor	O
with	O
512KB	O
of	O
dedicated	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	B-Architecture
)	O
,	O
OCC	O
monitors	O
the	O
entire	O
chip	O
.	O
</s>
<s>
Introduced	O
in	O
1999	O
,	O
the	O
PowerPC	B-Architecture
440	O
was	O
the	O
first	O
PowerPC	B-Architecture
core	O
from	O
IBM	O
to	O
include	O
the	O
Book	O
E	O
extension	O
to	O
the	O
PowerPC	B-Architecture
specification	O
.	O
</s>
<s>
It	O
also	O
included	O
the	O
CoreConnect	B-Architecture
bus	I-Architecture
technology	O
designed	O
to	O
be	O
the	O
interface	O
between	O
the	O
parts	O
inside	O
a	O
PowerPC	B-Architecture
based	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
device	O
.	O
</s>
<s>
It	O
is	O
a	O
high-performance	O
core	O
with	O
separate	O
32KB	O
instruction	O
and	O
data	O
L1	O
caches	B-General_Concept
,	O
a	O
seven-stage	O
out-of-order	O
dual-issue	O
pipeline	O
,	O
supporting	O
speeds	O
of	O
up	O
to	O
800MHz	O
and	O
L2	O
caches	B-General_Concept
up	O
to	O
256KB	O
.	O
</s>
<s>
The	O
core	O
lacks	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	B-General_Concept
)	O
but	O
it	O
has	O
an	O
associated	O
four-stage	O
FPU	B-General_Concept
that	O
can	O
be	O
included	O
using	O
the	O
APU	O
(	O
Auxiliary	O
Processing	O
Unit	O
)	O
interface	O
.	O
</s>
<s>
The	O
440	O
core	O
adheres	O
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
using	O
the	O
Book	O
III-E	O
specification	O
.	O
</s>
<s>
Xilinx	O
currently	O
incorporates	O
one	O
or	O
two	O
cores	O
(	O
depending	O
on	O
the	O
member	O
of	O
the	O
family	O
)	O
into	O
the	O
Virtex-5	O
FXT	O
FPGA	B-Architecture
.	O
</s>
<s>
Broad	O
Reach	O
Engineering	O
has	O
used	O
the	O
IBM	O
440	O
synthesized	O
core	O
to	O
build	O
a	O
radiation-hardened	O
embedded	B-Architecture
SoC	O
that	O
includes	O
various	O
peripherals	O
(	O
two	O
ethernet	O
MACs	O
,	O
PCI	O
,	O
memory	O
controllers	O
,	O
DMA	O
controllers	O
,	O
EDAC	O
and	O
SIO	O
)	O
,	O
32KB	O
of	O
L1	O
cache	O
,	O
and	O
256KB	O
of	O
L2	O
cache	O
.	O
</s>
<s>
QCDOC	B-Operating_System
is	O
a	O
custom	O
supercomputer	B-Architecture
built	O
to	O
solve	O
small	O
but	O
extremely	O
computationally	O
demanding	O
problems	O
in	O
quantum	O
physics	O
.	O
</s>
<s>
Dual	O
440	O
cores	O
are	O
used	O
in	O
the	O
processors	O
powering	O
IBM	O
's	O
Blue	B-Operating_System
Gene/L	I-Operating_System
supercomputer	B-Architecture
,	O
which	O
until	O
June	O
2008	O
ranked	O
number	O
one	O
on	O
the	O
list	O
of	O
the	O
top	B-Operating_System
500	I-Operating_System
supercomputers	I-Operating_System
around	O
the	O
world	O
,	O
with	O
a	O
peak	O
performance	O
of	O
nearly	O
500	O
teraFLOPS	O
in	O
2008	O
.	O
</s>
<s>
The	O
440	O
core	O
is	O
also	O
used	O
in	O
the	O
Cray	B-Device
XT3	I-Device
,	O
XT4	B-Device
and	O
XT5	B-Device
supercomputers	B-Architecture
,	O
where	O
its	O
SeaStar	O
,	O
SeaStar2	O
and	O
SeaStar2+	O
communication	O
processors	O
closely	O
couples	O
HyperTransport	B-Device
memory	O
interface	O
with	O
routing	O
to	O
other	O
nodes	O
in	O
supercomputer	B-Architecture
clusters	O
.	O
</s>
<s>
The	O
SeaStar	O
device	O
provides	O
a	O
6.4	O
GB/s	O
connection	O
to	O
the	O
Opteron	B-General_Concept
based	O
processors	O
across	O
HyperTransport	B-Device
(	O
together	O
making	O
a	O
processing	O
element	O
,	O
PE	O
)	O
,	O
as	O
well	O
as	O
six	O
7.6	O
GB/s	O
links	O
to	O
neighboring	O
PEs	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
460EX	O
and	O
460GT	O
from	O
AMCC	O
are	O
,	O
despite	O
their	O
name	O
,	O
processors	O
with	O
the	O
440	O
core	O
.	O
</s>
<s>
Intrinsity	O
designed	O
the	O
now	O
defunct	O
Titan	B-General_Concept
core	I-General_Concept
for	O
AppliedMicro	O
from	O
the	O
ground	O
up	O
using	O
the	O
PowerPC	B-Architecture
440	O
core	O
spec	O
.	O
</s>
<s>
AppliedMicro	O
used	O
the	O
Titan	B-General_Concept
core	I-General_Concept
in	O
their	O
APM832xx	O
family	O
high	O
performance	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
products	O
but	O
these	O
parts	O
never	O
came	O
to	O
market	O
.	O
</s>
<s>
In	O
its	O
Virtex-5	O
FXT	O
FPGA	B-Architecture
product	O
line	O
,	O
Xilinx	O
embeds	O
up	O
to	O
two	O
PPC440	O
cores	O
.	O
</s>
<s>
The	O
embedded	B-Architecture
PPC440	O
has	O
a	O
maximum	O
frequency	O
of	O
550MHz	O
,	O
and	O
connects	O
to	O
the	O
surrounding	O
FPGA-fabric	O
through	O
a	O
special	O
crossbar	O
switch	O
,	O
increasing	O
the	O
Virtex-5	O
FXT	O
family	O
's	O
system	O
performance	O
over	O
2.6	O
times	O
compared	O
to	O
the	O
Virtex-4	O
FX	O
family	O
's	O
embedded	B-Architecture
PPC405	O
.	O
</s>
<s>
LSI	O
uses	O
the	O
PowerPC	B-Architecture
440	O
core	O
in	O
a	O
number	O
of	O
its	O
SAS	O
controller	O
chips	O
,	O
including	O
the	O
widely	O
used	O
SAS2008	O
variant	O
.	O
</s>
<s>
It	O
has	O
provisions	O
to	O
prevent	O
tampering	O
and	O
reverse	O
engineering	O
and	O
is	O
manufactured	O
at	O
IBM	O
's	O
highly	O
secure	O
Trusted	O
Foundry	B-Algorithm
.	O
</s>
<s>
It	O
has	O
embedded	B-Architecture
DRAM	O
,	O
dual	O
440	O
cores	O
with	O
dual	O
precision	O
FPUs	O
and	O
auxiliary	O
computing	O
units	O
providing	O
acceleration	O
and	O
protection	O
for	O
communications	O
,	O
complex	O
algorithms	O
and	O
synchronization	O
between	O
cores	O
.	O
</s>
<s>
The	O
processing	O
core	O
of	O
the	O
Blue	B-Operating_System
Gene/P	I-Operating_System
supercomputer	B-Architecture
is	O
designed	O
and	O
manufactured	O
by	O
IBM	O
.	O
</s>
<s>
It	O
is	O
very	O
similar	O
to	O
the	O
PowerPC	B-Architecture
440	O
but	O
few	O
details	O
are	O
disclosed	O
.	O
</s>
<s>
The	O
Blue	B-Operating_System
Gene/P	I-Operating_System
processor	O
consists	O
of	O
four	O
PowerPC	B-Architecture
450	O
cores	O
running	O
at	O
850MHz	O
reaching	O
13.6	O
gigaflops	O
in	O
total	O
.	O
</s>
<s>
IBM	O
is	O
claiming	O
very	O
power	O
efficient	O
design	O
compared	O
to	O
other	O
supercomputer	B-Architecture
processors	O
.	O
</s>
<s>
Introduced	O
in	O
2006	O
,	O
the	O
460	O
cores	O
are	O
similar	O
to	O
the	O
440	O
but	O
reach	O
1.4GHz	O
,	O
are	O
developed	O
with	O
multi-core	B-Architecture
applications	O
in	O
mind	O
and	O
have	O
24	O
additional	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	B-Architecture
)	O
instructions	O
.	O
</s>
<s>
The	O
460	O
core	O
adheres	O
to	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
using	O
the	O
Book	O
III-E	O
specification	O
.	O
</s>
<s>
PowerPC	B-Architecture
460S	O
a	O
completely	O
synthesized	O
core	O
and	O
can	O
be	O
licensed	O
from	O
IBM	O
or	O
Synopsys	O
for	O
manufacturing	O
on	O
different	O
foundries	B-Algorithm
.	O
</s>
<s>
460S	O
can	O
be	O
configured	O
with	O
different	O
amounts	O
of	O
L1	O
and	O
L2	O
cache	O
as	O
well	O
as	O
with	O
or	O
without	O
SMP	B-Operating_System
and	O
FPU	B-General_Concept
.	O
</s>
<s>
PowerPC	B-Architecture
464-H90	O
a	O
90nm	O
,	O
hard	O
core	O
(	O
not	O
synthesizable	O
)	O
,	O
released	O
in	O
2006	O
,	O
will	O
offer	O
a	O
customizable	O
core	O
for	O
ASICs	O
that	O
can	O
be	O
manufactured	O
with	O
IBM	O
or	O
at	O
manufacturing	O
facilities	O
at	O
Chartered	O
or	O
Samsung	B-Application
.	O
</s>
<s>
PowerPC	B-Architecture
464FP-H90	O
released	O
in	O
2007	O
,	O
is	O
a	O
hard	O
core	O
that	O
adds	O
a	O
double	O
precision	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	B-General_Concept
)	O
.	O
</s>
<s>
PowerPC	B-Architecture
460SX	O
and	O
460GTx	O
are	O
based	O
on	O
the	O
464-H90	O
core	O
.	O
</s>
<s>
They	O
run	O
at	O
0.8	O
to	O
1.2GHz	O
,	O
have	O
512KB	O
of	O
L2	O
cache	O
that	O
doubles	O
as	O
SRAM	B-Architecture
storage	O
,	O
a	O
400MHz	O
clock	O
DDR2	O
memory	O
controller	O
,	O
four	O
Gigabit	O
Ethernet	O
controllers	O
,	O
PCIe	O
controllers	O
and	O
a	O
variety	O
of	O
application-specific	O
accelerators	O
and	O
controller	O
facilities	O
.	O
</s>
<s>
DDR2-controller	O
,	O
256	O
KB	O
SRAM	B-Architecture
configurable	O
as	O
L2	O
cache	O
.	O
</s>
<s>
APM86190	O
and	O
APM86290	O
PACKETpro	O
codenamed	O
"	O
Mamba	O
"	O
,	O
they	O
are	O
single	O
and	O
dual	B-Architecture
core	I-Architecture
SoC	O
processors	O
based	O
on	O
the	O
PowerPC	B-Architecture
465	O
core	O
,	O
running	O
at	O
0.6-1.5GHz	O
.	O
</s>
<s>
32	O
KB	O
instruction/32	O
KB	O
data	O
L1	O
caches	B-General_Concept
and	O
256	O
KB	O
L2	O
cache	O
,	O
DDR3	O
controller	O
,	O
PCIe	O
,	O
SATA2	O
,	O
USB2	O
,	O
Gbit	O
Ethernet	O
and	O
various	O
other	O
I/O	O
interfaces	O
and	O
accelerators	O
like	O
TCP/IP	O
offloading	O
and	O
a	O
cryptography	O
accelerator	O
with	O
non-volatile	O
storage	O
for	O
crypto	O
keys	O
and	O
secure	O
boot	O
and	O
tampering	O
detection	O
.	O
</s>
<s>
APM86791	O
PACKETpro	O
codenamed	O
"	O
Keelback	O
"	O
,	O
it	O
is	O
a	O
single	O
core	O
SoC	O
processor	O
based	O
on	O
the	O
PowerPC	B-Architecture
465	O
core	O
running	O
at	O
1GHz	O
with	O
32	O
KB	O
instruction/32	O
KB	O
data	O
L1	O
caches	B-General_Concept
and	O
256	O
KB	O
L2	O
cache	O
,	O
DDR3	O
controller	O
,	O
2x	O
PCIe	O
,	O
2x	O
SATA2	O
,	O
2x	O
USB2	O
,	O
4x	O
Gbit	O
Ethernet	O
.	O
</s>
<s>
The	O
470	O
embedded	B-Architecture
and	O
customizable	O
core	O
,	O
adhering	O
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
v2.05	O
Book	O
III-E	O
,	O
was	O
designed	O
by	O
IBM	O
together	O
with	O
LSI	O
and	O
implemented	O
in	O
the	O
PowerPC	B-Architecture
476FP	O
in	O
2009	O
.	O
</s>
<s>
The	O
476FP	O
core	O
has	O
32/32	O
kB	O
L1	O
cache	O
,	O
dual	O
integer	O
units	O
and	O
a	O
SIMD	B-Device
capable	O
double	O
precision	O
FPU	B-General_Concept
that	O
handles	O
DSP	B-Architecture
instructions	O
.	O
</s>
<s>
The	O
9	O
stage	O
out	O
of	O
order	O
,	O
5-issue	O
pipeline	O
handles	O
speeds	O
up	O
to	O
2GHz	O
,	O
supports	O
the	O
PLB6	O
bus	O
,	O
up	O
to	O
1	O
MB	O
L2	O
cache	O
and	O
up	O
to	O
16	O
cores	O
in	O
SMP	B-Operating_System
configurations	O
.	O
</s>
