<s>
Power10	B-Operating_System
is	O
a	O
superscalar	B-General_Concept
,	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
microprocessor	B-Architecture
family	O
,	O
based	O
on	O
the	O
open	B-License
source	I-License
Power	B-Architecture
ISA	I-Architecture
,	O
and	O
announced	O
in	O
August	O
2020	O
at	O
the	O
Hot	O
Chips	O
conference	O
;	O
systems	O
with	O
Power10	B-Operating_System
CPUs	O
.	O
</s>
<s>
Generally	O
available	O
from	O
September	O
2021	O
in	O
the	O
IBM	O
Power10	B-Operating_System
Enterprise	O
E1080	O
server	O
.	O
</s>
<s>
The	O
processor	O
is	O
designed	O
to	O
have	O
15	O
cores	B-Architecture
available	O
,	O
but	O
a	O
spare	O
core	O
will	O
be	O
included	O
during	O
manufacture	O
to	O
cost-effectively	O
allow	O
for	O
yield	O
issues	O
.	O
</s>
<s>
Power10-based	O
processors	O
will	O
be	O
manufactured	O
by	O
Samsung	B-Application
using	O
a	O
7	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
with	O
18	O
layers	O
of	O
metal	O
and	O
18	O
billion	O
transistors	O
on	O
a	O
602mm2	O
silicon	O
die	O
.	O
</s>
<s>
The	O
main	O
features	O
of	O
Power10	B-Operating_System
are	O
higher	O
performance	O
per	O
watt	O
and	O
better	O
memory	B-General_Concept
and	O
I/O	B-General_Concept
architectures	O
,	O
with	O
a	O
focus	O
on	O
artificial	B-Application
intelligence	I-Application
(	O
AI	B-Application
)	O
workloads	O
.	O
</s>
<s>
Each	O
Power10	B-Operating_System
core	O
has	O
doubled	O
up	O
on	O
most	O
functional	B-General_Concept
units	I-General_Concept
compared	O
to	O
its	O
predecessor	O
POWER9	B-Device
.	O
</s>
<s>
The	O
core	O
is	O
eight-way	O
multithreaded	B-Operating_System
(	O
SMT8	B-General_Concept
)	O
and	O
has	O
48KB	O
instruction	O
and	O
32KB	O
data	O
L1	B-General_Concept
caches	I-General_Concept
,	O
a	O
2MB	O
large	O
L2	O
cache	O
and	O
a	O
very	O
large	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
with	O
4096	O
entries	O
.	O
</s>
<s>
Each	O
core	O
has	O
eight	O
execution	O
slices	O
each	O
with	O
one	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
,	O
branch	B-General_Concept
predictor	I-General_Concept
,	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
unit	I-Architecture
and	O
SIMD-engine	O
,	O
able	O
to	O
be	O
fed	O
128-bit	O
(	O
64+64	O
)	O
instructions	O
from	O
the	O
new	O
prefix/fuse	O
instructions	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.3.1	O
.	O
</s>
<s>
Each	O
execution	O
slice	O
can	O
handle	O
20	O
instructions	O
each	O
,	O
backed	O
up	O
by	O
a	O
shared	O
512-entry	O
instruction	O
table	O
,	O
and	O
fed	O
to	O
128-entry-wide	O
(	O
64	O
single-threaded	O
)	O
load	B-General_Concept
queue	I-General_Concept
and	O
80-entry	O
(	O
40	O
single-threaded	O
)	O
wide	O
store	O
queue	O
.	O
</s>
<s>
Better	O
branch	B-General_Concept
prediction	I-General_Concept
features	O
have	O
doubled	O
the	O
accuracy	O
.	O
</s>
<s>
A	O
core	O
has	O
four	O
matrix	B-Architecture
math	I-Architecture
assist	O
(	O
MMA	O
)	O
engines	O
,	O
for	O
better	O
handling	O
of	O
SIMD	B-Device
code	O
,	O
especially	O
for	O
matrix	O
multiplication	O
instructions	O
where	O
AI	B-General_Concept
inference	I-General_Concept
workloads	O
have	O
a	O
20-fold	O
performance	O
increase	O
.	O
</s>
<s>
The	O
processor	O
has	O
two	O
"	O
hemispheres	O
"	O
with	O
eight	O
cores	B-Architecture
each	O
,	O
sharing	O
a	O
64MB	O
L3	O
cache	O
for	O
a	O
total	O
of	O
16	O
cores	B-Architecture
and	O
128MB	O
L3	O
caches	O
.	O
</s>
<s>
Due	O
to	O
yield	O
issues	O
,	O
at	O
least	O
one	O
core	O
is	O
always	O
disabled	O
,	O
reducing	O
L3	O
cache	O
by	O
8MB	O
to	O
a	O
usable	O
total	O
of	O
15	O
cores	B-Architecture
and	O
120MB	O
L3	O
cache	O
.	O
</s>
<s>
Each	O
chip	O
also	O
has	O
eight	O
crypto	O
accelerators	O
offloading	O
common	O
algorithms	O
such	O
as	O
AES	B-Algorithm
and	O
SHA-3	B-Algorithm
.	O
</s>
<s>
Increased	O
clock	O
gating	O
and	O
reworked	O
microarchitecture	B-General_Concept
at	O
every	O
stage	O
,	O
together	O
with	O
the	O
fuse/prefix	O
instructions	O
enabling	O
more	O
work	O
with	O
fewer	O
work	O
units	O
,	O
and	O
smarter	O
cache	O
with	O
lower	O
memory	B-General_Concept
latencies	I-General_Concept
and	O
effective	O
address	O
tagging	O
reducing	O
cache	O
misses	O
,	O
enables	O
the	O
Power10	B-Operating_System
core	O
to	O
consume	O
half	O
the	O
power	O
as	O
POWER9	B-Device
.	O
</s>
<s>
And	O
in	O
the	O
case	O
of	O
mounting	O
two	O
cores	B-Architecture
on	O
the	O
same	O
module	O
,	O
up	O
to	O
3	O
times	O
as	O
fast	O
in	O
the	O
same	O
power	O
budget	O
.	O
</s>
<s>
As	O
the	O
cores	B-Architecture
can	O
act	O
like	O
eight	O
logical	O
processors	O
the	O
15-core	O
processor	O
looks	O
like	O
120	O
cores	B-Architecture
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
On	O
a	O
dual-chip	B-Algorithm
module	I-Algorithm
,	O
that	O
becomes	O
240	O
simultaneous	O
threads	O
per	O
socket	B-General_Concept
.	O
</s>
<s>
The	O
chips	O
have	O
completely	O
reworked	O
memory	B-General_Concept
and	O
I/O	B-General_Concept
architectures	O
,	O
using	O
the	O
open	O
Coherent	O
Accelerator	O
Processor	O
Interface	O
(	O
OpenCAPI	O
)	O
and	O
Open	O
Memory	B-General_Concept
Interface	O
(	O
OMI	O
)	O
.	O
</s>
<s>
Using	O
serial	B-Protocol
memory	I-Protocol
communications	I-Protocol
to	O
off	O
chip	O
controllers	B-General_Concept
reduces	O
signaling	O
lanes	O
to	O
and	O
from	O
the	O
chip	O
,	O
increases	O
the	O
bandwidth	O
and	O
allows	O
the	O
processor	O
to	O
be	O
flexible	O
in	O
its	O
memory	B-General_Concept
technology	O
,	O
.	O
</s>
<s>
Power10	B-Operating_System
supports	O
a	O
wide	O
range	O
of	O
memory	B-General_Concept
types	O
,	O
including	O
DDR3	O
through	O
DDR5	O
,	O
GDDR	O
,	O
HBM	O
,	O
or	O
Persistent	O
Storage	O
Memory	B-General_Concept
.	O
</s>
<s>
Power10	B-Operating_System
enables	O
encrypting	O
of	O
data	O
with	O
no	O
performance	O
penalty	O
at	O
every	O
stage	O
from	O
RAM	O
,	O
across	O
accelerators	O
and	O
cluster	B-Architecture
nodes	I-Architecture
to	O
data	O
at	O
rest	O
.	O
</s>
<s>
Power10	B-Operating_System
comes	O
with	O
PowerAXON	O
facility	O
enabling	O
chip	O
to	O
chip	O
,	O
system	O
to	O
system	O
and	O
OpenCAPI	O
bus	O
for	O
accelerators	O
,	O
I/O	B-General_Concept
and	O
other	O
high	O
performance	O
cache	B-General_Concept
coherent	I-General_Concept
peripherals	O
.	O
</s>
<s>
It	O
manages	O
the	O
communications	O
between	O
nodes	O
in	O
a	O
16x	O
socket	B-General_Concept
single	B-Algorithm
chip	I-Algorithm
module	I-Algorithm
(	O
SCM	B-Algorithm
)	O
cluster	O
or	O
a	O
4x	O
socket	B-General_Concept
dual	O
chip	O
module	O
(	O
DCM	O
)	O
cluster	O
.	O
</s>
<s>
It	O
also	O
manages	O
the	O
memory	B-General_Concept
semantics	I-General_Concept
for	O
clustering	O
of	O
systems	O
enabling	O
load/store	B-Architecture
access	O
from	O
the	O
core	O
up	O
to	O
2PB	O
of	O
RAM	O
on	O
the	O
entire	O
Power10	B-Operating_System
cluster	O
.	O
</s>
<s>
IBM	O
calls	O
this	O
feature	O
Memory	B-General_Concept
Inception	O
.	O
</s>
<s>
Power10	B-Operating_System
includes	O
PCIe	O
5	O
.	O
</s>
<s>
The	O
SCM	B-Algorithm
has	O
32x	O
and	O
the	O
DCM	O
has	O
64x	O
PCIe	O
5	O
lanes	O
.	O
</s>
<s>
The	O
decision	O
to	O
remove	O
NVLink	O
support	O
from	O
Power10	B-Operating_System
was	O
made	O
due	O
to	O
PCIe	O
5.0	O
'	O
s	O
bandwidth	O
capabilities	O
rendering	O
NVLink	O
support	O
obsolete	O
for	O
the	O
use	O
cases	O
that	O
Power10	B-Operating_System
was	O
designed	O
for	O
.	O
</s>
<s>
Support	O
for	O
NVLink	O
on-chip	O
was	O
previously	O
a	O
unique	O
selling	O
point	O
for	O
POWER8	B-Device
and	O
POWER9	B-Device
.	O
</s>
<s>
The	O
Power10	B-Operating_System
chip	O
is	O
available	O
in	O
two	O
variants	O
,	O
defined	O
by	O
firmware	B-Application
in	O
the	O
packaging	B-Algorithm
.	O
</s>
<s>
Even	O
though	O
the	O
chips	O
are	O
physically	O
identical	O
and	O
the	O
difference	O
is	O
set	O
in	O
firmware	B-Application
,	O
it	O
cannot	O
be	O
changed	O
by	O
the	O
user	O
nor	O
IBM	O
after	O
manufacturing	O
.	O
</s>
<s>
The	O
Power10	B-Operating_System
comes	O
in	O
three	O
flip-chip	B-Algorithm
plastic	I-Algorithm
land	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
FC-PLGA	O
)	O
packages	B-Algorithm
:	O
one	O
single	B-Algorithm
chip	I-Algorithm
module	I-Algorithm
(	O
SCM	B-Algorithm
)	O
and	O
two	O
dual-chip	O
modules	O
(	O
DCM	O
and	O
eSCM	O
)	O
.	O
</s>
<s>
SCM	B-Algorithm
,	O
singe	O
chip	O
module	O
–	O
3.6-4.15	O
GHz	O
,	O
up	O
to	O
15	O
SMT8	B-General_Concept
cores	B-Architecture
.	O
</s>
<s>
The	O
module	O
has	O
a	O
unique	O
configuration	O
with	O
8	O
connectors	O
on	O
the	O
substrate	O
(	O
OTF	O
)	O
for	O
symmetric	O
multiprocessing	O
(	O
SMP	O
)	O
cables	O
directly	O
connecting	O
other	O
Power10	B-Operating_System
SCM	B-Algorithm
modules	O
.	O
</s>
<s>
DCM	O
,	O
dual	O
chip	O
module	O
–	O
3.4-4.0	O
GHz	O
,	O
up	O
to	O
24	O
SMT8	B-General_Concept
cores	B-Architecture
.	O
</s>
<s>
eSCM	O
,	O
entry	O
single	B-Algorithm
chip	I-Algorithm
module	I-Algorithm
–	O
3.0-3.9	O
GHz	O
,	O
up	O
to	O
8	O
SMT8	B-General_Concept
cores	B-Architecture
.	O
</s>
<s>
It	O
combines	O
two	O
Power10	B-Operating_System
chips	O
.	O
</s>
<s>
The	O
first	O
chip	O
is	O
fully	O
functional	O
with	O
4-8	O
active	O
cores	B-Architecture
.	O
</s>
<s>
The	O
IBM	O
Power	O
E1080	O
,	O
codename	O
Denali	O
,	O
is	O
the	O
top	O
end	O
Power10	B-Operating_System
computer	O
by	O
IBM	O
.	O
</s>
<s>
Each	O
node	O
has	O
4×	O
Power10	B-Operating_System
SCM	B-Algorithm
,	O
configurable	O
with	O
10	O
,	O
12	O
,	O
or	O
15	O
SMT8	B-General_Concept
cores	B-Architecture
per	O
processor	O
,	O
and	O
up	O
to	O
16	O
TB	O
OMI-DDR4	O
RAM	O
.	O
</s>
<s>
The	O
Power	O
E1080	O
natively	O
runs	O
PowerVM	B-Application
running	O
AIX	B-Application
,	O
IBM	B-Application
i	I-Application
and	O
little-endian	O
Linux	B-Application
.	O
</s>
<s>
The	O
Power	O
E1080	O
also	O
supports	O
up	O
to	O
sixteen	O
I/O	B-General_Concept
expansion	O
drawers	O
,	O
four	O
per	O
CEC	O
node	O
.	O
</s>
<s>
A	O
maximum	O
specification	O
configuration	O
allows	O
the	O
Power	O
E1080	O
to	O
support	O
192	O
single	O
slot	O
PCIe	O
cards	O
across	O
a	O
16	O
socket	B-General_Concept
system	O
.	O
</s>
<s>
2-4	O
×	O
CPU	B-General_Concept
sockets	I-General_Concept
for	O
2-4	O
×	O
DCM	O
modules	O
,	O
24-96	O
cores	B-Architecture
.	O
</s>
<s>
64×	O
OMI	O
memory	B-General_Concept
slots	O
which	O
support	O
up	O
to	O
16	O
TB	O
RAM	O
.	O
</s>
<s>
Run	O
a	O
mix	O
of	O
Linux	B-Application
,	O
AIX	B-Application
or	O
IBM	B-Application
i	I-Application
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
The	O
S-models	O
can	O
run	O
Linux	B-Application
,	O
IBM	B-Application
i	I-Application
and	O
AIX	B-Application
.	O
</s>
<s>
The	O
L-models	O
are	O
made	O
for	O
Linux	B-Application
,	O
but	O
are	O
allowed	O
to	O
run	O
AIX	B-Application
and	O
IBM	B-Application
i	I-Application
on	O
up	O
to	O
25%	O
of	O
available	O
CPU	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
1-2	O
×	O
CPU	B-General_Concept
sockets	I-General_Concept
for	O
1-2	O
×	O
DCM	O
modules	O
,	O
24-48	O
cores	B-Architecture
.	O
</s>
<s>
32×	O
OMI	O
memory	B-General_Concept
slots	O
which	O
support	O
up	O
to	O
8	O
TB	O
RAM	O
.	O
</s>
<s>
1-2	O
×	O
CPU	B-General_Concept
sockets	I-General_Concept
for	O
1-2	O
×	O
DCM	O
modules	O
,	O
24-40	O
cores	B-Architecture
.	O
</s>
<s>
32×	O
OMI	O
memory	B-General_Concept
slots	O
which	O
support	O
up	O
to	O
4	O
TB	O
RAM	O
.	O
</s>
<s>
1-2	O
×	O
CPU	B-General_Concept
sockets	I-General_Concept
for	O
1-2	O
×	O
eSCM	O
modules	O
,	O
4-16	O
cores	B-Architecture
.	O
</s>
<s>
16×	O
OMI	O
memory	B-General_Concept
slots	O
which	O
support	O
up	O
to	O
2	O
TB	O
RAM	O
.	O
</s>
<s>
1×	O
Power10	B-Operating_System
eSCM	O
module	O
with	O
4	O
or	O
8	O
cores	B-Architecture
.	O
</s>
<s>
8×	O
OMI	O
memory	B-General_Concept
slots	O
which	O
support	O
up	O
to	O
1	O
TB	O
RAM	O
.	O
</s>
<s>
The	O
PowerAXON	O
facility	O
now	O
extends	O
all	O
the	O
way	O
to	O
2PB	O
of	O
unified	O
clustered	O
memory	B-General_Concept
space	O
,	O
shared	O
across	O
multiple	O
cluster	B-Architecture
nodes	I-Architecture
,	O
and	O
includes	O
support	O
for	O
PCIe	O
5	O
.	O
</s>
<s>
New	O
SIMD	B-Device
instructions	O
and	O
new	O
data	O
types	O
including	O
bfloat16	O
,	O
INT4(INTEGER )	O
and	O
INT8(BIGINT )	O
.	O
</s>
<s>
are	O
aimed	O
at	O
improving	O
AI	B-Application
workloads	O
.	O
</s>
<s>
Unlike	O
earlier	O
POWER9	B-Device
and	O
POWER8	B-Device
CPUs	O
,	O
Power10	B-Operating_System
requires	O
closed	O
source	O
,	O
third	O
party	O
firmware	B-Application
in	O
security	O
sensitive	O
areas	O
of	O
the	O
CPU	O
module	O
,	O
along	O
with	O
additional	O
closed	O
source	O
,	O
third	O
party	O
firmware	B-Application
in	O
the	O
required	O
off-module	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
Power10	B-Operating_System
is	O
unusual	O
in	O
that	O
its	O
name	O
is	O
not	O
capitalised	O
like	O
POWER9	B-Device
and	O
all	O
other	O
previous	O
POWER	O
processors	O
are	O
.	O
</s>
<s>
This	O
change	O
is	O
one	O
part	O
in	O
IBM	O
's	O
rebranding	O
of	O
their	O
Power	O
Systems	O
offering	O
,	O
which	O
beginning	O
with	O
Power10	B-Operating_System
is	O
now	O
just	O
"	O
Power	O
"	O
.	O
</s>
<s>
Power10	B-Operating_System
also	O
has	O
a	O
logo	O
.	O
</s>
