<s>
A	O
posted	B-Architecture
write	I-Architecture
is	O
a	O
computer	O
bus	O
write	O
transaction	O
that	O
does	O
not	O
wait	O
for	O
a	O
write	O
completion	O
response	O
to	O
indicate	O
success	O
or	O
failure	O
of	O
the	O
write	O
transaction	O
.	O
</s>
<s>
For	O
a	O
posted	B-Architecture
write	I-Architecture
,	O
the	O
CPU	O
assumes	O
that	O
the	O
write	O
cycle	O
will	O
complete	O
with	O
zero	O
wait	O
states	O
,	O
and	O
so	O
does	O
n't	O
wait	O
for	O
the	O
done	O
.	O
</s>
<s>
For	O
starters	O
,	O
it	O
does	O
n't	O
have	O
to	O
wait	O
for	O
the	O
done	O
response	O
,	O
but	O
it	O
also	O
allows	O
for	O
better	O
pipelining	B-General_Concept
of	O
the	O
datapath	B-General_Concept
without	O
much	O
performance	O
penalty	O
.	O
</s>
<s>
A	O
non-posted	O
write	O
requires	O
that	O
a	O
bus	O
transaction	O
responds	O
with	O
a	O
write	O
completion	O
response	O
to	O
indicate	O
success	O
or	O
failure	O
of	O
the	O
transaction	O
,	O
and	O
is	O
naturally	O
much	O
slower	O
than	O
a	O
posted	B-Architecture
write	I-Architecture
since	O
it	O
requires	O
a	O
round	O
trip	O
delay	O
similar	O
to	O
read	O
bus	O
transactions	O
.	O
</s>
<s>
In	O
reference	O
to	O
memory	O
bus	O
accesses	O
,	O
a	O
posted	B-Architecture
write	I-Architecture
is	O
referred	O
to	O
as	O
a	O
posted	O
memory	O
write	O
(	O
PMW	O
)	O
.	O
</s>
