<s>
The	O
Pixel	B-Device
Visual	I-Device
Core	I-Device
(	O
PVC	O
)	O
is	O
a	O
series	O
of	O
ARM-based	B-Architecture
system	B-Algorithm
in	I-Algorithm
package	I-Algorithm
(	O
SiP	B-Algorithm
)	O
image	B-General_Concept
processors	I-General_Concept
designed	O
by	O
Google	B-Application
.	I-Application
</s>
<s>
The	O
PVC	O
is	O
a	O
fully	O
programmable	O
image	B-General_Concept
,	O
vision	B-General_Concept
and	O
AI	B-General_Concept
multi-core	O
domain-specific	O
architecture	O
(	O
DSA	O
)	O
for	O
mobile	B-Application
devices	I-Application
and	O
in	O
future	O
for	O
IoT	B-Operating_System
.	O
</s>
<s>
It	O
first	O
appeared	O
in	O
the	B-Application
Google	I-Application
Pixel	B-Device
2	I-Device
and	O
2	O
XL	O
which	O
were	O
introduced	O
on	O
October	O
19	O
,	O
2017	O
.	O
</s>
<s>
It	O
has	O
also	O
appeared	O
in	O
the	B-Application
Google	I-Application
Pixel	B-Device
3	I-Device
and	O
3	O
XL	O
.	O
</s>
<s>
Google	B-Application
previously	O
used	O
Qualcomm	B-Architecture
Snapdragon	I-Architecture
's	O
CPU	B-Device
,	O
GPU	B-Architecture
,	O
IPU	B-General_Concept
,	O
and	O
DSP	B-Architecture
to	O
handle	O
its	O
image	B-Algorithm
processing	I-Algorithm
for	O
their	O
Google	B-Device
Nexus	I-Device
and	O
Google	B-Device
Pixel	I-Device
devices	O
.	O
</s>
<s>
With	O
the	O
increasing	O
importance	O
of	O
computational	B-Algorithm
photography	I-Algorithm
techniques	O
,	O
Google	B-Application
developed	O
the	O
Pixel	B-Device
Visual	I-Device
Core	I-Device
(	O
PVC	O
)	O
.	O
</s>
<s>
Google	B-Application
claims	O
the	O
PVC	O
uses	O
less	O
power	O
than	O
using	O
CPU	B-Device
and	O
GPU	B-Architecture
while	O
still	O
being	O
fully	O
programmable	O
,	O
unlike	O
their	O
tensor	B-Device
processing	I-Device
unit	I-Device
(	O
TPU	O
)	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
.	O
</s>
<s>
Indeed	O
,	O
classical	O
mobile	B-Application
devices	I-Application
equip	O
an	O
image	B-General_Concept
signal	I-General_Concept
processor	I-General_Concept
(	O
ISP	O
)	O
that	O
is	O
a	O
fixed	O
functionality	O
image	B-Algorithm
processing	I-Algorithm
pipeline	O
.	O
</s>
<s>
In	O
contrast	O
to	O
this	O
,	O
the	O
PVC	O
has	O
a	O
flexible	O
programmable	O
functionality	O
,	O
not	O
limited	O
only	O
to	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
The	O
PVC	O
in	O
the	B-Application
Google	I-Application
Pixel	B-Device
2	I-Device
and	O
2	O
XL	O
is	O
labeled	O
SR3HX	O
X726C502	O
.	O
</s>
<s>
The	O
PVC	O
in	O
the	B-Application
Google	I-Application
Pixel	B-Device
3	I-Device
and	O
3	O
XL	O
is	O
labeled	O
SR3HX	O
X739F030	O
.	O
</s>
<s>
Thanks	O
to	O
the	O
PVC	O
,	O
the	O
Pixel	B-Device
2	I-Device
and	O
Pixel	B-Device
3	I-Device
obtained	O
a	O
mobile	O
DxOMark	B-Algorithm
of	O
98	O
and	O
101	O
.	O
</s>
<s>
The	O
latter	O
one	O
was	O
the	O
top-ranked	O
single-lens	O
mobile	O
DxOMark	B-Algorithm
score	O
,	O
tied	O
with	O
the	O
iPhone	O
XR	O
.	O
</s>
<s>
A	O
typical	O
image-processing	O
program	O
of	O
the	O
PVC	O
is	O
written	O
in	O
Halide	B-Operating_System
.	O
</s>
<s>
Currently	O
,	O
it	O
supports	O
just	O
a	O
subset	O
of	O
Halide	B-Operating_System
programming	O
language	O
without	O
floating	O
point	O
operations	O
and	O
with	O
limited	O
memory	O
access	O
patterns	O
.	O
</s>
<s>
Halide	B-Operating_System
is	O
a	O
domain-specific	B-Language
language	I-Language
that	O
lets	O
the	O
user	O
decouple	O
the	O
algorithm	O
and	O
the	O
scheduling	O
of	O
its	O
execution	O
.	O
</s>
<s>
The	O
PVC	O
has	O
two	O
types	O
of	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
,	O
a	O
virtual	O
and	O
a	O
physical	O
one	O
.	O
</s>
<s>
First	O
,	O
a	O
high-level	O
language	O
program	O
is	O
compiled	O
into	O
a	O
virtual	O
ISA	O
(	O
vISA	O
)	O
,	O
inspired	O
by	O
RISC-V	B-Device
ISA	O
,	O
which	O
abstracts	O
completely	O
from	O
the	O
target	O
hardware	O
generation	O
.	O
</s>
<s>
Then	O
,	O
the	O
vISA	O
program	O
is	O
compiled	O
into	O
the	O
so-called	O
physical	O
ISA	O
(	O
pISA	O
)	O
,	O
that	O
is	O
a	O
VLIW	B-General_Concept
ISA	O
.	O
</s>
<s>
The	O
Pixel	B-Device
Visual	I-Device
Core	I-Device
is	O
designed	O
to	O
be	O
a	O
scalable	O
multi-core	O
energy-efficient	O
architecture	O
,	O
ranging	O
from	O
even	O
numbers	O
between	O
2	O
and	O
16	O
core	O
designs	O
.	O
</s>
<s>
The	O
core	O
of	O
a	O
PVC	O
is	O
the	O
image	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
IPU	B-General_Concept
)	O
a	O
programmable	O
unit	O
tailored	O
for	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
The	O
Pixel	B-Device
Visual	I-Device
Core	I-Device
architecture	O
was	O
also	O
designed	O
either	O
to	O
be	O
its	O
own	O
chip	O
,	O
like	O
the	O
SR3HX	O
,	O
or	O
as	O
an	O
IP	B-Architecture
block	I-Architecture
for	O
System	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SOC	O
)	O
.	O
</s>
<s>
The	O
IPU	B-General_Concept
core	O
has	O
a	O
stencil	O
processor	O
(	O
STP	O
)	O
,	O
a	O
line	O
buffer	O
pool	O
(	O
LBP	O
)	O
and	O
a	O
NoC	B-Architecture
.	O
</s>
<s>
The	O
STP	O
mainly	O
provides	O
a	O
2-D	O
SIMD	B-Device
array	O
of	O
processing	O
elements	O
(	O
PEs	O
)	O
able	O
to	O
perform	O
stencil	B-Application
computations	I-Application
,	O
a	O
small	O
neighborhood	O
of	O
pixels	O
.	O
</s>
<s>
Though	O
it	O
seems	O
similar	O
to	O
systolic	B-Architecture
array	I-Architecture
and	O
wavefront	O
computations	O
,	O
the	O
STP	O
has	O
an	O
explicit	O
software	O
controlled	O
data	O
movement	O
.	O
</s>
<s>
Each	O
PEs	O
features	O
2x	O
16-bit	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
,	O
1x	O
16-bit	O
Multiplier	B-Algorithm
–	I-Algorithm
accumulator	I-Algorithm
unit	O
(	O
MAC	O
)	O
,	O
10x	O
16-bit	O
registers	B-General_Concept
,	O
and	O
10x	O
1-bit	O
predicate	O
registers	B-General_Concept
.	O
</s>
<s>
Considering	O
that	O
one	O
of	O
the	O
most	O
energy	O
costly	O
operation	O
is	O
DRAM	O
access	O
,	O
each	O
STP	O
has	O
temporary	O
buffers	O
to	O
increase	O
data	B-General_Concept
locality	I-General_Concept
,	O
namely	O
LBP	O
.	O
</s>
<s>
The	O
used	O
LBP	O
is	O
a	O
2-D	O
FIFO	B-Operating_System
that	O
accommodates	O
different	O
sizes	O
of	O
reading	O
and	O
writing	O
.	O
</s>
<s>
Each	O
LBP	O
can	O
have	O
eight	O
logical	O
LB	O
memories	O
and	O
one	O
for	O
DMA	B-General_Concept
input-output	O
operations	O
.	O
</s>
<s>
The	O
NoC	B-Architecture
used	O
is	O
a	O
ring	O
network	B-Architecture
on	I-Architecture
chip	I-Architecture
used	O
to	O
communicate	O
with	O
only	O
neighbor	O
cores	O
for	O
energy	O
savings	O
and	O
pipelined	O
computational	O
pattern	O
preservation	O
.	O
</s>
<s>
The	O
SR3HX	O
PVC	O
features	O
a	O
64-bit	O
ARMv8a	O
ARM	O
Cortex-A53	O
CPU	B-Device
,	O
8x	O
image	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
IPU	B-General_Concept
)	O
cores	O
,	O
512	O
MB	O
LPDDR4	O
,	O
MIPI	O
,	O
PCIe	O
.	O
</s>
<s>
The	O
IPU	B-General_Concept
cores	O
each	O
have	O
512	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
consisting	O
of	O
256	O
processing	O
elements	O
(	O
PEs	O
)	O
arranged	O
as	O
a	O
16	O
x	O
16	O
2-dimensional	O
array	O
.	O
</s>
<s>
Those	O
cores	O
execute	O
a	O
custom	O
VLIW	B-General_Concept
ISA	O
.	O
</s>
<s>
The	O
SR3HX	O
PVC	O
is	O
manufactured	O
as	O
a	O
SiP	B-Algorithm
by	O
TSMC	O
using	O
their	O
28HPM	O
HKMG	B-Algorithm
process	O
.	O
</s>
<s>
(	O
Codename	O
:	O
Monette	O
Hill	O
)	O
Google	B-Application
claims	O
the	O
SR3HX	O
PVC	O
is	O
7-16x	O
more	O
energy-efficient	O
than	O
the	O
Snapdragon	B-Architecture
835	O
.	O
</s>
<s>
And	O
that	O
the	O
SR3HX	O
PVC	O
can	O
perform	O
3	O
trillion	O
operations	O
per	O
second	O
,	O
HDR+	O
can	O
run	O
5x	O
faster	O
and	O
at	O
less	O
than	O
one-tenth	O
the	O
energy	O
than	O
the	O
Snapdragon	B-Architecture
835	O
.	O
</s>
<s>
It	O
supports	O
Halide	B-Operating_System
for	O
image	B-Algorithm
processing	I-Algorithm
and	O
TensorFlow	B-Language
for	O
machine	O
learning	O
.	O
</s>
<s>
The	O
current	O
chip	O
runs	O
at	O
426MHz	O
and	O
the	O
single	O
IPU	B-General_Concept
is	O
able	O
to	O
perform	O
more	O
than	O
1	O
TeraOPS	O
.	O
</s>
