<s>
In	O
the	O
design	O
of	O
pipelined	B-General_Concept
computer	I-General_Concept
processors	I-General_Concept
,	O
a	O
pipeline	B-General_Concept
stall	I-General_Concept
is	O
a	O
delay	O
in	O
execution	O
of	O
an	O
instruction	B-General_Concept
in	O
order	O
to	O
resolve	O
a	O
hazard	B-General_Concept
.	O
</s>
<s>
In	O
a	O
standard	O
five-stage	O
pipeline	O
,	O
during	O
the	O
decoding	O
stage	O
,	O
the	O
control	O
unit	O
will	O
determine	O
whether	O
the	O
decoded	O
instruction	B-General_Concept
reads	O
from	O
a	O
register	O
to	O
which	O
the	O
currently	O
executed	O
instruction	B-General_Concept
writes	O
.	O
</s>
<s>
If	O
this	O
condition	O
holds	O
,	O
the	O
control	O
unit	O
will	O
stall	O
the	O
instruction	B-General_Concept
by	O
one	O
clock	O
cycle	O
.	O
</s>
<s>
It	O
also	O
stalls	O
the	O
instruction	B-General_Concept
in	O
the	O
fetch	O
stage	O
,	O
to	O
prevent	O
the	O
instruction	B-General_Concept
in	O
that	O
stage	O
from	O
being	O
overwritten	O
by	O
the	O
next	B-General_Concept
instruction	I-General_Concept
in	O
the	O
program	O
.	O
</s>
<s>
In	O
a	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
which	O
uses	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
register	O
to	O
determine	O
the	O
current	B-General_Concept
instruction	I-General_Concept
being	O
fetched	O
in	O
the	O
pipeline	O
,	O
to	O
prevent	O
new	O
instructions	O
from	O
being	O
fetched	O
when	O
an	O
instruction	B-General_Concept
in	O
the	O
decoding	O
stage	O
has	O
been	O
stalled	O
,	O
the	O
value	O
in	O
the	O
PC	B-General_Concept
register	I-General_Concept
and	O
the	O
instruction	B-General_Concept
in	O
the	O
fetch	O
stage	O
are	O
preserved	O
to	O
prevent	O
changes	O
.	O
</s>
<s>
The	O
values	O
are	O
preserved	O
until	O
the	O
instruction	B-General_Concept
causing	O
the	O
conflict	O
has	O
passed	O
through	O
the	O
execution	O
stage	O
.	O
</s>
<s>
Such	O
an	O
event	O
is	O
often	O
called	O
a	O
bubble	B-General_Concept
,	O
by	O
analogy	O
with	O
an	O
air	O
bubble	B-General_Concept
in	O
a	O
fluid	O
pipe	O
.	O
</s>
<s>
In	O
that	O
case	O
,	O
the	O
bubble	B-General_Concept
is	O
implemented	O
by	O
feeding	O
NOP	B-Language
(	O
"	O
no	B-Language
operation	I-Language
"	O
)	O
instructions	O
to	O
the	O
execution	O
stage	O
,	O
until	O
the	O
bubble	B-General_Concept
is	O
flushed	O
past	O
it	O
.	O
</s>
<s>
The	O
following	O
is	O
two	O
executions	O
of	O
the	O
same	O
four	O
instructions	O
through	O
a	O
4-stage	O
pipeline	O
but	O
,	O
for	O
whatever	O
reason	O
,	O
a	O
delay	O
in	O
fetching	O
of	O
the	O
purple	O
instruction	B-General_Concept
in	O
cycle	O
#2	O
leads	O
to	O
a	O
bubble	B-General_Concept
being	O
created	O
delaying	O
all	O
instructions	O
after	O
it	O
as	O
well	O
.	O
</s>
<s>
The	O
below	O
example	O
shows	O
a	O
bubble	B-General_Concept
being	O
inserted	O
into	O
a	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
,	O
with	O
five	O
stages	O
(	O
IF	O
=	O
Instruction	B-General_Concept
Fetch	O
,	O
ID	O
=	O
Instruction	B-General_Concept
Decode	O
,	O
EX	O
=	O
Execute	O
,	O
MEM	O
=	O
Memory	O
access	O
,	O
WB	O
=	O
Register	O
write	O
back	O
)	O
.	O
</s>
<s>
In	O
this	O
example	O
,	O
data	O
available	O
after	O
the	O
MEM	O
stage	O
(	O
4th	O
stage	O
)	O
of	O
the	O
first	O
instruction	B-General_Concept
is	O
required	O
as	O
input	O
by	O
the	O
EX	O
stage	O
(	O
3rd	O
stage	O
)	O
of	O
the	O
second	O
instruction	B-General_Concept
.	O
</s>
<s>
Without	O
a	O
bubble	B-General_Concept
,	O
the	O
EX	O
stage	O
(	O
3rd	O
stage	O
)	O
only	O
has	O
access	O
to	O
the	O
output	O
of	O
the	O
previous	O
EX	O
stage	O
.	O
</s>
<s>
Thus	O
adding	O
a	O
bubble	B-General_Concept
resolves	O
the	O
time	O
dependence	O
without	O
needing	O
to	O
propagate	O
data	O
backwards	O
in	O
time	O
(	O
which	O
is	O
impossible	O
)	O
.	O
</s>
