<s>
A	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
is	O
a	O
type	O
of	O
integrated	B-Algorithm
circuit	I-Algorithm
packaging	I-Algorithm
.	O
</s>
<s>
PGAs	O
are	O
often	O
mounted	O
on	O
printed	O
circuit	O
boards	O
using	O
the	O
through	B-Algorithm
hole	I-Algorithm
method	O
or	O
inserted	O
into	O
a	O
socket	B-General_Concept
.	O
</s>
<s>
PGAs	O
allow	O
for	O
more	O
pins	O
per	O
integrated	O
circuit	O
than	O
older	O
packages	O
,	O
such	O
as	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
.	O
</s>
<s>
Connections	O
can	O
be	O
made	O
either	O
by	O
wire	B-Algorithm
bonding	I-Algorithm
or	O
through	O
flip	B-Device
chip	I-Device
mounting	O
.	O
</s>
<s>
Typically	O
,	O
PGA	O
packages	O
use	O
wire	B-Algorithm
bonding	I-Algorithm
when	O
the	O
chip	O
is	O
mounted	O
on	O
the	O
pinned	O
side	O
,	O
and	O
flip	B-Device
chip	I-Device
construction	O
when	O
the	O
chip	O
is	O
on	O
the	O
top	O
side	O
.	O
</s>
<s>
Some	O
PGA	O
packages	O
contain	O
multiple	O
dies	O
,	O
for	O
example	O
Zen	O
2	O
and	O
Zen	O
3	O
Ryzen	O
CPUs	B-General_Concept
for	O
the	O
AM4	O
socket	B-General_Concept
.	O
</s>
<s>
A	O
flip-chip	B-Device
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
FC-PGA	B-Algorithm
or	O
FCPGA	B-Algorithm
)	O
is	O
a	O
form	O
of	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
in	O
which	O
the	O
die	O
faces	O
downwards	O
on	O
the	O
top	O
of	O
the	O
substrate	O
with	O
the	O
back	O
of	O
the	O
die	O
exposed	O
.	O
</s>
<s>
The	O
FC-PGA	B-Algorithm
was	O
introduced	O
by	O
Intel	O
with	O
the	O
Coppermine	O
core	O
Pentium	B-General_Concept
III	I-General_Concept
and	O
Celeron	B-Device
processors	O
based	O
on	O
Socket	B-Device
370	I-Device
,	O
and	O
was	O
later	O
used	O
for	O
Socket	O
478-based	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Celeron	B-Device
processors	O
.	O
</s>
<s>
FC-PGA	B-Algorithm
processors	O
fit	O
into	O
zero	B-General_Concept
insertion	I-General_Concept
force	I-General_Concept
(	O
ZIF	O
)	O
Socket	B-Device
370	I-Device
and	O
Socket	O
478-based	O
motherboard	B-General_Concept
sockets	I-General_Concept
;	O
similar	O
packages	O
have	O
also	O
been	O
used	O
by	O
AMD	O
.	O
</s>
<s>
A	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CPGA	O
)	O
is	O
a	O
type	O
of	O
packaging	B-Algorithm
used	O
by	O
integrated	O
circuits	O
.	O
</s>
<s>
This	O
type	O
of	O
packaging	B-Algorithm
uses	O
a	O
ceramic	O
substrate	O
with	O
pins	O
arranged	O
in	O
a	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
.	O
</s>
<s>
Some	O
CPUs	B-General_Concept
that	O
use	O
CPGA	O
packaging	B-Algorithm
are	O
the	O
AMD	O
Socket	B-General_Concept
A	O
Athlons	B-Architecture
and	O
the	O
Duron	O
.	O
</s>
<s>
A	O
CPGA	O
was	O
used	O
by	O
AMD	O
for	O
Athlon	B-Architecture
and	O
Duron	O
processors	O
based	O
on	O
Socket	B-General_Concept
A	O
,	O
as	O
well	O
as	O
some	O
AMD	O
processors	O
based	O
on	O
Socket	B-General_Concept
AM2	O
and	O
Socket	B-General_Concept
AM2+	O
.	O
</s>
<s>
This	O
type	O
of	O
packaging	B-Algorithm
uses	O
a	O
ceramic	O
substrate	O
with	O
pins	O
arranged	O
in	O
an	O
array	O
.	O
</s>
<s>
An	O
organic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
OPGA	B-Algorithm
)	O
is	O
a	O
type	O
of	O
connection	O
for	O
integrated	O
circuits	O
,	O
and	O
especially	O
CPUs	B-General_Concept
,	O
where	O
the	O
silicon	O
die	O
is	O
attached	O
to	O
a	O
plate	O
made	O
out	O
of	O
an	O
organic	O
plastic	O
which	O
is	O
pierced	O
by	O
an	O
array	O
of	O
pins	O
which	O
make	O
the	O
requisite	O
connections	O
to	O
the	O
socket	B-General_Concept
.	O
</s>
<s>
Plastic	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PPGA	B-Algorithm
)	O
packaging	B-Algorithm
was	O
used	O
by	O
Intel	O
for	O
late-model	O
Mendocino	O
core	O
Celeron	B-Device
processors	O
based	O
on	O
Socket	B-Device
370	I-Device
.	O
</s>
<s>
Some	O
pre-Socket	O
8	O
processors	O
also	O
used	O
a	O
similar	O
form	O
factor	O
,	O
although	O
they	O
were	O
not	O
officially	O
referred	O
to	O
as	O
PPGA	B-Algorithm
.	O
</s>
<s>
The	O
staggered	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
SPGA	B-Algorithm
)	O
is	O
used	O
by	O
Intel	O
processors	O
based	O
on	O
Socket	B-General_Concept
5	I-General_Concept
and	O
Socket	B-General_Concept
7	I-General_Concept
.	O
</s>
<s>
Socket	B-Device
8	I-Device
used	O
a	O
partial	O
SPGA	B-Algorithm
layout	O
on	O
half	O
the	O
processor	O
.	O
</s>
<s>
SPGA	B-Algorithm
packages	O
are	O
usually	O
used	O
by	O
devices	O
that	O
require	O
a	O
higher	O
pin	O
density	O
than	O
what	O
a	O
PGA	O
can	O
provide	O
,	O
such	O
as	O
microprocessors	B-Architecture
.	O
</s>
<s>
A	O
stud	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
SGA	O
)	O
is	O
a	O
short-pinned	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
chip	O
scale	O
package	O
for	O
use	O
in	O
surface-mount	O
technology	O
.	O
</s>
<s>
The	O
polymer	B-Algorithm
stud	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
or	O
plastic	B-Algorithm
stud	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
was	O
developed	O
jointly	O
by	O
the	O
Interuniversity	O
Microelectronics	O
Centre	O
(	O
IMEC	O
)	O
and	O
Laboratory	O
for	O
Production	O
Technology	O
,	O
Siemens	O
AG	O
.	O
</s>
<s>
The	O
reduced	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
was	O
used	O
by	O
the	O
socketed	O
mobile	O
variants	O
of	O
Intel	O
's	O
Core	O
i3/5/7	O
processors	O
and	O
features	O
a	O
reduced	O
pin	O
pitch	O
of	O
1mm	O
,	O
as	O
opposed	O
to	O
the	O
1.27mm	O
pin	O
pitch	O
used	O
by	O
contemporary	O
AMD	O
processors	O
and	O
older	O
Intel	O
processors	O
.	O
</s>
<s>
It	O
is	O
used	O
in	O
the	O
G1	B-Device
,	O
G2	B-Device
,	O
and	O
G3	B-Device
sockets	O
.	O
</s>
