<s>
In	O
computing	O
,	O
a	O
physical	B-General_Concept
address	I-General_Concept
(	O
also	O
real	B-General_Concept
address	I-General_Concept
,	O
or	O
binary	B-General_Concept
address	I-General_Concept
)	O
,	O
is	O
a	O
memory	B-General_Concept
address	I-General_Concept
that	O
is	O
represented	O
in	O
the	O
form	O
of	O
a	O
binary	O
number	O
on	O
the	O
address	B-Architecture
bus	I-Architecture
circuitry	O
in	O
order	O
to	O
enable	O
the	O
data	B-General_Concept
bus	I-General_Concept
to	O
access	O
a	O
particular	O
storage	O
cell	O
of	O
main	O
memory	O
,	O
or	O
a	O
register	O
of	O
memory-mapped	B-Architecture
I/O	I-Architecture
device	O
.	O
</s>
<s>
In	O
a	O
computer	O
supporting	O
virtual	B-Architecture
memory	I-Architecture
,	O
the	O
term	O
physical	B-General_Concept
address	I-General_Concept
is	O
used	O
mostly	O
to	O
differentiate	O
from	O
a	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
In	O
particular	O
,	O
in	O
computers	O
utilizing	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
to	O
translate	O
memory	O
addresses	O
,	O
the	O
virtual	O
and	O
physical	O
addresses	O
refer	O
to	O
an	O
address	O
before	O
and	O
after	O
translation	O
performed	O
by	O
the	O
MMU	O
,	O
respectively	O
.	O
</s>
<s>
Depending	O
upon	O
its	O
underlying	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
the	O
performance	O
of	O
a	O
computer	O
may	O
be	O
hindered	O
by	O
unaligned	O
access	O
to	O
memory	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
16-bit	B-Device
computer	I-Device
with	O
a	O
16-bit	B-Device
memory	O
data	B-General_Concept
bus	I-General_Concept
,	O
such	O
as	O
Intel	B-General_Concept
8086	I-General_Concept
,	O
generally	O
has	O
less	O
overhead	O
if	O
the	O
access	O
is	O
aligned	O
to	O
an	O
even	O
address	O
.	O
</s>
<s>
In	O
that	O
case	O
fetching	O
one	O
16-bit	B-Device
value	O
requires	O
a	O
single	O
memory	O
read	O
operation	O
,	O
a	O
single	O
transfer	O
over	O
a	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
If	O
the	O
16-bit	B-Device
data	O
value	O
starts	O
at	O
an	O
odd	O
address	O
,	O
the	O
processor	O
may	O
need	O
to	O
perform	O
two	O
memory	O
read	O
cycles	O
to	O
load	O
the	O
value	O
into	O
it	O
,	O
i.e.	O
</s>
<s>
On	O
some	O
processors	O
,	O
such	O
as	O
the	O
Motorola	B-Device
68000	I-Device
and	O
Motorola	B-Device
68010	I-Device
processors	O
,	O
and	O
SPARC	B-Architecture
processors	O
,	O
unaligned	O
memory	O
accesses	O
will	O
result	O
in	O
an	O
exception	O
being	O
raised	O
(	O
usually	O
resulting	O
in	O
a	O
software	O
exception	O
,	O
such	O
as	O
POSIX	O
's	O
SIGBUS	B-General_Concept
,	O
being	O
raised	O
)	O
.	O
</s>
<s>
The	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
feature	O
allows	O
other	O
devices	O
in	O
the	O
mother	B-Device
board	I-Device
besides	O
the	O
CPU	O
to	O
address	O
the	O
main	O
memory	O
.	O
</s>
