<s>
Permute	O
(	O
and	O
Shuffle	O
)	O
instructions	O
,	O
part	O
of	O
bit	B-Algorithm
manipulation	I-Algorithm
as	O
well	O
as	O
vector	B-Operating_System
processing	I-Operating_System
,	O
copy	O
unaltered	O
contents	O
from	O
a	O
source	O
array	O
to	O
a	O
destination	O
array	O
,	O
where	O
the	O
indices	O
are	O
specified	O
by	O
a	O
second	O
source	O
array	O
.	O
</s>
<s>
Note	O
that	O
unlike	O
in	O
memory-based	O
gather-scatter	B-General_Concept
all	O
three	O
of	O
dest	O
,	O
src	O
,	O
and	O
indices	O
are	O
registers	O
(	O
or	O
parts	O
of	O
registers	O
in	O
the	O
case	O
of	O
bit-level	O
permute	O
)	O
,	O
not	O
memory	O
locations	O
.	O
</s>
<s>
Given	O
that	O
the	O
indices	O
may	O
be	O
repeated	O
in	O
both	O
variants	O
,	O
the	O
resultant	O
output	O
is	O
not	O
a	O
strict	O
mathematical	O
permutation	B-Algorithm
because	O
duplicates	O
can	O
occur	O
in	O
the	O
output	O
.	O
</s>
<s>
A	O
special	O
case	O
of	O
permute	O
is	O
also	O
used	O
in	O
GPU	B-Architecture
"	O
swizzling	B-General_Concept
"	O
(	O
again	O
,	O
not	O
strictly	O
a	O
permutation	B-Algorithm
)	O
which	O
performs	O
on-the-fly	O
reordering	O
of	O
subvector	O
data	O
so	O
as	O
to	O
align	O
or	O
duplicate	O
elements	O
with	O
the	O
appropriate	O
SIMD	B-General_Concept
lane	I-General_Concept
.	O
</s>
<s>
Permute	B-Algorithm
instructions	I-Algorithm
occur	O
in	O
both	O
scalar	B-General_Concept
processors	I-General_Concept
as	O
well	O
as	O
vector	B-Operating_System
processing	I-Operating_System
engines	O
as	O
well	O
as	O
GPUs	B-Architecture
.	O
</s>
<s>
In	O
vector	O
instruction	O
sets	O
they	O
are	O
typically	O
named	O
"	O
Register	O
Gather/Scatter	B-General_Concept
"	O
operations	O
such	O
as	O
in	O
RISC-V	B-Device
vectors	O
,	O
and	O
take	O
Vectors	O
as	O
input	O
for	O
both	O
source	O
elements	O
and	O
source	O
array	O
,	O
and	O
output	O
another	O
Vector	O
.	O
</s>
<s>
In	O
scalar	O
instruction	O
sets	O
the	O
scalar	O
registers	O
are	O
broken	O
down	O
into	O
smaller	O
sections	O
(	O
unpacked	O
,	O
SIMD	B-Device
style	O
)	O
where	O
the	O
fragments	O
are	O
then	O
used	O
as	O
array	O
sources	O
.	O
</s>
<s>
bdep	O
(	O
bit	O
deposit	O
)	O
in	O
RISC-V	B-Device
bitmanip	O
;	O
in	O
the	O
Power	B-Architecture
ISA	I-Architecture
it	O
is	O
known	O
as	O
and	O
has	O
been	O
included	O
for	O
several	O
decades	O
,	O
and	O
is	O
still	O
in	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.3.0	O
B	O
spec	O
.	O
</s>
<s>
Also	O
in	O
some	O
non-vector	O
ISAs	O
,	O
due	O
to	O
there	O
sometimes	O
being	O
insufficient	O
space	O
in	O
the	O
one	O
source	O
input	O
register	O
to	O
specify	O
the	O
permutation	B-Algorithm
source	O
array	O
in	O
full	O
(	O
particularly	O
if	O
the	O
operation	O
involves	O
bit-level	O
permutation	B-Algorithm
)	O
,	O
will	O
include	O
partial	O
reordering	O
instructions	O
.	O
</s>
<s>
Examples	O
include	O
VSHUFF32x4	O
from	O
AVX-512	B-General_Concept
.	O
</s>
<s>
Permute	O
operations	O
in	O
different	O
forms	O
are	O
surprisingly	O
common	O
,	O
occurring	O
in	O
AltiVec	B-General_Concept
,	O
Power	B-Architecture
ISA	I-Architecture
,	O
PowerPC	B-General_Concept
G4	I-General_Concept
,	O
AVX-512	B-General_Concept
,	O
SVE2	O
,	O
vector	B-Operating_System
processors	I-Operating_System
,	O
and	O
GPUs	B-Architecture
.	O
</s>
<s>
They	O
are	O
sufficiently	O
important	O
that	O
LLVM	B-Application
added	O
the	O
intrinsic	O
and	O
GCC	B-Application
added	O
the	O
intrinsic	O
.	O
</s>
<s>
GCC	B-Application
's	O
intrinsic	O
matches	O
the	O
functionality	O
of	O
OpenCL	B-Application
's	O
shuffle	O
intrinsics	O
.	O
</s>
<s>
Note	O
that	O
all	O
of	O
these	O
,	O
mathematically	O
,	O
are	O
not	O
permutations	B-Algorithm
because	O
duplicates	O
can	O
occur	O
in	O
the	O
output	O
.	O
</s>
