<s>
Peripheral	B-Protocol
Component	I-Protocol
Interconnect	I-Protocol
(	O
PCI	B-Protocol
)	O
is	O
a	O
local	B-Architecture
computer	B-General_Concept
bus	I-General_Concept
for	O
attaching	O
hardware	B-Architecture
devices	O
in	O
a	O
computer	O
and	O
is	O
part	O
of	O
the	O
PCI	B-Protocol
Local	I-Protocol
Bus	I-Protocol
standard	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
supports	O
the	O
functions	O
found	O
on	O
a	O
processor	B-Architecture
bus	I-Architecture
but	O
in	O
a	O
standardized	O
format	O
that	O
is	O
independent	O
of	O
any	O
given	O
processor	O
's	O
native	O
bus	B-General_Concept
.	O
</s>
<s>
Devices	O
connected	O
to	O
the	O
PCI	B-Protocol
bus	I-Protocol
appear	O
to	O
a	O
bus	B-Architecture
master	I-Architecture
to	O
be	O
connected	O
directly	O
to	O
its	O
own	O
bus	B-General_Concept
and	O
are	O
assigned	O
addresses	O
in	O
the	O
processor	O
's	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
It	O
is	O
a	O
parallel	O
bus	B-General_Concept
,	O
synchronous	B-Application
to	O
a	O
single	O
bus	B-General_Concept
clock	O
.	O
</s>
<s>
Attached	O
devices	O
can	O
take	O
either	O
the	O
form	O
of	O
an	O
integrated	O
circuit	O
fitted	O
onto	O
the	O
motherboard	B-Device
(	O
called	O
a	O
planar	O
device	O
in	O
the	O
PCI	B-Protocol
specification	O
)	O
or	O
an	O
expansion	B-Device
card	I-Device
that	O
fits	O
into	O
a	O
slot	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
Local	I-Protocol
Bus	I-Protocol
was	O
first	O
implemented	O
in	O
IBM	O
PC	O
compatibles	O
,	O
where	O
it	O
displaced	O
the	O
combination	O
of	O
several	O
slow	O
Industry	B-Architecture
Standard	I-Architecture
Architecture	I-Architecture
(	O
ISA	B-Architecture
)	O
slots	O
and	O
one	O
fast	O
VESA	O
Local	B-Architecture
Bus	I-Architecture
(	O
VLB	O
)	O
slot	O
as	O
the	O
bus	B-General_Concept
configuration	O
.	O
</s>
<s>
Typical	O
PCI	B-Protocol
cards	I-Protocol
used	O
in	O
PCs	O
include	O
:	O
network	B-Protocol
cards	I-Protocol
,	O
sound	B-Device
cards	I-Device
,	O
modems	B-Application
,	O
extra	O
ports	O
such	O
as	O
Universal	O
Serial	B-Protocol
Bus	B-General_Concept
(	O
USB	B-Protocol
)	O
or	O
serial	B-Protocol
,	O
TV	B-Device
tuner	I-Device
cards	I-Device
and	O
hard	B-Device
disk	I-Device
drive	I-Device
host	B-Architecture
adapters	I-Architecture
.	O
</s>
<s>
PCI	B-Protocol
video	B-Device
cards	I-Device
replaced	O
ISA	B-Architecture
and	O
VLB	O
cards	O
until	O
rising	O
bandwidth	O
needs	O
outgrew	O
the	O
abilities	O
of	O
PCI	B-Protocol
.	O
</s>
<s>
The	O
preferred	O
interface	O
for	O
video	B-Device
cards	I-Device
then	O
became	O
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
AGP	O
)	O
,	O
a	O
superset	O
of	O
PCI	B-Protocol
,	O
before	O
giving	O
way	O
to	O
PCI	B-Protocol
Express	O
.	O
</s>
<s>
The	O
first	O
version	O
of	O
PCI	B-Protocol
found	O
in	O
retail	O
desktop	O
computers	O
was	O
a	O
32-bit	O
bus	B-General_Concept
using	O
a	O
33MHz	O
bus	B-General_Concept
clock	O
and	O
5V	O
signalling	O
,	O
although	O
the	O
PCI	B-Protocol
1.0	I-Protocol
standard	O
provided	O
for	O
a	O
64-bit	B-Device
variant	O
as	O
well	O
.	O
</s>
<s>
Version	O
2.0	O
of	O
the	O
PCI	B-Protocol
standard	O
introduced	O
3.3V	O
slots	O
,	O
physically	O
distinguished	O
by	O
a	O
flipped	O
physical	O
connector	O
to	O
prevent	O
accidental	O
insertion	O
of	O
5V	O
cards	O
.	O
</s>
<s>
Version	O
2.1	O
of	O
the	O
PCI	B-Protocol
standard	O
introduced	O
optional	O
66MHz	O
operation	O
.	O
</s>
<s>
A	O
server-oriented	O
variant	O
of	O
PCI	B-Protocol
,	O
PCI	B-Protocol
Extended	O
(	O
PCI-X	O
)	O
operated	O
at	O
frequencies	O
up	O
to	O
133MHz	O
for	O
PCI-X	O
1.0	O
and	O
up	O
to	O
533MHz	O
for	O
PCI-X	O
2.0	O
.	O
</s>
<s>
An	O
internal	O
connector	O
for	O
laptop	B-Device
cards	O
,	O
called	O
Mini	O
PCI	B-Protocol
,	O
was	O
introduced	O
in	O
version	O
2.2	O
of	O
the	O
PCI	B-Protocol
specification	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
was	O
also	O
adopted	O
for	O
an	O
external	O
laptop	B-Device
connector	O
standard	O
the	O
CardBus	O
.	O
</s>
<s>
The	O
first	O
PCI	B-Protocol
specification	O
was	O
developed	O
by	O
Intel	O
,	O
but	O
subsequent	O
development	O
of	O
the	O
standard	O
became	O
the	O
responsibility	O
of	O
the	O
PCI	B-Protocol
Special	O
Interest	O
Group	O
(	O
PCI-SIG	O
)	O
.	O
</s>
<s>
PCI	B-Protocol
and	O
PCI-X	O
sometimes	O
are	O
referred	O
to	O
as	O
either	O
Parallel	O
PCI	B-Protocol
or	O
Conventional	B-Protocol
PCI	I-Protocol
to	O
distinguish	O
them	O
technologically	O
from	O
their	O
more	O
recent	O
successor	O
PCI	B-Protocol
Express	O
,	O
which	O
adopted	O
a	O
serial	B-Protocol
,	O
lane-based	O
architecture	O
.	O
</s>
<s>
PCI	B-Protocol
's	O
heyday	O
in	O
the	O
desktop	O
computer	O
market	O
was	O
approximately	O
1995	O
to	O
2005	O
.	O
</s>
<s>
PCI	B-Protocol
and	O
PCI-X	O
have	O
become	O
obsolete	O
for	O
most	O
purposes	O
;	O
however	O
in	O
2020	O
they	O
are	O
still	O
common	O
on	O
modern	O
desktops	O
for	O
the	O
purposes	O
of	O
backward	B-General_Concept
compatibility	I-General_Concept
and	O
the	O
low	O
relative	O
cost	O
to	O
produce	O
.	O
</s>
<s>
Another	O
common	O
modern	O
application	O
of	O
parallel	O
PCI	B-Protocol
is	O
in	O
industrial	B-Device
PCs	I-Device
,	O
where	O
many	O
specialized	O
expansion	B-Device
cards	I-Device
,	O
used	O
here	O
,	O
never	O
transitioned	O
to	O
PCI	B-Protocol
Express	O
,	O
just	O
as	O
with	O
some	O
ISA	B-Architecture
cards	I-Architecture
.	O
</s>
<s>
Many	O
kinds	O
of	O
devices	O
formerly	O
available	O
on	O
PCI	B-Protocol
expansion	B-Device
cards	I-Device
are	O
now	O
commonly	O
integrated	O
onto	O
motherboards	B-Device
or	O
available	O
in	O
USB	B-Protocol
and	O
PCI	B-Protocol
Express	O
versions	O
.	O
</s>
<s>
Work	O
on	O
PCI	B-Protocol
began	O
at	O
the	O
Intel	O
Architecture	O
Labs	O
(	O
IAL	O
,	O
also	O
Architecture	O
Development	O
Lab	O
)	O
.	O
</s>
<s>
PCI	B-Protocol
was	O
immediately	O
put	O
to	O
use	O
in	O
servers	O
,	O
replacing	O
Micro	B-Device
Channel	I-Device
architecture	I-Device
(	O
MCA	B-Device
)	O
and	O
Extended	B-Device
Industry	I-Device
Standard	I-Device
Architecture	I-Device
(	O
EISA	B-Device
)	O
as	O
the	O
server	O
expansion	B-Device
bus	I-Device
of	O
choice	O
.	O
</s>
<s>
In	O
mainstream	O
PCs	O
,	O
PCI	B-Protocol
was	O
slower	O
to	O
replace	O
VLB	O
,	O
and	O
did	O
not	O
gain	O
significant	O
market	O
penetration	O
until	O
late	O
1994	O
in	O
second-generation	O
Pentium	B-General_Concept
PCs	O
.	O
</s>
<s>
By	O
1996	O
,	O
VLB	O
was	O
all	O
but	O
extinct	O
,	O
and	O
manufacturers	O
had	O
adopted	O
PCI	B-Protocol
even	O
for	O
Intel	B-General_Concept
80486	I-General_Concept
(	O
486	B-General_Concept
)	O
computers	O
.	O
</s>
<s>
EISA	B-Device
continued	O
to	O
be	O
used	O
alongside	O
PCI	B-Protocol
through	O
2000	O
.	O
</s>
<s>
Apple	O
Computer	O
adopted	O
PCI	B-Protocol
for	O
professional	O
Power	B-Device
Macintosh	I-Device
computers	O
(	O
replacing	O
NuBus	B-Device
)	O
in	O
mid-1995	O
,	O
and	O
the	O
consumer	O
Performa	B-Device
product	O
line	O
(	O
replacing	O
LC	O
Processor	B-Device
Direct	I-Device
Slot	I-Device
(	O
PDS	O
)	O
)	O
in	O
mid-1996	O
.	O
</s>
<s>
Outside	O
the	O
server	O
market	O
,	O
the	O
64-bit	B-Device
version	O
of	O
plain	O
PCI	B-Protocol
remained	O
rare	O
in	O
practice	O
though	O
,	O
although	O
it	O
was	O
used	O
for	O
example	O
by	O
all	O
(	O
post-iMac	O
)	O
G3	O
and	O
G4	B-Device
Power	I-Device
Macintosh	I-Device
computers	I-Device
.	O
</s>
<s>
Later	O
revisions	O
of	O
PCI	B-Protocol
added	O
new	O
features	O
and	O
performance	O
improvements	O
,	O
including	O
a	O
66MHz	O
3.3V	O
standard	O
and	O
133MHz	O
PCI-X	O
,	O
and	O
the	O
adaptation	O
of	O
PCI	B-Protocol
signaling	O
to	O
other	O
form	O
factors	O
.	O
</s>
<s>
Both	O
PCI-X1.0b	O
and	O
PCI-X2.0	O
are	O
backward	B-General_Concept
compatible	I-General_Concept
with	O
some	O
PCI	B-Protocol
standards	O
.	O
</s>
<s>
These	O
revisions	O
were	O
used	O
on	O
server	O
hardware	B-Architecture
but	O
consumer	O
PC	B-Architecture
hardware	I-Architecture
remained	O
nearly	O
all	O
32-bit	O
,	O
33MHz	O
and	O
5	O
volt	O
.	O
</s>
<s>
The	O
PCI-SIG	O
introduced	O
the	O
serial	B-Protocol
PCI	B-Protocol
Express	O
in	O
.	O
</s>
<s>
Since	O
then	O
,	O
motherboard	B-Device
manufacturers	O
have	O
included	O
progressively	O
fewer	O
PCI	B-Protocol
slots	I-Protocol
in	O
favor	O
of	O
the	O
new	O
standard	O
.	O
</s>
<s>
Many	O
new	O
motherboards	B-Device
do	O
not	O
provide	O
PCI	B-Protocol
slots	I-Protocol
at	O
all	O
,	O
as	O
of	O
late	O
2013	O
.	O
</s>
<s>
PCI	B-Protocol
provides	O
separate	O
memory	O
and	O
memory-mapped	B-Architecture
I/O	I-Architecture
port	O
address	B-General_Concept
spaces	I-General_Concept
for	O
the	O
x86	B-Operating_System
processor	O
family	O
,	O
64	B-Device
and	O
32	O
bits	O
,	O
respectively	O
.	O
</s>
<s>
Addresses	O
in	O
these	O
address	B-General_Concept
spaces	I-General_Concept
are	O
assigned	O
by	O
software	O
.	O
</s>
<s>
A	O
third	O
address	B-General_Concept
space	I-General_Concept
,	O
called	O
the	O
PCI	B-Architecture
Configuration	I-Architecture
Space	I-Architecture
,	O
which	O
uses	O
a	O
fixed	O
addressing	O
scheme	O
,	O
allows	O
software	O
to	O
determine	O
the	O
amount	O
of	O
memory	O
and	O
I/O	B-Architecture
address	B-General_Concept
space	I-General_Concept
needed	O
by	O
each	O
device	O
.	O
</s>
<s>
Each	O
device	O
can	O
request	O
up	O
to	O
six	O
areas	O
of	O
memory	O
space	O
or	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
port	O
space	O
via	O
its	O
configuration	O
space	O
registers	O
.	O
</s>
<s>
In	O
a	O
typical	O
system	O
,	O
the	O
firmware	B-Application
(	O
or	O
operating	B-General_Concept
system	I-General_Concept
)	O
queries	O
all	O
PCI	B-Protocol
buses	O
at	O
startup	O
time	O
(	O
via	O
PCI	B-Architecture
Configuration	I-Architecture
Space	I-Architecture
)	O
to	O
find	O
out	O
what	O
devices	O
are	O
present	O
and	O
what	O
system	O
resources	O
(	O
memory	O
space	O
,	O
I/O	B-General_Concept
space	O
,	O
interrupt	B-Application
lines	I-Application
,	O
etc	O
.	O
)	O
</s>
<s>
The	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
also	O
contains	O
a	O
small	O
amount	O
of	O
device	O
type	O
information	O
,	O
which	O
helps	O
an	O
operating	B-General_Concept
system	I-General_Concept
choose	O
device	O
drivers	O
for	O
it	O
,	O
or	O
at	O
least	O
to	O
have	O
a	O
dialogue	O
with	O
a	O
user	O
about	O
the	O
system	O
configuration	O
.	O
</s>
<s>
Devices	O
may	O
have	O
an	O
on-board	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
containing	O
executable	O
code	O
for	O
x86	B-Operating_System
or	O
PA-RISC	B-Device
processors	O
,	O
an	O
Open	B-Architecture
Firmware	I-Architecture
driver	O
,	O
or	O
an	O
Option	B-Device
ROM	I-Device
.	O
</s>
<s>
These	O
are	O
typically	O
needed	O
for	O
devices	O
used	O
during	O
system	O
startup	O
,	O
before	O
device	O
drivers	O
are	O
loaded	O
by	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
In	O
addition	O
,	O
there	O
are	O
PCI	B-Protocol
Latency	O
Timers	O
that	O
are	O
a	O
mechanism	O
for	O
PCI	B-Protocol
Bus-Mastering	O
devices	O
to	O
share	O
the	O
PCI	B-Protocol
bus	I-Protocol
fairly	O
.	O
</s>
<s>
"	O
Fair	O
"	O
in	O
this	O
case	O
means	O
that	O
devices	O
will	O
not	O
use	O
such	O
a	O
large	O
portion	O
of	O
the	O
available	O
PCI	B-Protocol
bus	I-Protocol
bandwidth	O
that	O
other	O
devices	O
are	O
not	O
able	O
to	O
get	O
needed	O
work	O
done	O
.	O
</s>
<s>
Note	O
,	O
this	O
does	O
not	O
apply	O
to	O
PCI	B-Protocol
Express	O
.	O
</s>
<s>
Devices	O
are	O
required	O
to	O
follow	O
a	O
protocol	O
so	O
that	O
the	O
interrupt	B-Application
lines	I-Application
can	O
be	O
shared	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
includes	O
four	O
interrupt	B-Application
pins	O
,	O
later	O
allow	O
up	O
to	O
8	O
PCI	B-Protocol
devices	O
share	O
the	O
same	O
interrupt	B-Application
line	I-Application
in	O
APIC	O
systems	O
,	O
all	O
of	O
which	O
are	O
available	O
to	O
each	O
device	O
.	O
</s>
<s>
However	O
,	O
they	O
are	O
not	O
wired	O
in	O
parallel	O
as	O
are	O
the	O
other	O
PCI	B-Protocol
bus	I-Protocol
lines	O
.	O
</s>
<s>
The	O
positions	O
of	O
the	O
interrupt	B-Application
lines	I-Application
rotate	O
between	O
slots	O
,	O
so	O
what	O
appears	O
to	O
one	O
device	O
as	O
the	O
INTA#	O
pin	O
is	O
INTB#	O
to	O
the	O
next	O
and	O
INTC#	O
to	O
the	O
one	O
after	O
that	O
.	O
</s>
<s>
Single-function	O
devices	O
usually	O
use	O
their	O
INTA#	O
for	O
interrupt	B-Application
signaling	O
,	O
so	O
the	O
device	O
load	O
is	O
spread	O
fairly	O
evenly	O
across	O
the	O
four	O
available	O
interrupt	B-Application
pins	O
.	O
</s>
<s>
This	O
alleviates	O
a	O
common	O
problem	O
with	O
sharing	O
interrupts	B-Application
.	O
</s>
<s>
The	O
mapping	O
of	O
PCI	B-Protocol
interrupt	B-Application
lines	I-Application
onto	O
system	O
interrupt	B-Application
lines	I-Application
,	O
through	O
the	O
PCI	B-Device
host	I-Device
bridge	I-Device
,	O
is	O
implementation-dependent	O
.	O
</s>
<s>
Platform-specific	O
Basic	B-Operating_System
Input/Output	I-Operating_System
System	I-Operating_System
(	O
BIOS	B-Operating_System
)	O
code	O
is	O
meant	O
to	O
know	O
this	O
,	O
and	O
set	O
the	O
"	O
interrupt	B-Application
line	I-Application
"	O
field	O
in	O
each	O
device	O
's	O
configuration	O
space	O
indicating	O
which	O
IRQ	O
it	O
is	O
connected	O
to	O
.	O
</s>
<s>
PCI	B-Protocol
interrupt	B-Application
lines	I-Application
are	O
level-triggered	O
.	O
</s>
<s>
This	O
was	O
chosen	O
over	O
edge-triggering	O
to	O
gain	O
an	O
advantage	O
when	O
servicing	O
a	O
shared	O
interrupt	B-Application
line	I-Application
,	O
and	O
for	O
robustness	O
:	O
edge	B-Application
triggered	I-Application
interrupts	I-Application
are	O
easy	O
to	O
miss	O
.	O
</s>
<s>
Later	O
revisions	O
of	O
the	O
PCI	B-Protocol
specification	O
add	O
support	O
for	O
message-signaled	B-Architecture
interrupts	I-Architecture
.	O
</s>
<s>
This	O
alleviates	O
the	O
problem	O
of	O
scarcity	O
of	O
interrupt	B-Application
lines	I-Application
.	O
</s>
<s>
Even	O
if	O
interrupt	B-Application
vectors	O
are	O
still	O
shared	O
,	O
it	O
does	O
not	O
suffer	O
the	O
sharing	O
problems	O
of	O
level-triggered	O
interrupts	B-Application
.	O
</s>
<s>
Finally	O
,	O
because	O
the	O
message	O
signaling	O
is	O
in-band	O
,	O
it	O
resolves	O
some	O
synchronization	O
problems	O
that	O
can	O
occur	O
with	O
posted	O
writes	O
and	O
out-of-band	B-Protocol
interrupt	B-Application
lines	I-Application
.	O
</s>
<s>
PCI	B-Protocol
Express	O
does	O
not	O
have	O
physical	O
interrupt	B-Application
lines	I-Application
at	O
all	O
.	O
</s>
<s>
It	O
uses	O
message-signaled	B-Architecture
interrupts	I-Architecture
exclusively	O
.	O
</s>
<s>
These	O
specifications	O
represent	O
the	O
most	O
common	O
version	O
of	O
PCI	B-Protocol
used	O
in	O
normal	O
PCs	O
:	O
</s>
<s>
The	O
PCI	B-Protocol
specification	O
also	O
provides	O
options	O
for	O
3.3V	O
signaling	O
,	O
64-bit	B-Device
bus	B-General_Concept
width	O
,	O
and	O
66MHz	O
clocking	O
,	O
but	O
these	O
are	O
not	O
commonly	O
encountered	O
outside	O
of	O
PCI-X	O
support	O
on	O
server	O
motherboards	B-Device
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
arbiter	O
performs	O
bus	B-Architecture
arbitration	I-Architecture
among	O
multiple	O
masters	O
on	O
the	O
PCI	B-Protocol
bus	I-Protocol
.	O
</s>
<s>
Any	O
number	O
of	O
bus	B-Architecture
masters	I-Architecture
can	O
reside	O
on	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
as	O
well	O
as	O
requests	O
for	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
One	O
pair	O
of	O
request	O
and	O
grant	O
signals	O
is	O
dedicated	O
to	O
each	O
bus	B-Architecture
master	I-Architecture
.	O
</s>
<s>
Typical	O
PCI	B-Protocol
cards	I-Protocol
have	O
either	O
one	O
or	O
two	O
key	O
notches	O
,	O
depending	O
on	O
their	O
signaling	O
voltage	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
connector	O
is	O
defined	O
as	O
having	O
62	O
contacts	O
on	O
each	O
side	O
of	O
the	O
edge	O
connector	O
,	O
but	O
two	O
or	O
four	O
of	O
them	O
are	O
replaced	O
by	O
key	O
notches	O
,	O
so	O
a	O
card	O
has	O
60	O
or	O
58	O
contacts	O
on	O
each	O
side	O
.	O
</s>
<s>
The	O
pinout	O
of	O
B	O
and	O
A	O
sides	O
are	O
as	O
follows	O
,	O
looking	O
down	O
into	O
the	O
motherboard	B-Device
connector	O
(	O
pins	O
A1	O
and	O
B1	O
are	O
closest	O
to	O
backplate	O
)	O
.	O
</s>
<s>
Management	O
Interface	O
Specification	O
v1.2	O
20	O
AD[31]	O
AD[30]	O
Address/data	O
bus	B-General_Concept
(	O
upper	O
half	O
)	O
21	O
AD[29]	O
+	O
3.3	O
V	O
22	O
Ground	O
AD[28]	O
23	O
AD[27]	O
AD[26]	O
24	O
AD[25]	O
Ground	O
25	O
+	O
3.3	O
V	O
AD[24]	O
26	O
C/BE[3]#	O
IDSEL	O
27	O
AD[23]	O
+	O
3.3	O
V	O
28	O
Ground	O
AD[22]	O
29	O
AD[21]	O
AD[20]	O
30	O
AD[19]	O
Ground	O
31	O
+	O
3.3	O
V	O
AD[18]	O
32	O
AD[17]	O
AD[16]	O
33	O
C/BE[2]#	O
+	O
3.3	O
V	O
34	O
Ground	O
FRAME#	O
Bus	B-General_Concept
transfer	O
in	O
progress	O
35	O
IRDY#	O
Ground	O
Initiator	O
ready	O
36	O
+	O
3.3	O
V	O
TRDY#	O
Target	O
ready	O
37	O
DEVSEL#	O
Ground	O
Target	O
selected	O
38	O
PCIXCAP	O
Ground	O
STOP#	O
PCI-X	O
capable	O
;	O
Target	O
requests	O
halt	O
39	O
LOCK#	O
+	O
3.3	O
V	O
Locked	O
transaction	O
40	O
PERR#	O
SMBCLK	O
SDONE	O
Parity	O
error	O
;	O
SMBus	B-Algorithm
clock	O
or	O
Snoop	O
done	O
(	O
obsolete	O
)	O
41	O
+	O
3.3	O
V	O
SMBDAT	O
SBO#	O
SMBus	B-Algorithm
data	O
or	O
Snoop	O
backoff	O
(	O
obsolete	O
)	O
42	O
SERR#	O
Ground	O
System	O
error	O
43	O
+	O
3.3	O
V	O
PAR	O
Even	O
parity	O
over	O
AD[31:00]	O
and	O
C/BE[3:0]#	O
44	O
C/BE[1]#	O
AD[15]	O
Address/data	O
bus	B-General_Concept
(	O
higher	O
half	O
)	O
45	O
AD[14]	O
+	O
3.3	O
V	O
46	O
Ground	O
AD[13]	O
47	O
AD[12]	O
AD[11]	O
48	O
AD[10]	O
Ground	O
49	O
M66EN	O
Ground	O
AD[09]	O
50	O
Ground	O
Ground	O
Key	O
notch	O
for	O
5	O
V-capable	O
cards	O
51	O
Ground	O
Ground	O
52	O
AD[08]	O
C/BE[0]#	O
Address/data	O
bus	B-General_Concept
(	O
lower	O
half	O
)	O
53	O
AD[07]	O
+	O
3.3	O
V	O
54	O
+	O
3.3	O
V	O
AD[06]	O
55	O
AD[05]	O
AD[04]	O
56	O
AD[03]	O
Ground	O
57	O
Ground	O
AD[02]	O
58	O
AD[01]	O
AD[00]	O
59	O
IOPWR	O
IOPWR	O
60	O
ACK64#	O
REQ64#	O
For	O
64-bit	B-Device
extension	O
;	O
no	O
connect	O
for	O
32-bit	O
devices	O
.	O
</s>
<s>
64-bit	B-Device
PCI	B-Protocol
extends	O
this	O
by	O
an	O
additional	O
32	O
contacts	O
on	O
each	O
side	O
which	O
provide	O
AD[63:32],	O
C/BE[7:4]#,	O
the	O
PAR64	O
parity	O
signal	O
,	O
and	O
a	O
number	O
of	O
power	O
and	O
ground	O
pins	O
.	O
</s>
<s>
Each	O
slot	O
has	O
its	O
own	O
REQ#	O
output	O
to	O
,	O
and	O
GNT#	O
input	O
from	O
the	O
motherboard	B-Device
arbiter	O
.	O
</s>
<s>
PRSNT1#	O
and	O
PRSNT2#	O
for	O
each	O
slot	O
have	O
their	O
own	O
pull-up	O
resistors	O
on	O
the	O
motherboard	B-Device
.	O
</s>
<s>
The	O
motherboard	B-Device
may	O
(	O
but	O
does	O
not	O
have	O
to	O
)	O
sense	O
these	O
pins	O
to	O
determine	O
the	O
presence	O
of	O
PCI	B-Protocol
cards	I-Protocol
and	O
their	O
power	O
requirements	O
.	O
</s>
<s>
The	O
interrupt	B-Application
pins	O
INTA#	O
through	O
INTD#	O
are	O
connected	O
to	O
all	O
slots	O
in	O
different	O
orders	O
.	O
</s>
<s>
Universal	O
cards	O
have	O
both	O
key	O
notches	O
and	O
use	O
IOPWR	O
to	O
determine	O
their	O
I/O	B-General_Concept
signal	O
levels	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
SIG	O
strongly	O
encourages	O
3.3V	O
PCI	B-Protocol
signaling	O
,	O
requiring	O
support	O
for	O
it	O
since	O
standard	O
revision	O
2.3	O
,	O
but	O
most	O
PC	B-Device
motherboards	I-Device
use	O
the	O
5V	O
variant	O
.	O
</s>
<s>
Thus	O
,	O
while	O
many	O
currently	O
available	O
PCI	B-Protocol
cards	I-Protocol
support	O
both	O
,	O
and	O
have	O
two	O
key	O
notches	O
to	O
indicate	O
that	O
,	O
there	O
are	O
still	O
a	O
large	O
number	O
of	O
5V-only	O
cards	O
on	O
the	O
market	O
.	O
</s>
<s>
The	O
M66EN	O
pin	O
is	O
an	O
additional	O
ground	O
on	O
5V	O
PCI	B-Protocol
buses	O
found	O
in	O
most	O
PC	B-Device
motherboards	I-Device
.	O
</s>
<s>
Cards	O
and	O
motherboards	B-Device
that	O
do	O
not	O
support	O
66MHz	O
operation	O
also	O
ground	O
this	O
pin	O
.	O
</s>
<s>
If	O
all	O
participants	O
support	O
66MHz	O
operation	O
,	O
a	O
pull-up	O
resistor	O
on	O
the	O
motherboard	B-Device
raises	O
this	O
signal	O
high	O
and	O
66MHz	O
operation	O
is	O
enabled	O
.	O
</s>
<s>
The	O
PCIXCAP	O
pin	O
is	O
an	O
additional	O
ground	O
on	O
PCI	B-Protocol
buses	O
and	O
cards	O
.	O
</s>
<s>
If	O
all	O
cards	O
and	O
the	O
motherboard	B-Device
support	O
the	O
PCI-X	O
protocol	O
,	O
a	O
pull-up	O
resistor	O
on	O
the	O
motherboard	B-Device
raises	O
this	O
signal	O
high	O
and	O
PCI-X	O
operation	O
is	O
enabled	O
.	O
</s>
<s>
SBO#	O
and	O
SDONE	O
are	O
signals	O
from	O
a	O
cache	B-General_Concept
controller	O
to	O
the	O
current	O
target	O
.	O
</s>
<s>
PME#	O
(	O
)	O
Power	O
management	O
event	O
(	O
optional	O
)	O
which	O
is	O
supported	O
in	O
PCI	B-Protocol
and	O
higher	O
.	O
</s>
<s>
PCI	B-Protocol
cards	I-Protocol
may	O
use	O
this	O
signal	O
to	O
send	O
and	O
receive	O
PME	O
via	O
the	O
PCI	B-Protocol
socket	O
directly	O
,	O
which	O
eliminates	O
the	O
need	O
for	O
a	O
special	O
Wake-on-LAN	O
cable	O
.	O
</s>
<s>
Most	O
32-bit	O
PCI	B-Protocol
cards	I-Protocol
will	O
function	O
properly	O
in	O
64-bit	B-Device
PCI-X	O
slots	O
,	O
but	O
the	O
bus	B-General_Concept
clock	O
rate	O
will	O
be	O
limited	O
to	O
the	O
clock	O
frequency	O
of	O
the	O
slowest	O
card	O
,	O
an	O
inherent	O
limitation	O
of	O
PCI	B-Protocol
's	O
shared	O
bus	B-General_Concept
topology	O
.	O
</s>
<s>
For	O
example	O
,	O
when	O
a	O
PCI	B-Protocol
2.3	I-Protocol
,	O
66-MHz	O
peripheral	O
is	O
installed	O
into	O
a	O
PCI-X	O
bus	B-General_Concept
capable	O
of	O
133MHz	O
,	O
the	O
entire	O
bus	B-General_Concept
backplane	O
will	O
be	O
limited	O
to	O
66MHz	O
.	O
</s>
<s>
To	O
get	O
around	O
this	O
limitation	O
,	O
many	O
motherboards	B-Device
have	O
two	O
or	O
more	O
PCI/PCI	O
-X	O
buses	O
,	O
with	O
one	O
bus	B-General_Concept
intended	O
for	O
use	O
with	O
high-speed	O
PCI-X	O
peripherals	O
,	O
and	O
the	O
other	O
bus	B-General_Concept
intended	O
for	O
general-purpose	O
peripherals	O
.	O
</s>
<s>
Many	O
64-bit	B-Device
PCI-X	O
cards	O
are	O
designed	O
to	O
work	O
in	O
32-bit	O
mode	O
if	O
inserted	O
in	O
shorter	O
32-bit	O
connectors	O
,	O
with	O
some	O
loss	O
of	O
performance	O
.	O
</s>
<s>
An	O
example	O
of	O
this	O
is	O
the	O
Adaptec	O
29160	O
64-bit	B-Device
SCSI	B-Architecture
interface	O
card	O
.	O
</s>
<s>
However	O
,	O
some	O
64-bit	B-Device
PCI-X	O
cards	O
do	O
not	O
work	O
in	O
standard	O
32-bit	O
PCI	B-Protocol
slots	I-Protocol
.	O
</s>
<s>
Installing	O
a	O
64-bit	B-Device
PCI-X	O
card	O
in	O
a	O
32-bit	O
slot	O
will	O
leave	O
the	O
64-bit	B-Device
portion	O
of	O
the	O
card	O
edge	O
connector	O
not	O
connected	O
and	O
overhanging	O
.	O
</s>
<s>
This	O
requires	O
that	O
there	O
be	O
no	O
motherboard	B-Device
components	O
positioned	O
so	O
as	O
to	O
mechanically	O
obstruct	O
the	O
overhanging	O
portion	O
of	O
the	O
card	O
edge	O
connector	O
.	O
</s>
<s>
PCI	B-Protocol
brackets	O
heights	O
:	O
</s>
<s>
PCI	B-Protocol
Card	I-Protocol
lengths	O
(	O
Standard	O
Bracket	O
&	O
3.3V	O
)	O
:	O
</s>
<s>
PCI	B-Protocol
Card	I-Protocol
lengths	O
(	O
Low	O
Profile	O
Bracket	O
&	O
3.3V	O
)	O
:	O
</s>
<s>
Mini	O
PCI	B-Protocol
was	O
added	O
to	O
PCI	B-Protocol
version	O
2.2	O
for	O
use	O
in	O
laptops	B-Device
;	O
it	O
uses	O
a	O
32-bit	O
,	O
33MHz	O
bus	B-General_Concept
with	O
powered	O
connections	O
(	O
3.3V	O
only	O
;	O
5V	O
is	O
limited	O
to	O
100mA	O
)	O
and	O
support	O
for	O
bus	B-Architecture
mastering	I-Architecture
and	O
DMA	B-General_Concept
.	O
</s>
<s>
The	O
standard	O
size	O
for	O
Mini	O
PCI	B-Protocol
cards	I-Protocol
is	O
approximately	O
a	O
quarter	O
of	O
their	O
full-sized	O
counterparts	O
.	O
</s>
<s>
There	O
is	O
no	O
access	O
to	O
the	O
card	O
from	O
outside	O
the	O
case	O
,	O
unlike	O
desktop	O
PCI	B-Protocol
cards	I-Protocol
with	O
brackets	O
carrying	O
connectors	O
.	O
</s>
<s>
This	O
limits	O
the	O
kinds	O
of	O
functions	O
a	O
Mini	O
PCI	B-Protocol
card	I-Protocol
can	O
perform	O
.	O
</s>
<s>
Many	O
Mini	O
PCI	B-Protocol
devices	O
were	O
developed	O
such	O
as	O
Wi-Fi	O
,	O
Fast	B-Protocol
Ethernet	I-Protocol
,	O
Bluetooth	B-Protocol
,	O
modems	B-Application
(	O
often	O
Winmodems	B-Device
)	O
,	O
sound	B-Device
cards	I-Device
,	O
cryptographic	B-General_Concept
accelerators	I-General_Concept
,	O
SCSI	B-Architecture
,	O
IDE	B-Protocol
–	O
ATA	B-Protocol
,	O
SATA	O
controllers	O
and	O
combination	O
cards	O
.	O
</s>
<s>
Mini	O
PCI	B-Protocol
cards	I-Protocol
can	O
be	O
used	O
with	O
regular	O
PCI-equipped	O
hardware	B-Architecture
,	O
using	O
Mini	O
PCI-to-PCI	O
converters	O
.	O
</s>
<s>
Mini	O
PCI	B-Protocol
cards	I-Protocol
have	O
a	O
2W	O
maximum	O
power	O
consumption	O
,	O
which	O
limits	O
the	O
functionality	O
that	O
can	O
be	O
implemented	O
in	O
this	O
form	O
factor	O
.	O
</s>
<s>
They	O
also	O
are	O
required	O
to	O
support	O
the	O
CLKRUN#	O
PCI	B-Protocol
signal	O
used	O
to	O
start	O
and	O
stop	O
the	O
PCI	B-Protocol
clock	O
for	O
power	O
management	O
purposes	O
.	O
</s>
<s>
The	O
additional	O
24	O
pins	O
provide	O
the	O
extra	O
signals	O
required	O
to	O
route	O
I/O	B-General_Concept
back	O
through	O
the	O
system	O
connector	O
(	O
audio	O
,	O
AC-Link	O
,	O
LAN	B-General_Concept
,	O
phone-line	O
interface	O
)	O
.	O
</s>
<s>
Mini	O
PCI	B-Protocol
is	O
distinct	O
from	O
144-pin	O
Micro	O
PCI	B-Protocol
.	O
</s>
<s>
PCI	B-Protocol
bus	I-Protocol
traffic	O
consists	O
of	O
a	O
series	O
of	O
PCI	B-Protocol
bus	I-Protocol
transactions	O
.	O
</s>
<s>
(	O
One	O
common	O
example	O
is	O
a	O
low-performance	O
PCI	B-Protocol
device	O
that	O
does	O
not	O
support	O
burst	B-Architecture
transactions	I-Architecture
,	O
and	O
always	O
halts	O
a	O
transaction	O
after	O
the	O
first	O
data	O
phase	O
.	O
)	O
</s>
<s>
Any	O
PCI	B-Protocol
device	O
may	O
initiate	O
a	O
transaction	O
.	O
</s>
<s>
First	O
,	O
it	O
must	O
request	O
permission	O
from	O
a	O
PCI	B-Protocol
bus	I-Protocol
arbiter	O
on	O
the	O
motherboard	B-Device
.	O
</s>
<s>
64-bit	B-Device
addressing	O
is	O
done	O
using	O
a	O
two-stage	O
address	O
phase	O
.	O
</s>
<s>
Devices	O
which	O
do	O
not	O
support	O
64-bit	B-Device
addressing	O
can	O
simply	O
not	O
respond	O
to	O
that	O
command	O
code	O
.	O
</s>
<s>
To	O
ensure	O
compatibility	O
with	O
32-bit	O
PCI	B-Protocol
devices	O
,	O
it	O
is	O
forbidden	O
to	O
use	O
a	O
dual	O
address	O
cycle	O
if	O
not	O
necessary	O
,	O
i.e.	O
</s>
<s>
While	O
the	O
PCI	B-Protocol
bus	I-Protocol
transfers	O
32	O
bits	O
per	O
data	O
phase	O
,	O
the	O
initiator	O
transmits	O
4	O
active-low	O
byte	B-Application
enable	O
signals	O
indicating	O
which	O
8-bit	O
bytes	B-Application
are	O
to	O
be	O
considered	O
significant	O
.	O
</s>
<s>
In	O
particular	O
,	O
a	O
write	O
must	O
affect	O
only	O
the	O
enabled	O
bytes	B-Application
in	O
the	O
target	O
PCI	B-Protocol
device	O
.	O
</s>
<s>
They	O
are	O
of	O
little	O
importance	O
for	O
memory	O
reads	O
,	O
but	O
I/O	B-General_Concept
reads	O
might	O
have	O
side	O
effects	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
standard	O
explicitly	O
allows	O
a	O
data	O
phase	O
with	O
no	O
bytes	B-Application
enabled	O
,	O
which	O
must	O
behave	O
as	O
a	O
no-op	O
.	O
</s>
<s>
PCI	B-Protocol
has	O
three	O
address	B-General_Concept
spaces	I-General_Concept
:	O
memory	O
,	O
I/O	B-Architecture
address	I-Architecture
,	O
and	O
configuration	O
.	O
</s>
<s>
Memory	O
addresses	O
are	O
32bits	O
(	O
optionally	O
64	B-Device
bits	I-Device
)	O
in	O
size	O
,	O
support	O
caching	B-General_Concept
and	O
can	O
be	O
burst	B-Architecture
transactions	I-Architecture
.	O
</s>
<s>
I/O	B-General_Concept
addresses	O
are	O
for	O
compatibility	O
with	O
the	O
Intel	B-Operating_System
x86	I-Operating_System
architecture	O
's	O
I/O	B-Architecture
port	I-Architecture
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
Although	O
the	O
PCI	B-Protocol
bus	I-Protocol
specification	O
allows	O
burst	B-Architecture
transactions	I-Architecture
in	O
any	O
address	B-General_Concept
space	I-General_Concept
,	O
most	O
devices	O
only	O
support	O
it	O
for	O
memory	O
addresses	O
and	O
not	O
I/O	B-General_Concept
.	O
</s>
<s>
Finally	O
,	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
provides	O
access	O
to	O
256	O
bytes	B-Application
of	O
special	O
configuration	O
registers	O
per	O
PCI	B-Protocol
device	O
.	O
</s>
<s>
Each	O
PCI	B-Protocol
slot	I-Protocol
gets	O
its	O
own	O
configuration	O
space	O
address	B-General_Concept
range	I-General_Concept
.	O
</s>
<s>
The	O
registers	O
are	O
used	O
to	O
configure	O
devices	O
memory	O
and	O
I/O	B-Architecture
address	I-Architecture
ranges	O
they	O
should	O
respond	O
to	O
from	O
transaction	O
initiators	O
.	O
</s>
<s>
When	O
a	O
computer	O
is	O
first	O
turned	O
on	O
,	O
all	O
PCI	B-Protocol
devices	O
respond	O
only	O
to	O
their	O
configuration	O
space	O
accesses	O
.	O
</s>
<s>
The	O
computer	O
's	O
BIOS	B-Operating_System
scans	O
for	O
devices	O
and	O
assigns	O
Memory	O
and	O
I/O	B-Architecture
address	I-Architecture
ranges	O
to	O
them	O
.	O
</s>
<s>
PCI	B-Protocol
devices	O
therefore	O
generally	O
attempt	O
to	O
avoid	O
using	O
the	O
all-ones	O
value	O
in	O
important	O
status	O
registers	O
,	O
so	O
that	O
such	O
an	O
error	O
can	O
be	O
easily	O
detected	O
by	O
software	O
.	O
</s>
<s>
PCI	B-Protocol
targets	O
must	O
examine	O
the	O
command	O
code	O
as	O
well	O
as	O
the	O
address	O
and	O
not	O
respond	O
to	O
address	O
phases	O
which	O
specify	O
an	O
unsupported	O
command	O
code	O
.	O
</s>
<s>
The	O
commands	O
that	O
refer	O
to	O
cache	B-General_Concept
lines	O
depend	O
on	O
the	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
cache	B-General_Concept
line	O
size	O
register	O
being	O
set	O
up	O
properly	O
;	O
they	O
may	O
not	O
be	O
used	O
until	O
that	O
has	O
been	O
done	O
.	O
</s>
<s>
This	O
is	O
a	O
special	O
form	O
of	O
read	O
cycle	O
implicitly	O
addressed	O
to	O
the	O
interrupt	B-Application
controller	O
,	O
which	O
returns	O
an	O
interrupt	B-Application
vector	O
.	O
</s>
<s>
One	O
possible	O
implementation	O
is	O
to	O
generate	O
an	O
interrupt	B-Application
acknowledge	O
cycle	O
on	O
an	O
ISA	B-Architecture
bus	I-Architecture
using	O
a	O
PCI/ISA	O
bus	O
bridge	O
.	O
</s>
<s>
This	O
command	O
is	O
for	O
IBM	O
PC	O
compatibility	O
;	O
if	O
there	O
is	O
no	O
Intel	B-Device
8259	I-Device
style	O
interrupt	B-Application
controller	O
on	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
this	O
cycle	O
need	O
never	O
be	O
used	O
.	O
</s>
<s>
This	O
cycle	O
is	O
a	O
special	O
broadcast	O
write	O
of	O
system	O
events	O
that	O
PCI	B-Protocol
card	I-Protocol
may	O
be	O
interested	O
in	O
.	O
</s>
<s>
No	O
device	O
ever	O
responds	O
to	O
this	O
cycle	O
;	O
it	O
is	O
always	O
terminated	O
with	O
a	O
master	O
abort	O
after	O
leaving	O
the	O
data	O
on	O
the	O
bus	B-General_Concept
for	O
at	O
least	O
4	O
cycles	O
.	O
</s>
<s>
This	O
performs	O
a	O
read	O
from	O
I/O	B-General_Concept
space	O
.	O
</s>
<s>
All	O
32	O
bits	O
of	O
the	O
read	O
address	O
are	O
provided	O
,	O
so	O
that	O
a	O
device	O
may	O
(	O
for	O
compatibility	O
reasons	O
)	O
implement	O
less	O
than	O
4	O
bytes	B-Application
worth	O
of	O
I/O	B-General_Concept
registers	O
.	O
</s>
<s>
If	O
the	O
byte	B-Application
enables	O
request	O
data	O
not	O
within	O
the	O
address	B-General_Concept
range	I-General_Concept
supported	O
by	O
the	O
PCI	B-Protocol
device	O
(	O
e.g.	O
</s>
<s>
a	O
4-byte	O
read	O
from	O
a	O
device	O
which	O
only	O
supports	O
2	O
bytes	B-Application
of	O
I/O	B-Architecture
address	I-Architecture
space	O
)	O
,	O
it	O
must	O
be	O
terminated	O
with	O
a	O
target	O
abort	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
standard	O
is	O
discouraging	O
the	O
use	O
of	O
I/O	B-General_Concept
space	O
in	O
new	O
devices	O
,	O
preferring	O
that	O
as	O
much	O
as	O
possible	O
be	O
done	O
through	O
main	O
memory	O
mapping	O
.	O
</s>
<s>
This	O
performs	O
a	O
write	O
to	O
I/O	B-General_Concept
space	O
.	O
</s>
<s>
A	O
PCI	B-Protocol
device	O
must	O
not	O
respond	O
to	O
an	O
address	O
cycle	O
with	O
these	O
command	O
codes	O
.	O
</s>
<s>
Because	O
the	O
smallest	O
memory	O
space	O
a	O
PCI	B-Protocol
device	O
is	O
permitted	O
to	O
implement	O
is	O
16	O
bytes	B-Application
,	O
the	O
two	O
least	O
significant	O
bits	O
of	O
the	O
address	O
are	O
not	O
needed	O
during	O
the	O
address	O
phase	O
;	O
equivalent	O
information	O
will	O
arrive	O
during	O
the	O
data	O
phases	O
in	O
the	O
form	O
of	O
byte	B-Application
select	O
signals	O
.	O
</s>
<s>
If	O
a	O
memory	O
space	O
is	O
marked	O
as	O
"	O
prefetchable	O
"	O
,	O
then	O
the	O
target	O
device	O
must	O
ignore	O
the	O
byte	B-Application
select	O
signals	O
on	O
a	O
memory	O
read	O
and	O
always	O
return	O
32	O
valid	O
bits	O
.	O
</s>
<s>
The	O
byte	B-Application
select	O
signals	O
are	O
more	O
important	O
in	O
a	O
write	O
,	O
as	O
unselected	O
bytes	B-Application
must	O
not	O
be	O
written	O
to	O
memory	O
.	O
</s>
<s>
Generally	O
,	O
PCI	B-Protocol
writes	O
are	O
faster	O
than	O
PCI	B-Protocol
reads	O
,	O
because	O
a	O
device	O
may	O
buffer	O
the	O
incoming	O
write	O
data	O
and	O
release	O
the	O
bus	B-General_Concept
faster	O
.	O
</s>
<s>
A	O
PCI	B-Protocol
device	O
must	O
not	O
respond	O
to	O
an	O
address	O
cycle	O
with	O
these	O
command	O
codes	O
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
an	O
I/O	B-General_Concept
read	O
,	O
but	O
reads	O
from	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
.	O
</s>
<s>
Burst	O
reads	O
(	O
using	O
linear	O
incrementing	O
)	O
are	O
permitted	O
in	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
.	O
</s>
<s>
Unlike	O
I/O	B-General_Concept
space	O
,	O
standard	O
PCI	B-Protocol
configuration	O
registers	O
are	O
defined	O
so	O
that	O
reads	O
never	O
disturb	O
the	O
state	O
of	O
the	O
device	O
.	O
</s>
<s>
It	O
is	O
possible	O
for	O
a	O
device	O
to	O
have	O
configuration	O
space	O
registers	O
beyond	O
the	O
standard	O
64	B-Device
bytes	B-Application
which	O
have	O
read	O
side	O
effects	O
,	O
but	O
this	O
is	O
rare	O
.	O
</s>
<s>
Thus	O
,	O
it	O
is	O
best	O
to	O
avoid	O
them	O
during	O
routine	O
operation	O
of	O
a	O
PCI	B-Protocol
device	O
.	O
</s>
<s>
This	O
command	O
is	O
identical	O
to	O
a	O
generic	O
memory	O
read	O
,	O
but	O
includes	O
the	O
hint	O
that	O
a	O
long	O
read	O
burst	O
will	O
continue	O
beyond	O
the	O
end	O
of	O
the	O
current	O
cache	B-General_Concept
line	O
,	O
and	O
the	O
target	O
should	O
internally	O
prefetch	O
a	O
large	O
amount	O
of	O
data	O
.	O
</s>
<s>
PCI	B-Protocol
targets	O
that	O
do	O
not	O
support	O
64-bit	B-Device
addressing	O
may	O
simply	O
treat	O
this	O
as	O
another	O
reserved	O
command	O
code	O
and	O
not	O
respond	O
to	O
it	O
.	O
</s>
<s>
This	O
command	O
is	O
identical	O
to	O
a	O
generic	O
memory	O
read	O
,	O
but	O
includes	O
the	O
hint	O
that	O
the	O
read	O
will	O
continue	O
to	O
the	O
end	O
of	O
the	O
cache	B-General_Concept
line	O
.	O
</s>
<s>
This	O
command	O
is	O
identical	O
to	O
a	O
generic	O
memory	O
write	O
,	O
but	O
comes	O
with	O
the	O
guarantee	O
that	O
one	O
or	O
more	O
whole	O
cache	B-General_Concept
lines	O
will	O
be	O
written	O
,	O
with	O
all	O
byte	B-Application
selects	O
enabled	O
.	O
</s>
<s>
This	O
is	O
an	O
optimization	O
for	O
write-back	O
caches	B-General_Concept
snooping	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
Normally	O
,	O
a	O
write-back	O
cache	B-General_Concept
holding	O
dirty	O
data	O
must	O
interrupt	B-Application
the	O
write	O
operation	O
long	O
enough	O
to	O
write	O
its	O
own	O
dirty	O
data	O
first	O
.	O
</s>
<s>
If	O
the	O
write	O
is	O
performed	O
using	O
this	O
command	O
,	O
the	O
data	O
to	O
be	O
written	O
back	O
is	O
guaranteed	O
to	O
be	O
irrelevant	O
,	O
and	O
may	O
simply	O
be	O
invalidated	O
in	O
the	O
write-back	O
cache	B-General_Concept
.	O
</s>
<s>
This	O
optimization	O
only	O
affects	O
the	O
snooping	O
cache	B-General_Concept
,	O
and	O
makes	O
no	O
difference	O
to	O
the	O
target	O
,	O
which	O
may	O
treat	O
this	O
as	O
a	O
synonym	O
for	O
the	O
memory	O
write	O
command	O
.	O
</s>
<s>
Soon	O
after	O
promulgation	O
of	O
the	O
PCI	B-Protocol
specification	O
,	O
it	O
was	O
discovered	O
that	O
lengthy	O
transactions	O
by	O
some	O
devices	O
,	O
due	O
to	O
slow	O
acknowledgments	O
,	O
long	O
data	O
bursts	O
,	O
or	O
some	O
combination	O
,	O
could	O
cause	O
buffer	O
underrun	O
or	O
overrun	O
in	O
other	O
devices	O
.	O
</s>
<s>
This	O
is	O
usually	O
the	O
next	O
data	O
phase	O
,	O
but	O
Memory	O
Write	O
and	O
Invalidate	O
transactions	O
must	O
continue	O
to	O
the	O
end	O
of	O
the	O
cache	B-General_Concept
line	O
.	O
</s>
<s>
A	O
device	O
may	O
be	O
the	O
target	O
of	O
other	O
transactions	O
while	O
completing	O
one	O
delayed	O
transaction	O
;	O
it	O
must	O
remember	O
the	O
transaction	O
type	O
,	O
address	O
,	O
byte	B-Application
selects	O
and	O
(	O
if	O
a	O
write	O
)	O
data	O
value	O
,	O
and	O
only	O
complete	O
the	O
correct	O
transaction	O
.	O
</s>
<s>
A	O
target	O
abandons	O
a	O
delayed	O
transaction	O
when	O
a	O
retry	O
succeeds	O
in	O
delivering	O
the	O
buffered	O
result	O
,	O
the	O
bus	B-General_Concept
is	O
reset	O
,	O
or	O
when	O
215	O
=	O
32768	O
clock	O
cycles	O
(	O
approximately	O
1ms	O
)	O
elapse	O
without	O
seeing	O
a	O
retry	O
.	O
</s>
<s>
The	O
latter	O
should	O
never	O
happen	O
in	O
normal	O
operation	O
,	O
but	O
it	O
prevents	O
a	O
deadlock	B-Operating_System
of	O
the	O
whole	O
bus	B-General_Concept
if	O
one	O
initiator	O
is	O
reset	O
or	O
malfunctions	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
standard	O
permits	O
multiple	O
independent	O
PCI	B-Protocol
buses	O
to	O
be	O
connected	O
by	O
bus	B-General_Concept
bridges	O
that	O
will	O
forward	O
operations	O
on	O
one	O
bus	B-General_Concept
to	O
another	O
when	O
required	O
.	O
</s>
<s>
Although	O
PCI	B-Protocol
tends	O
not	O
to	O
use	O
many	O
bus	B-General_Concept
bridges	O
,	O
PCI	B-Protocol
Express	O
systems	O
use	O
many	O
PCI-to-PCI	O
bridge	O
usually	O
called	O
PCI	B-Protocol
Express	O
Root	O
Port	O
;	O
each	O
PCI	B-Protocol
Express	O
slot	O
appears	O
to	O
be	O
a	O
separate	O
bus	B-General_Concept
,	O
connected	O
by	O
a	O
bridge	O
to	O
the	O
others	O
.	O
</s>
<s>
The	O
PCI	B-Device
host	I-Device
bridge	I-Device
(	O
usually	O
northbridge	B-Device
in	O
x86	B-Operating_System
platforms	O
)	O
interconnect	B-General_Concept
between	O
CPU	O
,	O
main	O
memory	O
and	O
PCI	B-Protocol
bus	I-Protocol
.	O
</s>
<s>
Generally	O
,	O
when	O
a	O
bus	B-General_Concept
bridge	O
sees	O
a	O
transaction	O
on	O
one	O
bus	B-General_Concept
that	O
must	O
be	O
forwarded	O
to	O
the	O
other	O
,	O
the	O
original	O
transaction	O
must	O
wait	O
until	O
the	O
forwarded	O
transaction	O
completes	O
before	O
a	O
result	O
is	O
ready	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
standard	O
permits	O
bus	B-General_Concept
bridges	O
to	O
convert	O
multiple	O
bus	B-General_Concept
transactions	O
into	O
one	O
larger	O
transaction	O
under	O
certain	O
situations	O
.	O
</s>
<s>
This	O
can	O
improve	O
the	O
efficiency	O
of	O
the	O
PCI	B-Protocol
bus	I-Protocol
.	O
</s>
<s>
It	O
is	O
permissible	O
to	O
insert	O
extra	O
data	O
phases	O
with	O
all	O
byte	B-Application
enables	O
turned	O
off	O
if	O
the	O
writes	O
are	O
almost	O
consecutive	O
.	O
</s>
<s>
Merging	O
Multiple	O
writes	O
to	O
disjoint	O
portions	O
of	O
the	O
same	O
word	O
may	O
be	O
merged	O
into	O
a	O
single	O
write	O
with	O
multiple	O
byte	B-Application
enables	O
asserted	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
writes	O
that	O
were	O
presented	O
to	O
the	O
bus	B-General_Concept
bridge	O
in	O
a	O
particular	O
order	O
are	O
merged	O
so	O
they	O
occur	O
at	O
the	O
same	O
time	O
when	O
forwarded	O
.	O
</s>
<s>
Collapsing	O
Multiple	O
writes	O
to	O
the	O
same	O
byte	B-Application
or	O
bytes	B-Application
may	O
not	O
be	O
combined	O
,	O
for	O
example	O
,	O
by	O
performing	O
only	O
the	O
second	O
write	O
and	O
skipping	O
the	O
first	O
write	O
that	O
was	O
overwritten	O
.	O
</s>
<s>
This	O
is	O
because	O
the	O
PCI	B-Protocol
specification	O
permits	O
writes	O
to	O
have	O
side	O
effects	O
.	O
</s>
<s>
PCI	B-Protocol
bus	I-Protocol
transactions	O
are	O
controlled	O
by	O
five	O
main	O
control	O
signals	O
,	O
two	O
driven	O
by	O
the	O
initiator	O
of	O
a	O
transaction	O
(	O
FRAME#	O
and	O
IRDY#	O
)	O
,	O
and	O
three	O
driven	O
by	O
the	O
target	O
(	O
DEVSEL#	O
,	O
TRDY#	O
,	O
and	O
STOP#	O
)	O
.	O
</s>
<s>
Pull-up	O
resistors	O
on	O
the	O
motherboard	B-Device
ensure	O
they	O
will	O
remain	O
high	O
(	O
inactive	O
or	O
deasserted	O
)	O
if	O
not	O
driven	O
by	O
any	O
device	O
,	O
but	O
the	O
PCI	B-Protocol
bus	I-Protocol
does	O
not	O
depend	O
on	O
the	O
resistors	O
to	O
change	O
the	O
signal	O
level	O
;	O
all	O
devices	O
drive	O
the	O
signals	O
high	O
for	O
one	O
cycle	O
before	O
ceasing	B-Device
to	I-Device
drive	I-Device
the	O
signals	O
.	O
</s>
<s>
All	O
PCI	B-Protocol
bus	I-Protocol
signals	O
are	O
sampled	O
on	O
the	O
rising	O
edge	O
of	O
the	O
clock	O
.	O
</s>
<s>
Signals	O
nominally	O
change	O
on	O
the	O
falling	O
edge	O
of	O
the	O
clock	O
,	O
giving	O
each	O
PCI	B-Protocol
device	O
approximately	O
one	O
half	O
a	O
clock	O
cycle	O
to	O
decide	O
how	O
to	O
respond	O
to	O
the	O
signals	O
it	O
observed	O
on	O
the	O
rising	O
edge	O
,	O
and	O
one	O
half	O
a	O
clock	O
cycle	O
to	O
transmit	O
its	O
response	O
to	O
the	O
other	O
device	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
requires	O
that	O
every	O
time	O
the	O
device	O
driving	O
a	O
PCI	B-Protocol
bus	I-Protocol
signal	O
changes	O
,	O
one	O
turnaround	O
cycle	O
must	O
elapse	O
between	O
the	O
time	O
the	O
one	O
device	O
stops	O
driving	O
the	O
signal	O
and	O
the	O
other	O
device	O
starts	O
.	O
</s>
<s>
Without	O
this	O
,	O
there	O
might	O
be	O
a	O
period	O
when	O
both	O
devices	O
were	O
driving	O
the	O
signal	O
,	O
which	O
would	O
interfere	O
with	O
bus	B-General_Concept
operation	O
.	O
</s>
<s>
The	O
combination	O
of	O
this	O
turnaround	O
cycle	O
and	O
the	O
requirement	O
to	O
drive	O
a	O
control	O
line	O
high	O
for	O
one	O
cycle	O
before	O
ceasing	B-Device
to	I-Device
drive	I-Device
it	O
means	O
that	O
each	O
of	O
the	O
main	O
control	O
lines	O
must	O
be	O
high	O
for	O
a	O
minimum	O
of	O
two	O
cycles	O
when	O
changing	O
owners	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
protocol	O
is	O
designed	O
so	O
this	O
is	O
rarely	O
a	O
limitation	O
;	O
only	O
in	O
a	O
few	O
special	O
cases	O
(	O
notably	O
fast	O
back-to-back	O
transactions	O
)	O
is	O
it	O
necessary	O
to	O
insert	O
additional	O
delay	O
to	O
meet	O
this	O
requirement	O
.	O
</s>
<s>
Any	O
device	O
on	O
a	O
PCI	B-Protocol
bus	I-Protocol
that	O
is	O
capable	O
of	O
acting	O
as	O
a	O
bus	B-Architecture
master	I-Architecture
may	O
initiate	O
a	O
transaction	O
with	O
any	O
other	O
device	O
.	O
</s>
<s>
To	O
ensure	O
that	O
only	O
one	O
transaction	O
is	O
initiated	O
at	O
a	O
time	O
,	O
each	O
master	O
must	O
first	O
wait	O
for	O
a	O
bus	B-General_Concept
grant	O
signal	O
,	O
GNT#	O
,	O
from	O
an	O
arbiter	O
located	O
on	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Each	O
device	O
has	O
a	O
separate	O
request	O
line	O
REQ#	O
that	O
requests	O
the	O
bus	B-General_Concept
,	O
but	O
the	O
arbiter	O
may	O
"	O
park	O
"	O
the	O
bus	B-General_Concept
grant	O
signal	O
at	O
any	O
device	O
if	O
there	O
are	O
no	O
current	O
requests	O
.	O
</s>
<s>
During	O
a	O
transaction	O
,	O
either	O
FRAME#	O
or	O
IRDY#	O
or	O
both	O
are	O
asserted	O
;	O
when	O
both	O
are	O
deasserted	O
,	O
the	O
bus	B-General_Concept
is	O
idle	O
.	O
</s>
<s>
A	O
device	O
may	O
initiate	O
a	O
transaction	O
at	O
any	O
time	O
that	O
GNT#	O
is	O
asserted	O
and	O
the	O
bus	B-General_Concept
is	O
idle	O
.	O
</s>
<s>
A	O
PCI	B-Protocol
bus	I-Protocol
transaction	O
begins	O
with	O
an	O
address	O
phase	O
.	O
</s>
<s>
The	O
initiator	O
,	O
seeing	O
that	O
it	O
has	O
GNT#	O
and	O
the	O
bus	B-General_Concept
is	O
idle	O
,	O
drives	O
the	O
target	O
address	O
onto	O
the	O
AD[31:0]	O
lines	O
,	O
the	O
associated	O
command	O
(	O
e.g.	O
</s>
<s>
memory	O
read	O
,	O
or	O
I/O	B-General_Concept
write	O
)	O
on	O
the	O
C/BE[3:0]#	O
lines	O
,	O
and	O
pulls	O
FRAME#	O
low	O
.	O
</s>
<s>
(	O
Actually	O
,	O
the	O
time	O
to	O
respond	O
is	O
2.5	O
cycles	O
,	O
since	O
PCI	B-Protocol
devices	O
must	O
transmit	O
all	O
signals	O
half	O
a	O
cycle	O
early	O
so	O
that	O
they	O
can	O
be	O
received	O
three	O
cycles	O
later	O
.	O
)	O
</s>
<s>
Note	O
that	O
a	O
device	O
must	O
latch	B-General_Concept
the	O
address	O
on	O
the	O
first	O
cycle	O
;	O
the	O
initiator	O
is	O
required	O
to	O
remove	O
the	O
address	O
and	O
command	O
from	O
the	O
bus	B-General_Concept
on	O
the	O
following	O
cycle	O
,	O
even	O
before	O
receiving	O
a	O
DEVSEL#	O
response	O
.	O
</s>
<s>
On	O
the	O
fifth	O
cycle	O
of	O
the	O
address	O
phase	O
(	O
or	O
earlier	O
if	O
all	O
other	O
devices	O
have	O
medium	O
DEVSEL	O
or	O
faster	O
)	O
,	O
a	O
catch-all	O
"	O
subtractive	O
decoding	O
"	O
is	O
allowed	O
for	O
some	O
address	B-General_Concept
ranges	I-General_Concept
.	O
</s>
<s>
This	O
is	O
commonly	O
used	O
by	O
an	O
ISA	B-Architecture
bus	I-Architecture
bridge	O
for	O
addresses	O
within	O
its	O
range	O
(	O
24	O
bits	O
for	O
memory	O
and	O
16	O
bits	O
for	O
I/O	B-General_Concept
)	O
.	O
</s>
<s>
This	O
is	O
known	O
as	O
master	O
abort	O
termination	O
and	O
it	O
is	O
customary	O
for	O
PCI	B-Protocol
bus	I-Protocol
bridges	O
to	O
return	O
all-ones	O
data	O
(	O
0xFFFFFFFF	O
)	O
in	O
this	O
case	O
.	O
</s>
<s>
PCI	B-Protocol
devices	O
therefore	O
are	O
generally	O
designed	O
to	O
avoid	O
using	O
the	O
all-ones	O
value	O
in	O
important	O
status	O
registers	O
,	O
so	O
that	O
such	O
an	O
error	O
can	O
be	O
easily	O
detected	O
by	O
software	O
.	O
</s>
<s>
Targets	O
latch	B-General_Concept
the	O
address	O
and	O
begin	O
decoding	O
it	O
.	O
</s>
<s>
To	O
allow	O
64-bit	B-Device
addressing	O
,	O
a	O
master	O
will	O
present	O
the	O
address	O
over	O
two	O
consecutive	O
cycles	O
.	O
</s>
<s>
Dual-address	O
cycles	O
are	O
forbidden	O
if	O
the	O
high-order	O
address	O
bits	O
are	O
zero	O
,	O
so	O
devices	O
which	O
do	O
not	O
support	O
64-bit	B-Device
addressing	O
can	O
simply	O
not	O
respond	O
to	O
dual	O
cycle	O
commands	O
.	O
</s>
<s>
Addresses	O
for	O
PCI	B-Architecture
configuration	I-Architecture
space	I-Architecture
access	O
are	O
decoded	O
specially	O
.	O
</s>
<s>
For	O
these	O
,	O
the	O
low-order	O
address	O
lines	O
specify	O
the	O
offset	O
of	O
the	O
desired	O
PCI	B-Protocol
configuration	O
register	O
,	O
and	O
the	O
high-order	O
address	O
lines	O
are	O
ignored	O
.	O
</s>
<s>
In	O
all	O
cases	O
,	O
the	O
initiator	O
drives	O
active-low	O
byte	B-Application
select	O
signals	O
on	O
the	O
C/BE[3:0]#	O
lines	O
,	O
but	O
the	O
data	O
on	O
the	O
AD[31:0]	O
may	O
be	O
driven	O
by	O
the	O
initiator	O
(	O
in	O
case	O
of	O
writes	O
)	O
or	O
target	O
(	O
in	O
case	O
of	O
reads	O
)	O
.	O
</s>
<s>
During	O
data	O
phases	O
,	O
the	O
C/BE[3:0]#	O
lines	O
are	O
interpreted	O
as	O
active-low	O
byte	B-Application
enables	O
.	O
</s>
<s>
In	O
case	O
of	O
a	O
write	O
,	O
the	O
asserted	O
signals	O
indicate	O
which	O
of	O
the	O
four	O
bytes	B-Application
on	O
the	O
AD	O
bus	B-General_Concept
are	O
to	O
be	O
written	O
to	O
the	O
addressed	O
location	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
read	O
,	O
they	O
indicate	O
which	O
bytes	B-Application
the	O
initiator	O
is	O
interested	O
in	O
.	O
</s>
<s>
For	O
reads	O
,	O
it	O
is	O
always	O
legal	O
to	O
ignore	O
the	O
byte	B-Application
enable	O
signals	O
and	O
simply	O
return	O
all	O
32	O
bits	O
;	O
cacheable	O
memory	O
resources	O
are	O
required	O
to	O
always	O
return	O
32	O
valid	O
bits	O
.	O
</s>
<s>
The	O
byte	B-Application
enables	O
are	O
mainly	O
useful	O
for	O
I/O	B-General_Concept
space	O
accesses	O
where	O
reads	O
have	O
side	O
effects	O
.	O
</s>
<s>
A	O
data	O
phase	O
with	O
all	O
four	O
C/BE	O
#	O
lines	O
deasserted	O
is	O
explicitly	O
permitted	O
by	O
the	O
PCI	B-Protocol
standard	O
,	O
and	O
must	O
have	O
no	O
effect	O
on	O
the	O
target	O
other	O
than	O
to	O
advance	O
the	O
address	O
in	O
the	O
burst	O
access	O
in	O
progress	O
.	O
</s>
<s>
Whichever	O
side	O
is	O
providing	O
the	O
data	O
must	O
drive	O
it	O
on	O
the	O
AD	O
bus	B-General_Concept
before	O
asserting	O
its	O
ready	O
signal	O
.	O
</s>
<s>
The	O
data	O
recipient	O
must	O
latch	B-General_Concept
the	O
AD	O
bus	B-General_Concept
each	O
cycle	O
until	O
it	O
sees	O
both	O
IRDY#	O
and	O
TRDY#	O
asserted	O
,	O
which	O
marks	O
the	O
end	O
of	O
the	O
current	O
data	O
phase	O
and	O
indicates	O
that	O
the	O
just-latched	O
data	O
is	O
the	O
word	O
to	O
be	O
transferred	O
.	O
</s>
<s>
To	O
maintain	O
full	O
burst	O
speed	O
,	O
the	O
data	O
sender	O
then	O
has	O
half	O
a	O
clock	O
cycle	O
after	O
seeing	O
both	O
IRDY#	O
and	O
TRDY#	O
asserted	O
to	O
drive	O
the	O
next	O
word	O
onto	O
the	O
AD	O
bus	B-General_Concept
.	O
</s>
<s>
In	O
case	O
of	O
a	O
read	O
,	O
clock	O
2	O
is	O
reserved	O
for	O
turning	O
around	O
the	O
AD	O
bus	B-General_Concept
,	O
so	O
the	O
target	O
is	O
not	O
permitted	O
to	O
drive	O
data	O
on	O
the	O
bus	B-General_Concept
even	O
if	O
it	O
is	O
capable	O
of	O
fast	O
DEVSEL	O
.	O
</s>
<s>
This	O
cycle	O
is	O
,	O
however	O
,	O
reserved	O
for	O
AD	O
bus	B-General_Concept
turnaround	O
.	O
</s>
<s>
Thus	O
,	O
a	O
target	O
may	O
not	O
drive	O
the	O
AD	O
bus	B-General_Concept
(	O
and	O
thus	O
may	O
not	O
assert	O
TRDY#	O
)	O
on	O
the	O
second	O
cycle	O
of	O
a	O
transaction	O
.	O
</s>
<s>
Simple	O
PCI	B-Protocol
devices	O
that	O
do	O
not	O
support	O
multi-word	O
bursts	O
will	O
always	O
request	O
this	O
immediately	O
.	O
</s>
<s>
The	O
cycle	O
after	O
the	O
target	O
asserts	O
TRDY#	O
,	O
the	O
final	O
data	O
transfer	O
is	O
complete	O
,	O
both	O
sides	O
deassert	O
their	O
respective	O
RDY#	O
signals	O
,	O
and	O
the	O
bus	B-General_Concept
is	O
idle	O
again	O
.	O
</s>
<s>
This	O
is	O
to	O
ensure	O
that	O
bus	B-General_Concept
turnaround	O
timing	O
rules	O
are	O
obeyed	O
on	O
the	O
FRAME#	O
line	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
target	O
that	O
does	O
not	O
support	O
burst	B-Architecture
transfers	I-Architecture
will	O
always	O
do	O
this	O
to	O
force	O
single-word	O
PCI	B-Protocol
transactions	O
.	O
</s>
<s>
A	O
Disconnect	O
without	O
data	O
before	O
transferring	O
any	O
data	O
is	O
a	O
retry	O
,	O
and	O
unlike	O
other	O
PCI	B-Protocol
transactions	O
,	O
PCI	B-Protocol
initiators	O
are	O
required	O
to	O
pause	O
slightly	O
before	O
continuing	O
the	O
operation	O
.	O
</s>
<s>
See	O
the	O
PCI	B-Protocol
specification	O
for	O
details	O
.	O
</s>
<s>
The	O
initiator	O
may	O
not	O
retry	O
,	O
and	O
typically	O
treats	O
it	O
as	O
a	O
bus	B-General_Concept
error	I-General_Concept
.	O
</s>
<s>
If	O
the	O
initiator	O
ends	O
the	O
burst	O
at	O
the	O
same	O
time	O
as	O
the	O
target	O
requests	O
disconnection	O
,	O
there	O
is	O
no	O
additional	O
bus	B-General_Concept
cycle	O
.	O
</s>
<s>
Some	O
of	O
these	O
orders	O
depend	O
on	O
the	O
cache	B-General_Concept
line	O
size	O
,	O
which	O
is	O
configurable	O
on	O
all	O
PCI	B-Protocol
devices	O
.	O
</s>
<s>
If	O
the	O
starting	O
offset	O
within	O
the	O
cache	B-General_Concept
line	O
is	O
zero	O
,	O
all	O
of	O
these	O
modes	O
reduce	O
to	O
the	O
same	O
order	O
.	O
</s>
<s>
Cache	B-General_Concept
line	O
toggle	O
and	O
cache	B-General_Concept
line	O
wrap	O
modes	O
are	O
two	O
forms	O
of	O
critical-word-first	O
cache	B-General_Concept
line	O
fetching	O
.	O
</s>
<s>
This	O
is	O
the	O
native	O
order	O
for	O
Intel	B-General_Concept
486	I-General_Concept
and	O
Pentium	B-General_Concept
processors	O
.	O
</s>
<s>
It	O
has	O
the	O
advantage	O
that	O
it	O
is	O
not	O
necessary	O
to	O
know	O
the	O
cache	B-General_Concept
line	O
size	O
to	O
implement	O
it	O
.	O
</s>
<s>
PCI	B-Protocol
version	O
2.1	O
obsoleted	O
toggle	O
mode	O
and	O
added	O
the	O
cache	B-General_Concept
line	O
wrap	O
mode	O
,	O
where	O
fetching	O
proceeds	O
linearly	O
,	O
wrapping	O
around	O
at	O
the	O
end	O
of	O
each	O
cache	B-General_Concept
line	O
.	O
</s>
<s>
When	O
one	O
cache	B-General_Concept
line	O
is	O
completely	O
fetched	O
,	O
fetching	O
jumps	O
to	O
the	O
starting	O
offset	O
in	O
the	O
next	O
cache	B-General_Concept
line	O
.	O
</s>
<s>
Note	O
that	O
most	O
PCI	B-Protocol
devices	O
only	O
support	O
a	O
limited	O
range	O
of	O
typical	O
cache	B-General_Concept
line	O
sizes	O
;	O
if	O
the	O
cache	B-General_Concept
line	O
size	O
is	O
programmed	O
to	O
an	O
unexpected	O
value	O
,	O
they	O
force	O
single-word	O
access	O
.	O
</s>
<s>
PCI	B-Protocol
also	O
supports	O
burst	O
access	O
to	O
I/O	B-General_Concept
and	O
configuration	O
space	O
,	O
but	O
only	O
linear	O
mode	O
is	O
supported	O
.	O
</s>
<s>
On	O
clock	O
edge	O
1	O
,	O
the	O
initiator	O
starts	O
a	O
transaction	O
by	O
driving	O
an	O
address	O
,	O
command	O
,	O
and	O
asserting	O
FRAME#	O
The	O
other	O
signals	O
are	O
idle	O
(	O
indicated	O
by	O
^^^	O
)	O
,	O
pulled	O
high	O
by	O
the	O
motherboard	B-Device
's	O
pull-up	O
resistors	O
.	O
</s>
<s>
On	O
clock	O
edge	O
6	O
,	O
the	O
AD	O
bus	B-General_Concept
and	O
FRAME#	O
are	O
undriven	O
(	O
turnaround	O
cycle	O
)	O
and	O
the	O
other	O
control	O
lines	O
are	O
driven	O
high	O
for	O
1	O
cycle	O
.	O
</s>
<s>
The	O
equivalent	O
read	O
burst	O
takes	O
one	O
more	O
cycle	O
,	O
because	O
the	O
target	O
must	O
wait	O
1	O
cycle	O
for	O
the	O
AD	O
bus	B-General_Concept
to	O
turn	O
around	O
before	O
it	O
may	O
assert	O
TRDY#	O
:	O
</s>
<s>
The	O
PCI	B-Protocol
bus	I-Protocol
detects	O
parity	O
errors	O
,	O
but	O
does	O
not	O
attempt	O
to	O
correct	O
them	O
by	O
retrying	O
operations	O
;	O
it	O
is	O
purely	O
a	O
failure	O
indication	O
.	O
</s>
<s>
Due	O
to	O
this	O
,	O
there	O
is	O
no	O
need	O
to	O
detect	O
the	O
parity	O
error	O
before	O
it	O
has	O
happened	O
,	O
and	O
the	O
PCI	B-Protocol
bus	I-Protocol
actually	O
detects	O
it	O
a	O
few	O
cycles	O
later	O
.	O
</s>
<s>
All	O
access	O
rules	O
and	O
turnaround	O
cycles	O
for	O
the	O
AD	O
bus	B-General_Concept
apply	O
to	O
the	O
PAR	O
line	O
,	O
just	O
one	O
cycle	O
later	O
.	O
</s>
<s>
The	O
device	O
listening	O
on	O
the	O
AD	O
bus	B-General_Concept
checks	O
the	O
received	O
parity	O
and	O
asserts	O
the	O
PERR#	O
(	O
parity	O
error	O
)	O
line	O
one	O
cycle	O
after	O
that	O
.	O
</s>
<s>
This	O
generally	O
generates	O
a	O
processor	O
interrupt	B-Application
,	O
and	O
the	O
processor	O
can	O
search	O
the	O
PCI	B-Protocol
bus	I-Protocol
for	O
the	O
device	O
which	O
detected	O
the	O
error	O
.	O
</s>
<s>
Even	O
when	O
some	O
bytes	B-Application
are	O
masked	O
by	O
the	O
C/BE	O
#	O
lines	O
and	O
not	O
in	O
use	O
,	O
they	O
must	O
still	O
have	O
some	O
defined	O
value	O
,	O
and	O
this	O
value	O
must	O
be	O
used	O
to	O
compute	O
the	O
parity	O
.	O
</s>
<s>
Due	O
to	O
the	O
need	O
for	O
a	O
turnaround	O
cycle	O
between	O
different	O
devices	O
driving	O
PCI	B-Protocol
bus	I-Protocol
signals	O
,	O
in	O
general	O
it	O
is	O
necessary	O
to	O
have	O
an	O
idle	O
cycle	O
between	O
PCI	B-Protocol
bus	I-Protocol
transactions	O
.	O
</s>
<s>
the	O
initiator	O
still	O
has	O
permission	O
(	O
from	O
its	O
GNT#	O
input	O
)	O
to	O
use	O
the	O
PCI	B-Protocol
bus	I-Protocol
.	O
</s>
<s>
All	O
PCI	B-Protocol
targets	O
must	O
support	O
this	O
.	O
</s>
<s>
Targets	O
which	O
have	O
this	O
ability	O
indicate	O
it	O
by	O
a	O
special	O
bit	O
in	O
a	O
PCI	B-Protocol
configuration	O
register	O
,	O
and	O
if	O
all	O
targets	O
on	O
a	O
bus	B-General_Concept
have	O
it	O
,	O
all	O
initiators	O
may	O
use	O
back-to-back	O
transfers	O
freely	O
.	O
</s>
<s>
A	O
subtractive	O
decoding	O
bus	B-General_Concept
bridge	O
must	O
know	O
to	O
expect	O
this	O
extra	O
delay	O
in	O
the	O
event	O
of	O
back-to-back	O
cycles	O
,	O
to	O
advertise	O
back-to-back	O
support	O
.	O
</s>
<s>
Starting	O
from	O
revision	O
2.1	O
,	O
the	O
PCI	B-Protocol
specification	O
includes	O
optional	O
64-bit	B-Device
support	I-Device
.	O
</s>
<s>
This	O
is	O
provided	O
via	O
an	O
extended	O
connector	O
which	O
provides	O
the	O
64-bit	B-Device
bus	B-General_Concept
extensions	O
AD[63:32],	O
C/BE[7:4]#,	O
and	O
PAR64	O
,	O
and	O
a	O
number	O
of	O
additional	O
power	O
and	O
ground	O
pins	O
.	O
</s>
<s>
The	O
64-bit	B-Device
PCI	B-Protocol
connector	O
can	O
be	O
distinguished	O
from	O
a	O
32-bit	O
connector	O
by	O
the	O
additional	O
64-bit	B-Device
segment	O
.	O
</s>
<s>
Memory	O
transactions	O
between	O
64-bit	B-Device
devices	O
may	O
use	O
all	O
64bits	B-Device
to	O
double	O
the	O
data	O
transfer	O
rate	O
.	O
</s>
<s>
Non-memory	O
transactions	O
(	O
including	O
configuration	O
and	O
I/O	B-General_Concept
space	O
accesses	O
)	O
may	O
not	O
use	O
the	O
64-bit	B-Device
extension	O
.	O
</s>
<s>
During	O
a	O
64-bit	B-Device
burst	O
,	O
burst	O
addressing	O
works	O
just	O
as	O
in	O
a	O
32-bit	O
transfer	O
,	O
but	O
the	O
address	O
is	O
incremented	O
twice	O
per	O
data	O
phase	O
.	O
</s>
<s>
The	O
starting	O
address	O
must	O
be	O
64-bit	B-Device
aligned	O
;	O
i.e.	O
</s>
<s>
The	O
data	O
corresponding	O
to	O
the	O
intervening	O
addresses	O
(	O
with	O
AD2	O
=	O
1	O
)	O
is	O
carried	O
on	O
the	O
upper	O
half	O
of	O
the	O
AD	O
bus	B-General_Concept
.	O
</s>
<s>
To	O
initiate	O
a	O
64-bit	B-Device
transaction	O
,	O
the	O
initiator	O
drives	O
the	O
starting	O
address	O
on	O
the	O
AD	O
bus	B-General_Concept
and	O
asserts	O
REQ64#	O
at	O
the	O
same	O
time	O
as	O
FRAME#	O
.	O
</s>
<s>
If	O
the	O
selected	O
target	O
can	O
support	O
a	O
64-bit	B-Device
transfer	O
for	O
this	O
transaction	O
,	O
it	O
replies	O
by	O
asserting	O
ACK64#	O
at	O
the	O
same	O
time	O
as	O
DEVSEL#	O
.	O
</s>
<s>
Note	O
that	O
a	O
target	O
may	O
decide	O
on	O
a	O
per-transaction	O
basis	O
whether	O
to	O
allow	O
a	O
64-bit	B-Device
transfer	O
.	O
</s>
<s>
If	O
REQ64#	O
is	O
asserted	O
during	O
the	O
address	O
phase	O
,	O
the	O
initiator	O
also	O
drives	O
the	O
high	O
32	O
bits	O
of	O
the	O
address	O
and	O
a	O
copy	O
of	O
the	O
bus	B-General_Concept
command	O
on	O
the	O
high	O
half	O
of	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
If	O
the	O
address	O
requires	O
64	B-Device
bits	I-Device
,	O
a	O
dual	O
address	O
cycle	O
is	O
still	O
required	O
,	O
but	O
the	O
high	O
half	O
of	O
the	O
bus	B-General_Concept
carries	O
the	O
upper	O
half	O
of	O
the	O
address	O
and	O
the	O
final	O
command	O
code	O
during	O
both	O
address	O
phase	O
cycles	O
;	O
this	O
allows	O
a	O
64-bit	B-Device
target	O
to	O
see	O
the	O
entire	O
address	O
and	O
begin	O
responding	O
earlier	O
.	O
</s>
<s>
The	O
data	O
which	O
would	O
have	O
been	O
transferred	O
on	O
the	O
upper	O
half	O
of	O
the	O
bus	B-General_Concept
during	O
the	O
first	O
data	O
phase	O
is	O
instead	O
transferred	O
during	O
the	O
second	O
data	O
phase	O
.	O
</s>
<s>
Typically	O
,	O
the	O
initiator	O
drives	O
all	O
64	B-Device
bits	I-Device
of	O
data	O
before	O
seeing	O
DEVSEL#	O
.	O
</s>
<s>
If	O
ACK64#	O
is	O
missing	O
,	O
it	O
may	O
cease	O
driving	O
the	O
upper	O
half	O
of	O
the	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
PCI	B-Protocol
originally	O
included	O
optional	O
support	O
for	O
write-back	O
cache	B-General_Concept
coherence	I-General_Concept
.	O
</s>
<s>
This	O
required	O
support	O
by	O
cacheable	O
memory	O
targets	O
,	O
which	O
would	O
listen	O
to	O
two	O
pins	O
from	O
the	O
cache	B-General_Concept
on	O
the	O
bus	B-General_Concept
,	O
SDONE	O
(	O
snoop	O
done	O
)	O
and	O
SBO#	O
(	O
snoop	O
backoff	O
)	O
.	O
</s>
<s>
Because	O
this	O
was	O
rarely	O
implemented	O
in	O
practice	O
,	O
it	O
was	O
deleted	O
from	O
revision	O
2.2	O
of	O
the	O
PCI	B-Protocol
specification	O
,	O
and	O
the	O
pins	O
re-used	O
for	O
SMBus	B-Algorithm
access	O
in	O
revision	O
2.3	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
would	O
watch	O
all	O
memory	O
accesses	O
,	O
without	O
asserting	O
DEVSEL#	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
write	O
to	O
data	O
that	O
was	O
clean	O
in	O
the	O
cache	B-General_Concept
,	O
the	O
cache	B-General_Concept
would	O
only	O
have	O
to	O
invalidate	O
its	O
copy	O
,	O
and	O
would	O
assert	O
SDONE	O
as	O
soon	O
as	O
this	O
was	O
established	O
.	O
</s>
<s>
However	O
,	O
if	O
the	O
cache	B-General_Concept
contained	O
dirty	O
data	O
,	O
the	O
cache	B-General_Concept
would	O
have	O
to	O
write	O
it	O
back	O
before	O
the	O
access	O
could	O
proceed	O
.	O
</s>
<s>
In	O
the	O
meantime	O
,	O
the	O
cache	B-General_Concept
would	O
arbitrate	O
for	O
the	O
bus	B-General_Concept
and	O
write	O
its	O
data	O
back	O
to	O
memory	O
.	O
</s>
<s>
Targets	O
supporting	O
cache	B-General_Concept
coherency	I-General_Concept
are	O
also	O
required	O
to	O
terminate	O
bursts	O
before	O
they	O
cross	O
cache	B-General_Concept
lines	O
.	O
</s>
<s>
When	O
developing	O
and/or	O
troubleshooting	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
examination	O
of	O
hardware	B-Architecture
signals	O
can	O
be	O
very	O
important	O
.	O
</s>
<s>
Logic	O
analyzers	O
and	O
bus	B-General_Concept
analyzers	O
are	O
tools	O
which	O
collect	O
,	O
analyze	O
,	O
and	O
decode	O
signals	O
for	O
users	O
to	O
view	O
in	O
useful	O
ways	O
.	O
</s>
