<s>
The	O
Pentium	B-Device
Pro	I-Device
is	O
a	O
sixth-generation	O
x86	B-Operating_System
microprocessor	I-Operating_System
developed	O
and	O
manufactured	O
by	O
Intel	O
and	O
introduced	O
on	O
November	O
1	O
,	O
1995	O
.	O
</s>
<s>
It	O
introduced	O
the	O
P6	B-Device
microarchitecture	I-Device
(	O
sometimes	O
termed	O
i686	B-Device
)	O
and	O
was	O
originally	O
intended	O
to	O
replace	O
the	O
original	B-General_Concept
Pentium	I-General_Concept
in	O
a	O
full	O
range	O
of	O
applications	O
.	O
</s>
<s>
While	O
the	O
Pentium	B-General_Concept
and	O
Pentium	B-General_Concept
MMX	B-Architecture
had	O
3.1	O
and	O
4.5million	O
transistors	B-Application
,	O
respectively	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
contained	O
5.5million	O
transistors	B-Application
.	O
</s>
<s>
Later	O
,	O
it	O
was	O
reduced	O
to	O
a	O
more	O
narrow	O
role	O
as	O
a	O
server	O
and	O
high-end	O
desktop	O
processor	O
and	O
was	O
used	O
in	O
supercomputers	B-Architecture
like	O
ASCI	B-Device
Red	I-Device
,	O
the	O
first	O
computer	O
to	O
reach	O
the	O
trillion	O
floating	O
point	O
operations	O
per	O
second	O
(	O
teraFLOPS	O
)	O
performance	O
mark	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
was	O
capable	O
of	O
both	O
dual	O
-	O
and	O
quad-processor	O
configurations	O
.	O
</s>
<s>
It	O
only	O
came	O
in	O
one	O
form	O
factor	O
,	O
the	O
relatively	O
large	O
rectangular	O
Socket	B-Device
8	I-Device
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
was	O
succeeded	O
by	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
in	O
1998	O
.	O
</s>
<s>
The	O
lead	O
architect	O
of	O
Pentium	B-Device
Pro	I-Device
was	O
Fred	O
Pollack	O
who	O
was	O
specialized	O
in	O
superscalarity	O
and	O
had	O
also	O
worked	O
as	O
the	O
lead	O
engineer	O
of	O
the	O
Intel	B-Device
iAPX	I-Device
432	I-Device
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
incorporated	O
a	O
new	O
microarchitecture	B-General_Concept
,	O
different	O
from	O
the	O
Pentium	B-General_Concept
's	O
P5	B-General_Concept
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
(	O
P6	B-Device
)	O
implemented	O
many	O
radical	O
architectural	O
differences	O
mirroring	O
other	O
contemporary	O
x86	B-Operating_System
designs	O
such	O
as	O
the	O
NexGen	O
Nx586	B-Device
and	O
Cyrix	B-General_Concept
6x86	I-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
pipeline	O
had	O
extra	O
decode	O
stages	O
to	O
dynamically	O
translate	O
IA-32	B-Device
instructions	O
into	O
buffered	O
micro-operation	B-General_Concept
sequences	O
which	O
could	O
then	O
be	O
analysed	O
,	O
reordered	O
,	O
and	O
renamed	O
in	O
order	O
to	O
detect	O
parallelizable	O
operations	O
that	O
may	O
be	O
issued	O
to	O
more	O
than	O
one	O
execution	B-General_Concept
unit	I-General_Concept
at	O
once	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
thus	O
featured	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
,	O
including	O
speculative	B-General_Concept
execution	I-General_Concept
via	O
register	B-Architecture
renaming	I-Architecture
.	O
</s>
<s>
It	O
also	O
had	O
a	O
wider	O
36-bit	O
address	B-Architecture
bus	I-Architecture
,	O
usable	O
by	O
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
(	O
PAE	O
)	O
,	O
allowing	O
it	O
to	O
access	O
up	O
to	O
64	O
GB	O
of	O
memory	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
has	O
an	O
8KB	O
instruction	O
cache	O
,	O
from	O
which	O
up	O
to	O
16	O
bytes	O
are	O
fetched	O
on	O
each	O
cycle	O
and	O
sent	O
to	O
the	O
instruction	O
decoders	O
.	O
</s>
<s>
The	O
decoders	O
are	O
unequal	O
in	O
ability	O
:	O
only	O
one	O
can	O
decode	O
any	O
x86	B-Operating_System
instruction	O
,	O
while	O
the	O
other	O
two	O
can	O
only	O
decode	O
simple	O
x86	B-Operating_System
instructions	O
.	O
</s>
<s>
This	O
restricts	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
ability	O
to	O
decode	O
multiple	O
instructions	O
simultaneously	O
,	O
limiting	O
superscalar	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
x86	B-Operating_System
instructions	O
are	O
decoded	O
into	O
118-bit	O
micro-operations	B-General_Concept
(	O
micro-ops	B-General_Concept
)	O
.	O
</s>
<s>
The	O
micro-ops	B-General_Concept
are	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
-like	O
;	O
that	O
is	O
,	O
they	O
encode	O
an	O
operation	O
,	O
two	O
sources	O
,	O
and	O
a	O
destination	O
.	O
</s>
<s>
The	O
general	O
decoder	O
can	O
generate	O
up	O
to	O
four	O
micro-ops	B-General_Concept
per	O
cycle	O
,	O
whereas	O
the	O
simple	O
decoders	O
can	O
generate	O
one	O
micro-op	B-General_Concept
each	O
per	O
cycle	O
.	O
</s>
<s>
Thus	O
,	O
x86	B-Operating_System
instructions	O
that	O
operate	O
on	O
the	O
memory	O
(	O
e.g.	O
,	O
add	O
this	O
register	O
to	O
this	O
location	O
in	O
the	O
memory	O
)	O
can	O
only	O
be	O
processed	O
by	O
the	O
general	O
decoder	O
,	O
as	O
this	O
operation	O
requires	O
a	O
minimum	O
of	O
three	O
micro-ops	B-General_Concept
.	O
</s>
<s>
Likewise	O
,	O
the	O
simple	O
decoders	O
are	O
limited	O
to	O
instructions	O
that	O
can	O
be	O
translated	O
into	O
one	O
micro-op	B-General_Concept
.	O
</s>
<s>
Instructions	O
that	O
require	O
more	O
micro-ops	B-General_Concept
than	O
four	O
are	O
translated	O
with	O
the	O
assistance	O
of	O
a	O
sequencer	O
,	O
which	O
generates	O
the	O
required	O
micro-ops	B-General_Concept
over	O
multiple	O
clock	O
cycles	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
was	O
the	O
first	O
processor	O
in	O
the	O
x86-family	O
to	O
support	O
upgradeable	O
microcode	B-Device
under	O
BIOS	B-Operating_System
and/or	O
operating	B-General_Concept
system	I-General_Concept
(	O
OS	O
)	O
control	O
.	O
</s>
<s>
Micro-ops	B-General_Concept
exit	O
the	O
re-order	B-General_Concept
buffer	I-General_Concept
(	O
ROB	O
)	O
and	O
enter	O
a	O
reserve	O
station	O
(	O
RS	O
)	O
,	O
where	O
they	O
await	O
dispatch	O
to	O
the	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
In	O
each	O
clock	O
cycle	O
,	O
up	O
to	O
five	O
micro-ops	B-General_Concept
can	O
be	O
dispatched	O
to	O
five	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
has	O
a	O
total	O
of	O
six	O
execution	B-General_Concept
units	I-General_Concept
:	O
two	O
integer	O
units	O
,	O
one	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
a	O
load	O
unit	O
,	O
store	O
address	O
unit	O
,	O
and	O
a	O
store	O
data	O
unit	O
.	O
</s>
<s>
One	O
of	O
the	O
integer	O
units	O
shares	O
the	O
same	O
ports	O
as	O
the	O
FPU	O
,	O
and	O
therefore	O
the	O
Pentium	B-Device
Pro	I-Device
can	O
only	O
dispatch	O
one	O
integer	O
micro-op	B-General_Concept
and	O
one	O
floating-point	O
micro-op	B-General_Concept
,	O
or	O
two	O
integer	O
micro-ops	B-General_Concept
per	O
a	O
cycle	O
,	O
in	O
addition	O
to	O
micro-ops	B-General_Concept
for	O
the	O
other	O
three	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
After	O
the	O
microprocessor	B-Architecture
was	O
released	O
,	O
a	O
bug	O
was	O
discovered	O
in	O
the	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
commonly	O
called	O
the	O
"	O
Pentium	B-Device
Pro	I-Device
and	O
Pentium	B-General_Concept
II	I-General_Concept
FPU	O
bug	O
"	O
and	O
by	O
Intel	O
as	O
the	O
"	O
flag	O
erratum	O
"	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
P6	B-Device
microarchitecture	I-Device
was	O
used	O
in	O
one	O
form	O
or	O
another	O
by	O
Intel	O
for	O
more	O
than	O
a	O
decade	O
.	O
</s>
<s>
The	O
pipeline	O
would	O
scale	O
from	O
its	O
initial	O
150MHz	O
start	O
,	O
all	O
the	O
way	O
up	O
to	O
1.4GHz	O
with	O
the	O
"	O
Tualatin	O
"	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
The	O
design	O
's	O
various	O
traits	O
would	O
continue	O
after	O
that	O
in	O
the	O
derivative	O
core	O
called	O
"	O
Banias	O
"	O
in	O
Pentium	B-Architecture
M	I-Architecture
and	O
Intel	B-Device
Core	I-Device
(	O
Yonah	B-Device
)	O
,	O
which	O
itself	O
would	O
evolve	O
into	O
the	O
Core	B-Device
microarchitecture	I-Device
(	O
Core	B-Device
2	I-Device
processor	O
)	O
in	O
2006	O
and	O
onward	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
(	O
P6	B-Device
)	O
introduced	O
new	O
instructions	O
into	O
the	O
Intel	O
range	O
;	O
the	O
CMOVxx	O
(	O
‘	O
conditional	O
move’	O
)	O
instructions	O
can	O
move	O
a	O
value	O
that	O
is	O
either	O
the	O
contents	O
of	O
a	O
register	O
or	O
memory	O
location	O
into	O
another	O
register	O
or	O
not	O
,	O
according	O
to	O
some	O
predicate	O
logical	O
condition	O
xx	O
on	O
the	O
flags	O
register	O
,	O
xx	O
being	O
a	O
flags	O
predicate	O
code	O
as	O
given	O
in	O
the	O
condition	O
for	O
conditional	O
jump	O
instructions	O
.	O
</s>
<s>
This	O
op	O
code	O
is	O
reserved	O
and	O
guaranteed	O
to	O
cause	O
an	O
illegal	O
instruction	O
exception	O
on	O
the	O
P6	B-Device
and	O
all	O
later	O
processors	O
.	O
</s>
<s>
Despite	O
being	O
advanced	O
for	O
the	O
time	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
out-of-order	O
register	B-Architecture
renaming	I-Architecture
architecture	O
had	O
trouble	O
running	O
16-bit	B-Device
code	O
and	O
mixed	O
code	O
(	O
8-bit	O
with	O
16-bit	B-Device
(	O
8/16	O
)	O
,	O
or	O
16-bit	B-Device
with	O
32-bit	O
(	O
16/32	O
)	O
,	O
as	O
using	O
partial	O
registers	O
cause	O
frequent	O
pipeline	O
flushing	O
.	O
</s>
<s>
Specific	O
use	O
of	O
partial	O
registers	O
was	O
then	O
a	O
common	O
performance	O
optimization	O
,	O
as	O
it	O
incurred	O
no	O
performance	O
penalty	O
on	O
pre-P6	O
Intel	O
processors	O
;	O
also	O
,	O
the	O
dominant	O
operating	B-General_Concept
systems	I-General_Concept
at	O
the	O
time	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
release	O
were	O
16-bit	B-Device
DOS	B-Device
,	O
and	O
mixed	O
16/32	O
-bit	O
Windows	B-Application
3.1x	I-Application
and	O
Windows	B-Application
95	I-Application
(	O
although	O
the	O
latter	O
requires	O
a	O
32-bit	O
80386	O
CPU	O
,	O
much	O
of	O
its	O
code	O
is	O
still	O
16-bit	B-Device
for	O
performance	O
reasons	O
,	O
such	O
as	O
USER.exe	O
)	O
.	O
</s>
<s>
This	O
,	O
with	O
the	O
high	O
cost	O
of	O
Pentium	B-Device
Pro	I-Device
systems	O
,	O
led	O
to	O
tepid	O
sales	O
among	O
PC	O
buyers	O
at	O
the	O
time	O
.	O
</s>
<s>
To	O
fully	O
use	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
P6	B-Device
microarchitecture	I-Device
,	O
a	O
fully	O
32-bit	O
operating	B-General_Concept
system	I-General_Concept
is	O
needed	O
,	O
such	O
as	O
Windows	B-Device
NT	I-Device
,	O
Linux	B-Application
,	O
Unix	B-Application
,	O
or	O
OS/2	B-Application
.	O
</s>
<s>
The	O
performance	O
issues	O
on	O
legacy	O
code	O
were	O
later	O
partly	O
mitigated	O
by	O
Intel	O
with	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
Compared	O
to	O
RISC	B-Architecture
microprocessors	B-Architecture
,	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
when	O
introduced	O
,	O
slightly	O
outperformed	O
the	O
fastest	O
RISC	B-Architecture
microprocessors	B-Architecture
on	O
integer	O
performance	O
when	O
running	O
the	O
SPECint95	O
benchmark	O
,	O
but	O
floating-point	O
performance	O
was	O
significantly	O
lower	O
,	O
half	O
that	O
of	O
some	O
RISC	B-Architecture
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
's	O
integer	O
performance	O
lead	O
disappeared	O
rapidly	O
,	O
first	O
overtaken	O
by	O
the	O
MIPS	O
Technologies	O
R10000	B-General_Concept
in	O
January	O
1996	O
,	O
and	O
then	O
by	O
Digital	O
Equipment	O
Corporation	O
's	O
EV56	B-General_Concept
variant	O
of	O
the	O
Alpha	B-General_Concept
21164	I-General_Concept
.	O
</s>
<s>
Reviewers	O
quickly	O
noted	O
the	O
very	O
slow	O
writes	O
to	O
video	O
memory	O
as	O
the	O
weak	O
spot	O
of	O
the	O
P6	B-Device
platform	O
,	O
with	O
performance	O
here	O
being	O
as	O
low	O
as	O
10%	O
of	O
an	O
identically	O
clocked	O
Pentium	B-General_Concept
system	O
in	O
benchmarks	O
such	O
as	O
VIDSPEED	O
.	O
</s>
<s>
Methods	O
to	O
circumvent	O
this	O
included	O
setting	O
VESA	O
drawing	O
to	O
system	O
memory	O
instead	O
of	O
video	O
memory	O
in	O
games	O
such	O
as	O
Quake	B-Application
,	O
and	O
later	O
on	O
utilities	O
such	O
as	O
FASTVID	O
emerged	O
,	O
which	O
could	O
double	O
performance	O
in	O
certain	O
games	O
by	O
enabling	O
the	O
write	B-Architecture
combining	I-Architecture
features	O
of	O
the	O
CPU	O
.	O
</s>
<s>
memory	B-General_Concept
type	I-General_Concept
range	I-General_Concept
registers	I-General_Concept
(	O
MTRRs	O
)	O
are	O
set	O
automatically	O
by	O
Windows	O
video	O
drivers	O
starting	O
from	O
~	O
1997	O
,	O
and	O
there	O
the	O
improved	O
cache/memory	O
subsystem	O
and	O
FPU	O
performance	O
caused	O
it	O
to	O
outclass	O
the	O
Pentium	B-General_Concept
clock-for-clock	O
in	O
the	O
emerging	O
3D	O
games	O
of	O
the	O
mid	O
–	O
to	O
–	O
late	O
1990s	O
,	O
particularly	O
when	O
using	O
NT4	O
.	O
</s>
<s>
However	O
,	O
its	O
lack	O
of	O
MMX	B-Architecture
implementation	O
reduces	O
performance	O
in	O
multimedia	O
applications	O
that	O
made	O
use	O
of	O
those	O
instructions	O
.	O
</s>
<s>
Likely	O
Pentium	B-Device
Pro	I-Device
's	O
most	O
noticeable	O
addition	O
was	O
its	O
on-package	O
L2	O
cache	O
,	O
which	O
ranged	O
from	O
256KB	O
at	O
introduction	O
to	O
1MB	O
in	O
1997	O
.	O
</s>
<s>
Additionally	O
,	O
unlike	O
most	O
motherboard-based	O
cache	O
schemes	O
that	O
shared	O
the	O
main	O
system	O
bus	O
with	O
the	O
CPU	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
cache	O
had	O
its	O
own	O
back-side	B-Architecture
bus	I-Architecture
(	O
called	O
dual	B-Architecture
independent	I-Architecture
bus	I-Architecture
by	O
Intel	O
)	O
.	O
</s>
<s>
(	O
This	O
is	O
an	O
example	O
of	O
MLP	O
,	O
Memory	B-Operating_System
Level	I-Operating_System
Parallelism	I-Operating_System
.	O
)	O
</s>
<s>
This	O
cache	O
alone	O
gave	O
the	O
CPU	O
an	O
advantage	O
in	O
input/output	O
performance	O
over	O
older	O
x86	B-Operating_System
CPUs	O
.	O
</s>
<s>
In	O
multiprocessor	O
configurations	O
,	O
Pentium	B-Device
Pro	I-Device
's	O
integrated	O
cache	O
skyrocketed	O
performance	O
in	O
comparison	O
to	O
architectures	O
which	O
had	O
each	O
CPU	O
sharing	O
a	O
central	O
cache	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
's	O
"	O
on-package	O
cache	O
"	O
arrangement	O
was	O
unique	O
.	O
</s>
<s>
This	O
meant	O
that	O
a	O
single	O
,	O
tiny	O
flaw	O
in	O
either	O
die	O
made	O
it	O
necessary	O
to	O
discard	O
the	O
entire	O
assembly	O
,	O
which	O
was	O
one	O
of	O
the	O
reasons	O
for	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
relatively	O
low	O
production	O
yield	O
and	O
high	O
cost	O
.	O
</s>
<s>
Pentium	B-Device
Pro	I-Device
clock	O
speeds	O
were	O
150	O
,	O
166	O
,	O
180	O
or	O
200MHz	O
with	O
a	O
60	O
or	O
66MHz	O
external	B-Architecture
bus	I-Architecture
clock	O
.	O
</s>
<s>
Some	O
users	O
chose	O
to	O
overclock	B-Application
their	O
Pentium	B-Device
Pro	I-Device
chips	O
,	O
with	O
the	O
200MHz	O
version	O
often	O
being	O
run	O
at	O
233MHz	O
,	O
the	O
180MHz	O
version	O
often	O
being	O
run	O
at	O
200MHz	O
,	O
and	O
the	O
150MHz	O
version	O
often	O
being	O
run	O
at	O
166MHz	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
is	O
family	O
6	O
,	O
model	O
1	O
,	O
and	O
its	O
Intel	O
Product	O
code	O
is	O
80521	O
.	O
</s>
<s>
The	O
process	O
used	O
to	O
fabricate	O
the	O
Pentium	B-Device
Pro	I-Device
processor	O
die	O
and	O
its	O
separate	O
cache	O
memory	O
die	O
changed	O
,	O
leading	O
to	O
a	O
combination	O
of	O
processes	O
used	O
in	O
the	O
same	O
package	O
:	O
</s>
<s>
The	O
133MHz	O
Pentium	B-Device
Pro	I-Device
prototype	O
processor	O
die	O
was	O
fabricated	O
in	O
a	O
0.6μm	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
The	O
150MHz	O
Pentium	B-Device
Pro	I-Device
processor	O
die	O
was	O
fabricated	O
in	O
a	O
0.50μm	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
The	O
166	O
,	O
180	O
,	O
and	O
200MHz	O
Pentium	B-Device
Pro	I-Device
processor	O
die	O
was	O
fabricated	O
in	O
a	O
0.35μm	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
The	O
256KB	O
L2	O
cache	O
die	O
was	O
fabricated	O
in	O
a	O
0.50μm	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
The	O
512	O
and	O
1024KB	O
L2	O
cache	O
die	O
was	O
fabricated	O
in	O
a	O
0.35μm	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
(	O
up	O
to	O
512KB	O
cache	O
)	O
is	O
packaged	O
in	O
a	O
ceramic	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
.	O
</s>
<s>
The	O
MCM	O
contains	O
two	O
underside	O
cavities	O
in	O
which	O
the	O
microprocessor	B-Architecture
die	O
and	O
its	O
companion	O
cache	O
die	O
reside	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
with	O
1MB	O
of	O
cache	O
uses	O
a	O
plastic	O
MCM	O
.	O
</s>
<s>
The	O
MCM	O
has	O
387pins	O
,	O
of	O
which	O
approximately	O
half	O
are	O
arranged	O
in	O
a	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	B-Algorithm
)	O
and	O
half	O
in	O
an	O
interstitial	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
IPGA	O
)	O
.	O
</s>
<s>
The	O
packaging	O
was	O
designed	O
for	O
Socket	B-Device
8	I-Device
.	O
</s>
<s>
In	O
1998	O
,	O
the	O
300/333MHz	O
Pentium	B-General_Concept
II	I-General_Concept
Overdrive	O
processor	O
for	O
Socket8	O
was	O
released	O
.	O
</s>
<s>
Featuring	O
double	O
L1	O
and	O
512KB	O
of	O
full-speed	O
L2	O
cache	O
,	O
it	O
was	O
produced	O
by	O
Intel	O
as	O
a	O
drop-in	O
upgrade	O
option	O
for	O
owners	O
of	O
Pentium	B-Device
Pro	I-Device
systems	O
.	O
</s>
<s>
These	O
specially	O
packaged	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
processors	O
were	O
used	O
to	O
upgrade	O
ASCI	B-Device
Red	I-Device
,	O
which	O
became	O
the	O
first	O
computer	O
to	O
reach	O
the	O
teraFLOPS	O
performance	O
mark	O
with	O
the	O
Pentium	B-Device
Pro	I-Device
processor	O
and	O
then	O
the	O
first	O
to	O
exceed	O
2	O
teraFLOPS	O
after	O
the	O
upgrade	O
to	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
processors	O
.	O
</s>
<s>
As	O
Slot	B-Device
1	I-Device
motherboards	O
became	O
prevalent	O
,	O
several	O
manufacturers	O
released	O
slocket	B-General_Concept
adapters	O
,	O
such	O
as	O
the	O
Tyan	O
M2020	O
,	O
Asus	O
C-P6S1	O
,	O
Tekram	O
P6SL1	O
,	O
and	O
the	O
Abit	O
KP6	O
.	O
</s>
<s>
The	O
sockets	O
allowed	O
Pentium	B-Device
Pro	I-Device
processors	O
to	O
be	O
used	O
with	O
Slot1	O
motherboards	O
.	O
</s>
<s>
The	O
Intel	B-Device
440FX	I-Device
chipset	O
explicitly	O
supported	O
both	O
Pentium	B-Device
Pro	I-Device
and	O
PentiumII	O
processors	O
,	O
but	O
the	O
Intel	B-Device
440BX	I-Device
and	O
later	O
Slot1	O
chipsets	O
did	O
not	O
explicitly	O
support	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
so	O
the	O
Socket8	O
slockets	B-General_Concept
did	O
not	O
see	O
wide	O
use	O
.	O
</s>
<s>
Slockets	B-General_Concept
,	O
in	O
the	O
form	O
of	O
Socket	B-Device
370	I-Device
to	O
Slot1	O
adapters	O
,	O
saw	O
renewed	O
popularity	O
when	O
Intel	O
introduced	O
Socket370	O
Celeron	B-Device
and	O
Pentium	B-General_Concept
III	I-General_Concept
processors	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
used	O
GTL+	B-General_Concept
signaling	O
in	O
its	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
could	O
be	O
used	O
by	O
itself	O
on	O
up	O
to	O
four-way	O
designs	O
.	O
</s>
<s>
Eight-way	O
Pentium	B-Device
Pro	I-Device
computers	O
were	O
also	O
built	O
,	O
but	O
these	O
used	O
multiple	O
buses	O
.	O
</s>
<s>
The	O
design	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
bus	O
was	O
influenced	O
by	O
Futurebus	B-Architecture
,	O
the	O
Intel	B-Device
iAPX	I-Device
432	I-Device
bus	O
,	O
and	O
elements	O
of	O
the	O
Intel	B-General_Concept
i960	I-General_Concept
bus	O
.	O
</s>
<s>
Futurebus	B-Architecture
has	O
been	O
intended	O
as	O
an	O
advanced	O
bus	O
to	O
replace	O
VMEbus	B-Architecture
used	O
with	O
the	O
Motorola	B-Device
68000	I-Device
from	O
the	O
late	O
1970s	O
,	O
but	O
it	O
stagnated	O
in	O
standardization	O
committee	O
for	O
more	O
than	O
a	O
decade	O
if	O
you	O
count	O
all	O
the	O
twists	O
and	O
turns	O
.	O
</s>
<s>
Intel	O
's	O
iAPX	B-Device
432	I-Device
initiative	O
was	O
also	O
a	O
commercial	O
failure	O
,	O
but	O
in	O
the	O
process	O
they	O
did	O
learn	O
how	O
to	O
build	O
a	O
split-transaction	O
bus	O
to	O
support	O
a	O
cacheless	O
multiprocessor	O
system	O
.	O
</s>
<s>
The	O
i960	B-General_Concept
had	O
further	O
developed	O
the	O
split-transaction	O
iAPX	B-Device
432	I-Device
bus	O
to	O
include	O
a	O
cache	O
coherency	O
protocol	O
,	O
ending	O
up	O
with	O
a	O
feature	O
set	O
highly	O
reminiscent	O
of	O
the	O
original	O
Futurebus	B-Architecture
ambitions	O
.	O
</s>
<s>
The	O
lead	O
architect	O
of	O
i960	B-General_Concept
was	O
superscalarity	O
specialist	O
Fred	O
Pollack	O
who	O
was	O
also	O
the	O
lead	O
engineer	O
of	O
the	O
Intel	B-Device
iAPX	I-Device
432	I-Device
and	O
the	O
lead	O
architect	O
of	O
the	O
i686	B-Device
chip	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
was	O
designed	O
to	O
include	O
the	O
4-way	O
SMP	O
split-transaction	O
cache-coherent	O
bus	O
as	O
a	O
mandatory	O
feature	O
of	O
every	O
chip	O
produced	O
.	O
</s>
<s>
While	O
the	O
Pentium	B-Device
Pro	I-Device
was	O
not	O
successful	O
as	O
a	O
machine	O
for	O
the	O
masses	O
,	O
due	O
to	O
poor	O
16-bit	B-Device
support	O
for	O
Windows	B-Application
95	I-Application
,	O
it	O
did	O
become	O
highly	O
successful	O
in	O
the	O
file	O
server	O
space	O
due	O
to	O
its	O
advanced	O
,	O
integrated	O
bus	O
design	O
,	O
introducing	O
many	O
advanced	O
features	O
that	O
had	O
formerly	O
only	O
been	O
available	O
in	O
the	O
pricey	O
workstation	O
segment	O
into	O
the	O
commodity	O
marketplace	O
.	O
</s>
