<s>
The	O
Pentium	B-Architecture
M	I-Architecture
is	O
a	O
family	O
of	O
mobile	O
32-bit	O
single-core	O
x86	B-Operating_System
microprocessors	I-Operating_System
(	O
with	O
the	O
modified	O
Intel	B-Device
P6	I-Device
microarchitecture	O
)	O
introduced	O
in	O
March	O
2003	O
and	O
forming	O
a	O
part	O
of	O
the	O
Intel	O
Carmel	O
notebook	O
platform	O
under	O
the	O
then	O
new	O
Centrino	B-Device
brand	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
processors	O
had	O
a	O
maximum	O
thermal	B-General_Concept
design	I-General_Concept
power	I-General_Concept
(	O
TDP	B-General_Concept
)	O
of	O
5	O
–	O
27	O
W	O
depending	O
on	O
the	O
model	O
,	O
and	O
were	O
intended	O
for	O
use	O
in	O
laptops	O
(	O
thus	O
the	O
"	O
M	O
"	O
suffix	O
standing	O
for	O
mobile	O
)	O
.	O
</s>
<s>
They	O
evolved	O
from	O
the	O
core	B-Device
of	O
the	O
last	O
Pentium	B-General_Concept
III	I-General_Concept
–	O
branded	O
CPU	B-Device
by	O
adding	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	B-Architecture
)	O
interface	O
of	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
an	O
improved	O
instruction	O
decoding	O
and	O
issuing	O
front	O
end	O
,	O
improved	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
SSE2	B-General_Concept
support	O
,	O
and	O
a	O
much	O
larger	O
cache	O
.	O
</s>
<s>
The	O
first	O
Pentium	B-Architecture
M	I-Architecture
–	O
branded	O
CPU	B-Device
,	O
code-named	O
Banias	O
,	O
was	O
followed	O
by	O
Dothan	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
line	O
was	O
removed	O
from	O
the	O
official	O
price	O
lists	O
in	O
July	O
2009	O
,	O
when	O
the	O
Pentium	O
M-branded	O
processors	O
were	O
succeeded	O
by	O
the	O
Core-branded	O
dual-core	B-Architecture
mobile	O
Yonah	B-Device
CPU	B-Device
with	O
a	O
modified	O
microarchitecture	O
.	O
</s>
<s>
It	O
replaced	O
the	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
processor	O
,	O
which	O
suffered	O
from	O
power	O
consumption	O
and	O
heat	O
problems	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
represented	O
a	O
new	O
and	O
radical	O
departure	O
for	O
Intel	O
,	O
as	O
it	O
was	O
not	O
a	O
low-power	O
version	O
of	O
the	O
desktop-oriented	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
but	O
instead	O
a	O
heavily	O
modified	O
version	O
of	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
Tualatin	O
design	O
(	O
itself	O
based	O
on	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
core	B-Device
design	O
,	O
which	O
in	O
turn	O
had	O
been	O
a	O
heavily	O
improved	O
evolution	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
)	O
.	O
</s>
<s>
Running	O
with	O
very	O
low	O
average	O
power	O
consumption	O
and	O
much	O
lower	O
heat	O
output	O
than	O
desktop	O
processors	O
,	O
the	O
Pentium	B-Architecture
M	I-Architecture
runs	O
at	O
a	O
lower	O
clock	O
speed	O
than	O
the	O
laptop	O
version	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
(	O
The	O
Pentium	O
4-Mobile	O
,	O
or	O
P4-M	B-General_Concept
)	O
,	O
but	O
with	O
similar	O
performance	O
-	O
a	O
1.6GHz	O
Pentium	B-Architecture
M	I-Architecture
can	O
typically	O
attain	O
or	O
even	O
surpass	O
the	O
performance	O
of	O
a	O
2.4GHz	O
Pentium	O
4-M	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
740	I-Architecture
has	O
been	O
tested	O
to	O
perform	O
up	O
to	O
approximately	O
7,400	O
MIPS	O
and	O
3.9	O
GFLOPS	O
(	O
using	O
SSE2	B-General_Concept
)	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
coupled	O
the	O
execution	O
core	B-Device
of	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
with	O
a	O
Pentium	B-General_Concept
4	I-General_Concept
compatible	O
bus	O
interface	O
,	O
an	O
improved	O
instruction	O
decoding/issuing	O
front	O
end	O
,	O
improved	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
SSE2	B-General_Concept
support	O
,	O
and	O
a	O
much	O
larger	O
cache	O
.	O
</s>
<s>
Other	O
power	O
saving	O
methods	O
include	O
dynamically	O
variable	O
clock	O
frequency	O
and	O
core	B-Device
voltage	O
,	O
allowing	O
the	O
Pentium	B-Architecture
M	I-Architecture
to	O
throttle	O
clock	O
speed	O
when	O
the	O
system	O
is	O
idle	O
in	O
order	O
to	O
conserve	O
energy	O
,	O
using	O
the	O
SpeedStep	B-Device
3	O
technology	O
(	O
which	O
has	O
more	O
sleep	O
stages	O
than	O
previous	O
versions	O
of	O
SpeedStep	B-Device
)	O
.	O
</s>
<s>
With	O
this	O
technology	O
,	O
a	O
1.6GHz	O
Pentium	B-Architecture
M	I-Architecture
can	O
effectively	O
throttle	O
to	O
clock	O
speeds	O
of	O
600MHz	O
,	O
800MHz	O
,	O
1000MHz	O
,	O
1200MHz	O
,	O
1400MHz	O
and	O
1600MHz	O
;	O
these	O
intermediate	O
clock	O
states	O
allow	O
the	O
CPU	B-Device
to	O
better	O
throttle	O
clock	O
speed	O
to	O
suit	O
conditions	O
.	O
</s>
<s>
The	O
power	O
requirements	O
of	O
the	O
Pentium	B-Architecture
M	I-Architecture
varies	O
from	O
5watts	O
when	O
idle	O
to	O
27watts	O
at	O
full	O
load	O
.	O
</s>
<s>
This	O
is	O
useful	O
to	O
notebook	O
manufacturers	O
as	O
it	O
allows	O
them	O
to	O
include	O
the	O
Pentium	B-Architecture
M	I-Architecture
into	O
smaller	O
notebooks	O
.	O
</s>
<s>
Although	O
Intel	O
marketed	O
the	O
Pentium	B-Architecture
M	I-Architecture
exclusively	O
as	O
a	O
mobile	O
product	O
,	O
motherboard	O
manufacturers	O
such	O
as	O
AOpen	O
,	O
DFI	O
and	O
MSI	O
shipped	O
Pentium	B-Architecture
M	I-Architecture
compatible	O
boards	O
designed	O
to	O
non-mobile	O
enthusiasts	O
,	O
HTPC	O
,	O
workstation	O
and	O
server	O
applications	O
.	O
</s>
<s>
An	O
adapter	O
,	O
the	O
CT-479	O
,	O
was	O
developed	O
by	O
ASUS	O
to	O
allow	O
the	O
use	O
of	O
Pentium	B-Architecture
M	I-Architecture
processors	O
in	O
selected	O
ASUS	O
motherboards	O
designed	O
for	O
Socket	B-Device
478	I-Device
Pentium	B-General_Concept
4	I-General_Concept
processors	O
.	O
</s>
<s>
Shuttle	O
Inc	O
.	O
offered	O
packaged	O
Pentium	B-Architecture
M	I-Architecture
desktops	O
,	O
marketed	O
for	O
low	O
energy	O
consumption	O
and	O
minimal	O
cooling	O
system	O
noise	O
.	O
</s>
<s>
Pentium	B-Architecture
M	I-Architecture
processors	O
are	O
also	O
of	O
interest	O
to	O
embedded	B-Architecture
systems	I-Architecture
 '	O
manufacturers	O
because	O
the	O
low	O
power	O
consumption	O
of	O
the	O
Pentium	B-Architecture
M	I-Architecture
allows	O
the	O
design	O
of	O
fanless	O
and	O
miniaturized	O
embedded	O
PCs	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
also	O
responds	O
very	O
well	O
to	O
undervolting	O
,	O
which	O
can	O
be	O
done	O
with	O
the	O
program	O
Notebook	O
Hardware	O
Control	O
or	O
RMClock	O
.	O
</s>
<s>
As	O
the	O
M	O
line	O
was	O
originally	O
designed	O
in	O
Israel	O
,	O
the	O
first	O
Pentium	B-Architecture
M	I-Architecture
was	O
identified	O
by	O
the	O
codename	O
Banias	O
,	O
named	O
after	O
an	O
ancient	O
site	O
in	O
the	O
Golan	O
Heights	O
.	O
</s>
<s>
The	O
Intel	O
Haifa	O
team	O
had	O
previously	O
been	O
working	O
on	O
the	O
memory	O
controller	O
for	O
Timna	B-Device
,	O
which	O
was	O
based	O
on	O
earlier	O
P6	B-Device
memory	O
controller	O
designs	O
giving	O
them	O
detailed	O
knowledge	O
of	O
P6	B-Device
architecture	O
which	O
they	O
used	O
when	O
Intel	O
gave	O
them	O
a	O
crash	O
project	O
to	O
create	O
a	O
backup	O
mobile	O
CPU	B-Device
.	O
</s>
<s>
It	O
was	O
manufactured	O
on	O
a	O
130nm	O
process	O
,	O
was	O
released	O
at	O
frequencies	O
from	O
900MHz	O
to	O
1.7GHz	O
using	O
a	O
400MT/s	O
FSB	B-Architecture
,	O
and	O
had	O
1	O
megabyte	O
(	O
MB	O
)	O
of	O
Level	O
2	O
cache	O
.	O
</s>
<s>
The	O
core	B-Device
average	O
TDP	B-General_Concept
(	O
Thermal	B-General_Concept
Design	I-General_Concept
Power	I-General_Concept
)	O
is	O
24.5	O
watts	O
.	O
</s>
<s>
The	O
Banias	O
family	O
processors	O
internally	O
support	O
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
(	O
PAE	B-General_Concept
)	O
but	O
do	O
not	O
show	O
the	O
PAE	B-General_Concept
support	O
flag	O
in	O
their	O
CPUID	B-Architecture
information	O
;	O
this	O
causes	O
some	O
operating	O
systems	O
(	O
primarily	O
Linux	O
distributions	O
)	O
to	O
refuse	O
to	O
boot	O
on	O
such	O
processors	O
since	O
PAE	B-General_Concept
support	O
is	O
required	O
in	O
their	O
kernels	O
.	O
</s>
<s>
Using	O
the	O
'	O
forcepae	O
 '	O
Linux	O
boot	O
option	O
will	O
allow	O
Linux	O
to	O
boot	O
using	O
PAE	B-General_Concept
in	O
these	O
cases	O
.	O
</s>
<s>
Windows	B-Application
8	I-Application
and	O
later	O
wo	O
n't	O
boot	O
on	O
these	O
CPUs	B-Device
for	O
the	O
same	O
reason	O
,	O
emitting	O
an	O
error	O
with	O
code	O
0xc0000260	O
when	O
attempting	O
to	O
load	O
ntoskrnl.exe	O
early	O
on	O
in	O
the	O
boot	O
process	O
.	O
</s>
<s>
On	O
September	O
17	O
,	O
2003	O
,	O
Intel	O
unveiled	O
plans	O
for	O
releasing	O
its	O
then	O
next-generation	O
of	O
Pentium	B-Architecture
M	I-Architecture
processors	O
,	O
codenamed	O
"	O
Dothan	O
"	O
by	O
them	O
.	O
</s>
<s>
Dothan	O
Pentium	B-Architecture
M	I-Architecture
processors	O
(	O
product	O
code	O
80536	O
,	O
CPUID	B-Architecture
0x6DX	O
)	O
are	O
among	O
the	O
first	O
Intel	O
processors	O
to	O
be	O
identified	O
using	O
a	O
"	O
processor	O
number	O
"	O
rather	O
than	O
a	O
clockspeed	O
rating	O
;	O
the	O
initial	O
Dothan	O
versions	O
with	O
the	O
400Mhz	O
Front-Side-Bus	O
(	O
FSB	B-Architecture
)	O
are	O
known	O
as	O
Pentium	B-Architecture
M	I-Architecture
710	O
(	O
1.4GHz	O
)	O
,	O
715	O
(	O
1.5GHz	O
)	O
,	O
725	O
(	O
1.6GHz	O
)	O
,	O
735	O
(	O
1.7GHz	O
)	O
,	O
745	O
(	O
1.8GHz	O
)	O
,	O
755	O
(	O
2.0GHz	O
)	O
,	O
and	O
765	O
(	O
2.1GHz	O
)	O
.	O
</s>
<s>
These	O
initial	O
Dothan	O
models	O
all	O
have	O
a	O
TDP	B-General_Concept
of	O
21W	O
and	O
a	O
2MB	O
L2	O
cache	O
.	O
</s>
<s>
These	O
700	O
series	O
Dothan	O
Pentium	B-Architecture
M	I-Architecture
processors	O
retain	O
the	O
same	O
basic	O
design	O
as	O
the	O
original	O
Banias	O
Pentium	B-Architecture
M	I-Architecture
,	O
but	O
are	O
manufactured	O
on	O
a	O
90	O
nm	O
process	O
,	O
with	O
twice	O
the	O
secondary	O
cache	O
.	O
</s>
<s>
Die	O
size	O
,	O
at	O
87mm2	O
,	O
remains	O
in	O
the	O
same	O
neighborhood	O
as	O
the	O
original	O
Pentium	B-Architecture
M	I-Architecture
,	O
even	O
though	O
the	O
1000	O
series	O
contains	O
approximately	O
140	O
million	O
transistors	O
,	O
most	O
of	O
which	O
make	O
up	O
the	O
2MB	O
cache	O
.	O
</s>
<s>
Revisions	O
of	O
the	O
Dothan	O
core	B-Device
were	O
released	O
in	O
the	O
first	O
quarter	O
of	O
2005	O
with	O
the	O
Sonoma	O
chipsets	O
and	O
supported	O
a	O
533MT/s	O
FSB	B-Architecture
and	O
XD	O
(	O
Intel	O
's	O
name	O
for	O
the	O
NX	B-General_Concept
bit	I-General_Concept
)	O
;	O
and	O
the	O
PAE	B-General_Concept
support	O
flag	O
in	O
the	O
CPUID	B-Architecture
was	O
enabled	O
,	O
unlike	O
earlier	O
Pentium	B-Architecture
Ms	I-Architecture
that	O
showed	O
PAE	B-General_Concept
unavailable	O
.	O
</s>
<s>
These	O
revised	O
Dothan	O
processors	O
include	O
the	O
730	O
(	O
1.6GHz	O
)	O
,	O
740	O
(	O
1.73GHz	O
)	O
,	O
750	O
(	O
1.86GHz	O
)	O
,	O
760	O
(	O
2.0GHz	O
)	O
,	O
770	O
(	O
2.13GHz	O
)	O
and	O
780	O
(	O
2.26	O
GHz	O
)	O
and	O
have	O
a	O
TDP	B-General_Concept
of	O
27W	O
and	O
a	O
2MB	O
L2	O
cache	O
.	O
</s>
<s>
The	O
models	O
with	O
lower	O
frequencies	O
were	O
either	O
low	O
voltage	O
or	O
ultra-low	O
voltage	O
CPUs	B-Device
designed	O
for	O
improved	O
battery	O
life	O
and	O
reduced	O
heat	O
output	O
.	O
</s>
<s>
The	O
718	O
(	O
1.3GHz	O
)	O
,	O
738	O
(	O
1.4GHz	O
)	O
,	O
and	O
758	O
(	O
1.5GHz	O
)	O
models	O
are	O
low-voltage	O
(	O
1.116V	O
)	O
with	O
a	O
TDP	B-General_Concept
of	O
10W	O
,	O
while	O
the	O
723	O
(	O
1.0GHz	O
)	O
,	O
733	O
(	O
1.1GHz	O
)	O
,	O
and	O
753	O
(	O
1.2GHz	O
)	O
models	O
are	O
ultra-low	O
voltage	O
(	O
0.940V	O
)	O
with	O
a	O
TDP	B-General_Concept
of	O
5W	O
.	O
</s>
<s>
An	O
ultra	O
low-power	O
microprocessor	B-Architecture
based	O
on	O
the	O
Dothan	O
built	O
on	O
a	O
90nm	O
process	O
with	O
512	O
KB	O
L2	O
cache	O
and	O
400	O
MT/s	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
(	O
FSB	B-Architecture
)	O
.	O
</s>
<s>
The	O
next	O
generation	O
of	O
processors	O
,	O
codenamed	O
Yonah	B-Device
,	O
were	O
based	O
on	O
the	O
Enhanced	O
Pentium	B-Architecture
M	I-Architecture
architecture	O
,	O
and	O
released	O
under	O
the	O
Intel	B-Device
Core	I-Device
brand	O
,	O
as	O
Core	B-Device
Duo	O
and	O
Core	B-Device
Solo	O
.	O
</s>
