<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
(	O
marketed	O
as	O
Intel	B-General_Concept
Pentium	I-General_Concept
III	I-General_Concept
Processor	I-General_Concept
,	O
informally	O
PIII	B-General_Concept
or	O
P3	O
)	O
brand	O
refers	O
to	O
Intel	O
's	O
32-bit	B-Device
x86	I-Device
desktop	B-Device
and	O
mobile	B-General_Concept
CPUs	I-General_Concept
based	O
on	O
the	O
sixth-generation	O
P6	B-Device
microarchitecture	I-Device
introduced	O
on	O
February	O
28	O
,	O
1999	O
.	O
</s>
<s>
The	O
most	O
notable	O
differences	O
were	O
the	O
addition	O
of	O
the	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	B-General_Concept
)	O
instruction	B-General_Concept
set	I-General_Concept
(	O
to	O
accelerate	O
floating	B-Algorithm
point	I-Algorithm
and	O
parallel	O
calculations	O
)	O
,	O
and	O
the	O
introduction	O
of	O
a	O
controversial	O
serial	O
number	O
embedded	O
in	O
the	O
chip	O
during	O
manufacturing	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
is	O
also	O
a	O
single-core	O
processor	O
.	O
</s>
<s>
Even	O
after	O
the	O
release	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
in	O
late	O
2000	O
,	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
continued	O
to	O
be	O
produced	O
with	O
new	O
models	O
introduced	O
until	O
early	O
2003	O
,	O
and	O
were	O
discontinued	O
in	O
April	O
2004	O
for	O
desktop	B-Device
units	O
,	O
and	O
May	O
2007	O
for	O
mobile	O
units	O
.	O
</s>
<s>
Similarly	O
to	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
it	O
superseded	O
,	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
was	O
also	O
accompanied	O
by	O
the	O
Celeron	B-Device
brand	O
for	O
lower-end	O
versions	O
,	O
and	O
the	O
Xeon	B-Device
for	O
high-end	O
(	O
server	O
and	O
workstation	O
)	O
derivatives	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
was	O
eventually	O
superseded	O
by	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
but	O
its	O
Tualatin	O
core	O
also	O
served	O
as	O
the	O
basis	O
for	O
the	O
Pentium	B-Architecture
M	I-Architecture
CPUs	B-Device
,	O
which	O
used	O
many	O
ideas	O
from	O
the	O
P6	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Subsequently	O
,	O
it	O
was	O
the	O
Pentium	B-Architecture
M	I-Architecture
microarchitecture	O
of	O
Pentium	B-Architecture
M	I-Architecture
branded	O
CPUs	B-Device
,	O
and	O
not	O
the	O
NetBurst	B-Device
found	O
in	O
Pentium	B-General_Concept
4	I-General_Concept
processors	O
,	O
that	O
formed	O
the	O
basis	O
for	O
Intel	O
's	O
energy-efficient	O
Core	B-Device
microarchitecture	I-Device
of	O
CPUs	B-Device
branded	O
Core	B-Device
2	I-Device
,	O
Pentium	B-Device
Dual-Core	I-Device
,	O
Celeron	B-Device
(	O
Core	O
)	O
,	O
and	O
Xeon	B-Device
.	O
</s>
<s>
The	O
first	O
Pentium	B-General_Concept
III	I-General_Concept
variant	O
was	O
the	O
Katmai	O
(	O
Intel	O
product	O
code	O
80525	O
)	O
.	O
</s>
<s>
It	O
was	O
a	O
further	O
development	O
of	O
the	O
Deschutes	O
Pentium	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
saw	O
an	O
increase	O
of	O
2	O
million	O
transistors	O
over	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
The	O
differences	O
were	O
the	O
addition	O
of	O
execution	O
units	O
and	O
SSE	B-General_Concept
instruction	O
support	O
,	O
and	O
an	O
improved	O
L1	O
cache	B-General_Concept
controller	O
(	O
the	O
L2	O
cache	B-General_Concept
controller	O
was	O
left	O
unchanged	O
,	O
as	O
it	O
would	O
be	O
fully	O
redesigned	O
for	O
Coppermine	O
anyway	O
)	O
,	O
which	O
were	O
responsible	O
for	O
the	O
minor	O
performance	O
improvements	O
over	O
the	O
"	O
Deschutes	O
"	O
Pentium	B-General_Concept
IIs	I-General_Concept
.	O
</s>
<s>
The	O
Katmai	O
contains	O
9.5	O
million	O
transistors	O
,	O
not	O
including	O
the	O
512	O
Kbytes	O
L2	O
cache	B-General_Concept
(	O
which	O
adds	O
25	O
million	O
transistors	O
)	O
,	O
and	O
has	O
dimensions	O
of	O
12.3mm	O
by	O
10.4mm	O
(	O
128mm2	O
)	O
.	O
</s>
<s>
It	O
is	O
fabricated	O
in	O
Intel	O
's	O
P856.5	O
process	O
,	O
a	O
0.25	O
micrometre	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
process	O
with	O
five	O
levels	O
of	O
aluminum	O
interconnect	O
.	O
</s>
<s>
The	O
Katmai	O
used	O
the	O
same	O
slot-based	O
design	O
as	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
but	O
with	O
the	O
newer	O
Slot	B-Device
1	I-Device
Single	B-Device
Edge	I-Device
Contact	I-Device
Cartridge	I-Device
(	O
SECC	O
)	O
2	O
that	O
allowed	O
direct	O
CPU	B-Device
core	O
contact	O
with	O
the	O
heat	O
sink	O
.	O
</s>
<s>
A	O
notable	O
stepping	B-General_Concept
level	I-General_Concept
for	O
enthusiasts	O
was	O
SL35D	O
.	O
</s>
<s>
This	O
version	O
of	O
Katmai	O
was	O
officially	O
rated	O
for	O
450MHz	O
,	O
but	O
often	O
contained	O
cache	B-General_Concept
chips	O
for	O
the	O
600MHz	O
model	O
and	O
thus	O
usually	O
can	O
run	O
at	O
600MHz	O
.	O
</s>
<s>
From	O
December	O
1999	O
to	O
May	O
2000	O
,	O
Intel	O
released	O
Pentium	B-General_Concept
IIIs	I-General_Concept
running	O
at	O
speeds	O
of	O
750	O
,	O
800	O
,	O
850	O
,	O
866	O
,	O
900	O
,	O
933	O
and	O
1000MHz	O
(	O
1GHz	O
)	O
.	O
</s>
<s>
In	O
overall	O
performance	O
,	O
Coppermine	O
had	O
a	O
small	O
advantage	O
over	O
the	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
Athlons	B-Architecture
it	O
was	O
released	O
against	O
,	O
which	O
was	O
reversed	O
when	O
AMD	O
applied	O
their	O
own	O
die	O
shrink	O
and	O
added	O
an	O
on-die	O
L2	O
cache	B-General_Concept
to	O
the	O
Athlon	B-Architecture
.	O
</s>
<s>
Athlon	B-Architecture
held	O
the	O
advantage	O
in	O
floating-point	B-Algorithm
intensive	O
code	O
,	O
while	O
the	O
Coppermine	O
could	O
perform	O
better	O
when	O
SSE	B-General_Concept
optimizations	O
were	O
used	O
,	O
but	O
in	O
practical	O
terms	O
there	O
was	O
little	O
difference	O
in	O
how	O
the	O
two	O
chips	O
performed	O
,	O
clock-for-clock	O
.	O
</s>
<s>
However	O
,	O
AMD	O
were	O
able	O
to	O
clock	O
the	O
Athlon	B-Architecture
higher	O
,	O
reaching	O
speeds	O
of	O
1.2GHz	O
before	O
the	O
launch	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
In	O
performance	O
,	O
Coppermine	O
arguably	O
marked	O
a	O
bigger	O
step	O
than	O
Katmai	O
by	O
introducing	O
an	O
on-chip	O
L2	O
cache	B-General_Concept
,	O
which	O
Intel	O
names	O
Advanced	O
Transfer	O
Cache	B-General_Concept
(	O
ATC	O
)	O
.	O
</s>
<s>
The	O
ATC	O
operates	O
at	O
the	O
core	O
clock	O
rate	O
and	O
has	O
a	O
capacity	O
of	O
256KB	O
,	O
twice	O
that	O
of	O
the	O
on-chip	O
cache	B-General_Concept
formerly	O
on	O
Mendocino	O
Celerons	B-Device
.	O
</s>
<s>
Under	O
competitive	O
pressure	O
from	O
the	O
AMD	B-Architecture
Athlon	I-Architecture
,	O
Intel	O
reworked	O
the	O
internals	O
,	O
finally	O
removing	O
some	O
well-known	O
pipeline	B-General_Concept
stalls	O
.	O
</s>
<s>
The	O
Coppermine	O
was	O
available	O
in	O
370-pin	O
FC-PGA	B-Algorithm
or	O
FC-PGA2	O
for	O
use	O
with	O
Socket	B-Device
370	I-Device
,	O
or	O
in	O
SECC2	O
for	O
Slot	B-Device
1	I-Device
(	O
all	O
speeds	O
except	O
900	O
and	O
1100	O
)	O
.	O
</s>
<s>
FC-PGA	B-Algorithm
and	O
Slot	B-Device
1	I-Device
Coppermine	O
CPUs	B-Device
have	O
an	O
exposed	O
die	O
,	O
however	O
most	O
higher	O
frequency	O
SKUs	O
starting	O
with	O
the	O
866MHz	O
model	O
were	O
also	O
produced	O
in	O
FC-PGA2	O
variants	O
that	O
feature	O
an	O
integrated	O
heat	O
spreader	O
(	O
IHS	O
)	O
.	O
</s>
<s>
Some	O
heatsink	O
manufacturers	O
began	O
providing	O
pads	O
on	O
their	O
products	O
,	O
similar	O
to	O
what	O
AMD	O
did	O
with	O
the	O
"	O
Thunderbird	O
"	O
Athlon	B-Architecture
to	O
ensure	O
that	O
the	O
heatsink	O
was	O
mounted	O
flatly	O
.	O
</s>
<s>
A	O
1.13GHz	O
version	O
(	O
S-Spec	O
SL4HH	O
)	O
was	O
released	O
in	O
mid-2000	O
but	O
famously	O
recalled	O
after	O
a	O
collaboration	O
between	O
HardOCP	O
and	O
Tom	O
's	O
Hardware	O
discovered	O
various	O
instabilities	O
with	O
the	O
operation	O
of	O
the	O
new	O
CPU	B-Device
speed	O
grade	O
.	O
</s>
<s>
In	O
benchmarks	O
that	O
were	O
stable	O
,	O
performance	O
was	O
shown	O
to	O
be	O
sub-par	O
,	O
with	O
the	O
1.13GHz	O
CPU	B-Device
equalling	O
a	O
1.0GHz	O
model	O
.	O
</s>
<s>
Tom	O
's	O
Hardware	O
attributed	O
this	O
performance	O
deficit	O
to	O
relaxed	O
tuning	O
of	O
the	O
CPU	B-Device
and	O
motherboard	O
to	O
improve	O
stability	O
.	O
</s>
<s>
Intel	O
needed	O
at	O
least	O
six	O
months	O
to	O
resolve	O
the	O
problems	O
using	O
a	O
new	O
cD0	O
stepping	B-General_Concept
and	O
re-released	O
1.1GHz	O
and	O
1.13GHz	O
versions	O
in	O
2001	O
.	O
</s>
<s>
Microsoft	O
's	O
Xbox	B-Application
game	O
console	O
uses	O
a	O
variant	O
of	O
the	O
Pentium	O
III/Mobile	O
Celeron	O
family	O
in	O
a	O
Micro-PGA2	B-Device
form	O
factor	O
.	O
</s>
<s>
The	O
sSpec	O
designator	O
of	O
the	O
chips	O
is	O
SL5Sx	O
,	O
which	O
makes	O
it	O
more	O
similar	O
to	O
the	O
Mobile	B-Device
Celeron	I-Device
Coppermine-128	O
processor	O
.	O
</s>
<s>
It	O
shares	O
with	O
the	O
Coppermine-128	O
Celeron	B-Device
its	O
128KB	O
L2	O
cache	B-General_Concept
,	O
and	O
180nm	O
process	O
technology	O
,	O
but	O
keeps	O
the	O
8-way	O
cache	B-General_Concept
associativity	O
from	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
Intel	O
used	O
the	O
latest	O
FC-PGA2	O
Coppermines	O
with	O
the	O
cD0	O
stepping	B-General_Concept
and	O
modified	O
them	O
so	O
that	O
they	O
worked	O
with	O
low	O
voltage	O
system	O
bus	O
operation	O
at	O
1.25	O
V	O
AGTL	B-General_Concept
as	O
well	O
as	O
normal	O
1.5	O
V	O
AGTL+	B-General_Concept
signal	O
levels	O
,	O
and	O
would	O
auto	O
detect	O
differential	O
or	O
single-ended	O
clocking	O
.	O
</s>
<s>
This	O
modification	O
made	O
them	O
compatible	O
to	O
the	O
latest	O
generation	O
Socket	B-Device
370	I-Device
boards	O
supporting	O
Tualatin	O
CPUs	B-Device
while	O
maintaining	O
compatibility	O
with	O
older	O
Socket	B-Device
370	I-Device
boards	O
.	O
</s>
<s>
Tualatin-based	O
Pentium	B-General_Concept
IIIs	I-General_Concept
were	O
released	O
during	O
2001	O
until	O
early	O
2002	O
at	O
speeds	O
of	O
1.0	O
,	O
1.13	O
,	O
1.2	O
,	O
1.26	O
,	O
1.33	O
and	O
1.4GHz	O
.	O
</s>
<s>
A	O
basic	O
shrink	O
of	O
Coppermine	O
,	O
no	O
new	O
features	O
were	O
added	O
,	O
except	O
for	O
added	O
data	O
prefetch	O
logic	O
similar	O
to	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Athlon	B-Architecture
XP	O
for	O
potentially	O
better	O
use	O
of	O
the	O
L2	O
cache	B-General_Concept
,	O
although	O
its	O
use	O
compared	O
to	O
these	O
newer	O
CPUs	B-Device
is	O
limited	O
due	O
to	O
the	O
relatively	O
smaller	O
FSB	O
bandwidth	O
(	O
FSB	O
was	O
still	O
kept	O
at	O
133MHz	O
)	O
.	O
</s>
<s>
Variants	O
with	O
256	O
and	O
512KB	O
L2	O
cache	B-General_Concept
were	O
produced	O
,	O
the	O
latter	O
being	O
dubbed	O
Pentium	O
III-S	O
;	O
this	O
variant	O
was	O
mainly	O
intended	O
for	O
low-power	O
consumption	O
servers	O
and	O
also	O
exclusively	O
featured	O
SMP	O
support	O
within	O
the	O
Tualatin	O
line	O
.	O
</s>
<s>
Although	O
the	O
Socket	B-Device
370	I-Device
designation	O
was	O
kept	O
,	O
the	O
use	O
of	O
1.25	O
AGTL	B-General_Concept
signaling	O
in	O
place	O
of	O
1.5	O
V	O
AGTL+	B-General_Concept
rendered	O
prior	O
motherboards	O
incompatible	O
.	O
</s>
<s>
This	O
confusion	O
carried	O
over	O
to	O
the	O
chipset	O
naming	O
,	O
where	O
only	O
the	O
B-stepping	O
of	O
the	O
i815	O
chipset	O
was	O
compatible	O
with	O
Tualatin	O
processors	O
.	O
</s>
<s>
A	O
new	O
VRM	O
guideline	O
was	O
also	O
designed	O
by	O
Intel	O
,	O
version	O
8.5	O
,	O
which	O
required	O
finer	O
voltage	O
steps	O
and	O
debuted	O
load	O
line	O
Vcore	B-Device
(	O
in	O
place	O
of	O
fixed	O
voltage	O
regardless	O
of	O
current	O
on	O
8.4	O
)	O
.	O
</s>
<s>
Some	O
motherboard	O
manufacturers	O
would	O
mark	O
the	O
change	O
with	O
blue	O
sockets	O
(	O
instead	O
of	O
white	O
)	O
,	O
and	O
were	O
often	O
also	O
backwards	O
compatible	O
with	O
Coppermine	O
CPUs	B-Device
.	O
</s>
<s>
The	O
Tualatin	O
also	O
formed	O
the	O
basis	O
for	O
the	O
highly	O
popular	O
Pentium	O
III-M	O
mobile	B-General_Concept
processor	I-General_Concept
,	O
which	O
became	O
Intel	O
's	O
front-line	O
mobile	O
chip	O
(	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
drew	O
significantly	O
more	O
power	O
,	O
and	O
so	O
was	O
not	O
well-suited	O
for	O
this	O
role	O
)	O
for	O
the	O
next	O
two	O
years	O
.	O
</s>
<s>
The	O
Tualatin-based	O
Pentium	B-General_Concept
III	I-General_Concept
performed	O
well	O
in	O
some	O
applications	O
compared	O
to	O
the	O
fastest	O
Willamette-based	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
and	O
even	O
the	O
Thunderbird-based	O
Athlons	B-Architecture
.	O
</s>
<s>
Tualatin-based	O
Pentium	B-General_Concept
III	I-General_Concept
CPUs	B-Device
can	O
usually	O
be	O
visually	O
distinguished	O
from	O
Coppermine-based	O
processors	O
by	O
the	O
metal	O
integrated	O
heat-spreader	O
(	O
IHS	O
)	O
fixed	O
on	O
top	O
of	O
the	O
package	O
.	O
</s>
<s>
However	O
,	O
the	O
last	O
models	O
of	O
Coppermine	O
Pentium	B-General_Concept
IIIs	I-General_Concept
also	O
featured	O
the	O
IHS	O
—	O
the	O
integrated	O
heat	O
spreader	O
is	O
actually	O
what	O
distinguishes	O
the	O
FC-PGA2	O
package	O
from	O
the	O
FC-PGA	B-Algorithm
—	O
both	O
are	O
for	O
Socket	B-Device
370	I-Device
motherboards	O
.	O
</s>
<s>
Before	O
the	O
addition	O
of	O
the	O
heat	O
spreader	O
,	O
it	O
was	O
sometimes	O
difficult	O
to	O
install	O
a	O
heatsink	O
on	O
a	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
One	O
had	O
to	O
be	O
careful	O
not	O
to	O
put	O
force	O
on	O
the	O
core	O
at	O
an	O
angle	O
because	O
doing	O
so	O
would	O
cause	O
the	O
edges	O
and	O
corners	O
of	O
the	O
core	O
to	O
crack	O
and	O
could	O
destroy	O
the	O
CPU	B-Device
.	O
</s>
<s>
It	O
was	O
also	O
sometimes	O
difficult	O
to	O
achieve	O
a	O
flat	O
mating	O
of	O
the	O
CPU	B-Device
and	O
heatsink	O
surfaces	O
,	O
a	O
factor	O
of	O
critical	O
importance	O
to	O
good	O
heat	O
transfer	O
.	O
</s>
<s>
This	O
became	O
increasingly	O
challenging	O
with	O
the	O
Socket	B-Device
370	I-Device
CPUs	B-Device
,	O
compared	O
with	O
their	O
Slot	B-Device
1	I-Device
predecessors	O
,	O
because	O
of	O
the	O
force	O
required	O
to	O
mount	O
a	O
socket-based	O
cooler	O
and	O
the	O
narrower	O
,	O
2-sided	O
mounting	O
mechanism	O
(	O
Slot	B-Device
1	I-Device
featured	O
4-point	O
mounting	O
)	O
.	O
</s>
<s>
As	O
such	O
,	O
and	O
because	O
the	O
0.13μm	O
Tualatin	O
had	O
an	O
even	O
smaller	O
core	O
surface	O
area	O
than	O
the	O
0.18μm	O
Coppermine	O
,	O
Intel	O
installed	O
the	O
metal	O
heatspreader	O
on	O
Tualatin	O
and	O
all	O
future	O
desktop	B-Device
processors	O
.	O
</s>
<s>
Since	O
Katmai	O
was	O
built	O
in	O
the	O
same	O
0.25µm	O
process	O
as	O
Pentium	B-General_Concept
II	I-General_Concept
"	O
Deschutes	O
"	O
,	O
it	O
had	O
to	O
implement	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	B-General_Concept
)	O
using	O
minimal	O
silicon	O
.	O
</s>
<s>
To	O
utilize	O
the	O
existing	O
64-bit	O
data	O
paths	O
,	O
Katmai	O
issues	O
each	O
SIMD-FP	O
instruction	O
as	O
two	O
μops	B-General_Concept
.	O
</s>
<s>
To	O
compensate	O
partially	O
for	O
implementing	O
only	O
half	O
of	O
SSE	B-General_Concept
's	O
architectural	O
width	O
,	O
Katmai	O
implements	O
the	O
SIMD-FP	O
adder	O
as	O
a	O
separate	O
unit	O
on	O
the	O
second	O
dispatch	O
port	O
.	O
</s>
<s>
This	O
organization	O
allows	O
one	O
half	O
of	O
a	O
SIMD	O
multiply	O
and	O
one	O
half	O
of	O
an	O
independent	O
SIMD	O
add	O
to	O
be	O
issued	O
together	O
bringing	O
the	O
peak	O
throughput	O
back	O
to	O
four	O
floating	B-Algorithm
point	I-Algorithm
operations	O
per	O
cycle	O
—	O
at	O
least	O
for	O
code	O
with	O
an	O
even	O
distribution	O
of	O
multiplies	O
and	O
adds	O
.	O
</s>
<s>
The	O
issue	O
was	O
that	O
Katmai	O
's	O
hardware-implementation	O
contradicted	O
the	O
parallelism	O
model	O
implied	O
by	O
the	O
SSE	B-General_Concept
instruction-set	O
.	O
</s>
<s>
Programmers	O
faced	O
a	O
code-scheduling	O
dilemma	O
:	O
"	O
Should	O
the	O
SSE-code	O
be	O
tuned	O
for	O
Katmai	O
's	O
limited	O
execution	O
resources	O
,	O
or	O
should	O
it	O
be	O
tuned	O
for	O
a	O
future	O
processor	O
with	O
more	O
resources	O
?	O
"	O
</s>
<s>
Katmai-specific	O
SSE	B-General_Concept
optimizations	O
yielded	O
the	O
best	O
possible	O
performance	O
from	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
family	O
but	O
was	O
suboptimal	O
for	O
Coppermine	O
onwards	O
as	O
well	O
as	O
future	O
Intel	O
processors	O
,	O
such	O
as	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Core	O
series	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
was	O
the	O
first	O
x86	B-Operating_System
CPU	B-Device
to	O
include	O
a	O
unique	O
,	O
retrievable	O
,	O
identification	O
number	O
,	O
called	O
Processor	O
Serial	O
Number	O
(	O
PSN	O
)	O
.	O
</s>
<s>
A	O
Pentium	B-General_Concept
III	I-General_Concept
's	O
PSN	O
can	O
be	O
read	O
by	O
software	O
through	O
the	O
CPUID	B-Architecture
instruction	O
if	O
this	O
feature	O
has	O
not	O
been	O
disabled	O
through	O
the	O
BIOS	B-Operating_System
.	O
</s>
<s>
Intel	O
eventually	O
removed	O
the	O
PSN	O
feature	O
from	O
Tualatin-based	O
Pentium	B-General_Concept
IIIs	I-General_Concept
,	O
and	O
the	O
feature	O
was	O
absent	O
in	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Pentium	B-Architecture
M	I-Architecture
.	O
</s>
<s>
A	O
largely	O
equivalent	O
feature	O
,	O
the	O
Protected	O
Processor	O
Identification	O
Number	O
(	O
PPIN	O
)	O
was	O
later	O
added	O
to	O
x86	B-Operating_System
CPUs	B-Device
with	O
little	O
public	O
notice	O
,	O
starting	O
with	O
Intel	O
's	O
Ivy	B-Device
Bridge	I-Device
architecture	O
and	O
compatible	O
Zen	O
2	O
AMD	O
CPUs	B-Device
.	O
</s>
<s>
It	O
is	O
implemented	O
as	O
a	O
set	O
of	O
model-specific	B-General_Concept
registers	I-General_Concept
and	O
is	O
useful	O
for	O
machine	B-Device
check	I-Device
exception	I-Device
handling	O
.	O
</s>
<s>
A	O
new	O
feature	O
was	O
added	O
to	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
:	O
a	O
hardware-based	O
random	B-Algorithm
number	I-Algorithm
generator	O
.	O
</s>
