<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
brand	O
refers	O
to	O
Intel	O
's	O
sixth-generation	O
microarchitecture	B-General_Concept
(	O
"	O
P6	B-Device
"	O
)	O
and	O
x86-compatible	O
microprocessors	B-Architecture
introduced	O
on	O
May	O
7	O
,	O
1997	O
.	O
</s>
<s>
Containing	O
7.5	O
million	O
transistors	B-Application
(	O
27.4	O
million	O
in	O
the	O
case	O
of	O
the	O
mobile	O
Dixon	O
with	O
256KB	O
L2	B-General_Concept
cache	I-General_Concept
)	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
featured	O
an	O
improved	O
version	O
of	O
the	O
first	O
P6-generation	O
core	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
which	O
contained	O
5.5	O
million	O
transistors	B-Application
.	O
</s>
<s>
However	O
,	O
its	O
L2	B-General_Concept
cache	I-General_Concept
subsystem	O
was	O
a	O
downgrade	O
when	O
compared	O
to	O
the	O
Pentium	B-Device
Pros	I-Device
.	O
</s>
<s>
It	O
is	O
a	O
single-core	O
microprocessor	B-Architecture
.	O
</s>
<s>
In	O
1998	O
,	O
Intel	O
stratified	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
family	O
by	O
releasing	O
the	O
Pentium	O
II-based	O
Celeron	B-Device
line	O
of	O
processors	O
for	O
low-end	O
workstations	B-Device
and	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
line	O
for	O
servers	O
and	O
high-end	O
workstations	B-Device
.	O
</s>
<s>
The	O
Celeron	B-Device
was	O
characterized	O
by	O
a	O
reduced	O
or	O
omitted	O
(	O
in	O
some	O
cases	O
present	O
but	O
disabled	O
)	O
on-die	O
full-speed	O
L2	B-General_Concept
cache	I-General_Concept
and	O
a	O
66	O
MT/s	O
FSB	O
.	O
</s>
<s>
The	O
Xeon	O
was	O
characterized	O
by	O
a	O
range	O
of	O
full-speed	O
L2	B-General_Concept
cache	I-General_Concept
(	O
from	O
512KB	O
to	O
2048KB	O
)	O
,	O
a	O
100MT/s	O
FSB	O
,	O
a	O
different	O
physical	O
interface	O
(	O
Slot	B-Device
2	I-Device
)	O
,	O
and	O
support	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
.	O
</s>
<s>
In	O
February	O
1999	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
was	O
replaced	O
by	O
the	O
nearly	O
identical	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
which	O
only	O
added	O
the	O
then-new	O
SSE	B-General_Concept
instruction	O
set	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
microprocessor	B-Architecture
was	O
largely	O
based	O
upon	O
the	O
microarchitecture	B-General_Concept
of	O
its	O
predecessor	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
but	O
with	O
some	O
significant	O
improvements	O
.	O
</s>
<s>
Unlike	O
previous	O
Pentium	B-General_Concept
and	O
Pentium	B-Device
Pro	I-Device
processors	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
CPU	O
was	O
packaged	O
in	O
a	O
slot-based	O
module	O
rather	O
than	O
a	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
This	O
larger	O
package	O
was	O
a	O
compromise	O
allowing	O
Intel	O
to	O
separate	O
the	O
secondary	B-General_Concept
cache	I-General_Concept
from	O
the	O
processor	O
while	O
still	O
keeping	O
it	O
on	O
a	O
closely	O
coupled	O
back-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
L2	B-General_Concept
cache	I-General_Concept
ran	O
at	O
half	O
the	O
processor	O
's	O
clock	O
frequency	O
,	O
unlike	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
whose	O
off	O
die	O
L2	B-General_Concept
cache	I-General_Concept
ran	O
at	O
the	O
same	O
frequency	O
as	O
the	O
processor	O
.	O
</s>
<s>
However	O
,	O
its	O
associativity	O
was	O
increased	O
to	O
16-way	O
(	O
compared	O
to	O
4-way	O
on	O
the	O
Pentium	B-Device
Pro	I-Device
)	O
and	O
its	O
size	O
was	O
always	O
512KB	O
,	O
twice	O
of	O
the	O
smallest	O
option	O
of	O
256KB	O
on	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
Off-package	O
cache	B-General_Concept
solved	O
the	O
Pentium	B-Device
Pro	I-Device
's	O
low	O
yield	O
issues	O
,	O
allowing	O
Intel	O
to	O
introduce	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
at	O
a	O
mainstream	O
price	O
level	O
.	O
</s>
<s>
Intel	O
improved	O
16-bit	B-Device
code	O
execution	O
performance	O
on	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
,	O
an	O
area	O
in	O
which	O
the	O
Pentium	B-Device
Pro	I-Device
was	O
at	O
a	O
notable	O
handicap	O
,	O
by	O
adding	O
segment	O
register	O
caches	O
.	O
</s>
<s>
Most	O
consumer	O
software	O
of	O
the	O
day	O
was	O
still	O
using	O
at	O
least	O
some	O
16-bit	B-Device
code	O
,	O
because	O
of	O
a	O
variety	O
of	O
factors	O
.	O
</s>
<s>
To	O
compensate	O
for	O
the	O
slower	O
L2	B-General_Concept
cache	I-General_Concept
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
featured	O
32KB	O
of	O
L1	O
cache	B-General_Concept
,	O
double	O
that	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
as	O
well	O
as	O
4	O
write	O
buffers	O
(	O
vs	O
.	O
2	O
on	O
the	O
Pentium	B-Device
Pro	I-Device
)	O
;	O
these	O
can	O
also	O
be	O
used	O
by	O
either	O
pipeline	O
,	O
instead	O
of	O
each	O
one	O
being	O
fixed	O
to	O
one	O
pipeline	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
was	O
also	O
the	O
first	O
P6-based	O
CPU	O
to	O
implement	O
the	O
Intel	B-Architecture
MMX	I-Architecture
integer	O
SIMD	B-Device
instruction	O
set	O
which	O
had	O
already	O
been	O
introduced	O
on	O
the	O
Pentium	B-General_Concept
MMX	B-Architecture
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
was	O
basically	O
a	O
more	O
consumer-oriented	O
version	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
It	O
was	O
cheaper	O
to	O
manufacture	O
because	O
of	O
the	O
separate	O
,	O
slower	O
L2	B-General_Concept
cache	I-General_Concept
memory	O
.	O
</s>
<s>
The	O
improved	O
16-bit	B-Device
performance	O
and	O
MMX	B-Architecture
support	O
made	O
it	O
a	O
better	O
choice	O
for	O
consumer-level	O
operating	O
systems	O
,	O
such	O
as	O
Windows	O
9x	O
,	O
and	O
multimedia	O
applications	O
.	O
</s>
<s>
The	O
slower	O
and	O
cheaper	O
L2	B-General_Concept
cache	I-General_Concept
's	O
performance	O
penalty	O
was	O
mitigated	O
by	O
the	O
doubled	O
L1	O
cache	B-General_Concept
and	O
architectural	O
improvements	O
for	O
legacy	O
code	O
.	O
</s>
<s>
All	O
Klamath	O
and	O
some	O
early	O
Deschutes	O
Pentium	B-General_Concept
IIs	I-General_Concept
use	O
a	O
combined	O
L2	B-General_Concept
cache	I-General_Concept
controller	O
/	O
tag	O
RAM	O
chip	O
that	O
only	O
allows	O
for	O
512MB	O
to	O
be	O
cached	O
;	O
while	O
more	O
RAM	O
could	O
be	O
installed	O
in	O
theory	O
,	O
this	O
would	O
result	O
in	O
very	O
slow	O
performance	O
.	O
</s>
<s>
While	O
this	O
limit	O
was	O
practically	O
irrelevant	O
for	O
the	O
average	O
home	O
user	O
at	O
the	O
time	O
,	O
it	O
was	O
a	O
concern	O
for	O
some	O
workstation	B-Device
or	O
server	B-Application
users	O
.	O
</s>
<s>
Presumably	O
,	O
Intel	O
put	O
this	O
limitation	O
deliberately	O
in	O
place	O
to	O
distinguish	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
from	O
the	O
more	O
upmarket	O
Pentium	B-Device
Pro	I-Device
line	O
,	O
which	O
has	O
a	O
full	O
4GB	O
cacheable	O
area	O
.	O
</s>
<s>
The	O
'	O
82459AD	O
 '	O
revision	O
of	O
the	O
chip	O
on	O
some	O
333MHz	O
and	O
all	O
350MHz	O
and	O
faster	O
Pentium	B-General_Concept
IIs	I-General_Concept
lifted	O
this	O
restriction	O
and	O
also	O
offered	O
a	O
full	O
4	O
GB	O
cacheable	O
area	O
.	O
</s>
<s>
The	O
original	O
Klamath	O
Pentium	B-General_Concept
II	I-General_Concept
microprocessor	B-Architecture
(	O
Intel	O
product	O
code	O
80522	O
)	O
ran	O
at	O
233	O
,	O
266	O
,	O
and	O
300MHz	O
and	O
was	O
produced	O
in	O
a	O
0.35	O
μm	O
process	B-Architecture
.	O
</s>
<s>
These	O
CPUs	O
had	O
a	O
66MHz	O
front-side	B-Architecture
bus	I-Architecture
and	O
were	O
initially	O
used	O
on	O
motherboards	O
equipped	O
with	O
the	O
aging	O
Intel	O
440FX	O
Natoma	O
chipset	O
designed	O
for	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
Pentium	O
II-based	O
systems	O
using	O
the	O
Intel	B-Device
440LX	I-Device
Balboa	O
chipset	O
widely	O
popularized	O
SDRAM	O
(	O
which	O
was	O
to	O
replace	O
EDO	O
RAM	O
and	O
was	O
already	O
introduced	O
with	O
430VX	O
)	O
,	O
and	O
the	O
AGP	B-Architecture
graphics	O
bus	O
.	O
</s>
<s>
On	O
July	O
14	O
,	O
1997	O
,	O
Intel	O
announced	O
a	O
version	O
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Klamath	O
with	O
2×	O
72-bit	O
ECC	O
L2	B-General_Concept
cache	I-General_Concept
for	O
entry-level	O
servers	O
,	O
as	O
opposed	O
to	O
the	O
2×	O
64-bit	O
non-ECC	O
L2	B-General_Concept
cache	I-General_Concept
on	O
regular	O
models	O
.	O
</s>
<s>
The	O
Deschutes	O
core	O
Pentium	B-General_Concept
II	I-General_Concept
(	O
80523	O
)	O
,	O
which	O
debuted	O
at	O
333MHz	O
in	O
January	O
1998	O
,	O
was	O
produced	O
with	O
a	O
0.25	O
μm	O
process	B-Architecture
and	O
has	O
a	O
significantly	O
lower	O
power	O
draw	O
.	O
</s>
<s>
The	O
333MHz	O
variant	O
was	O
the	O
final	O
Pentium	B-General_Concept
II	I-General_Concept
CPU	O
that	O
used	O
the	O
older	O
66MHz	O
front-side	B-Architecture
bus	I-Architecture
;	O
all	O
subsequent	O
Deschutes-core	O
models	O
used	O
a	O
100MHz	O
FSB	O
.	O
</s>
<s>
Later	O
in	O
1998	O
,	O
Pentium	B-General_Concept
IIs	I-General_Concept
running	O
at	O
266	O
,	O
300	O
,	O
350	O
,	O
400	O
,	O
and	O
450MHz	O
were	O
also	O
released	O
.	O
</s>
<s>
Overclockers	B-Application
,	O
upon	O
learning	O
of	O
this	O
,	O
purchased	O
the	O
units	O
in	O
question	O
and	O
ran	O
them	O
well	O
over	O
500MHz	O
;	O
most	O
notably	O
,	O
when	O
overclocking	B-Application
,	O
the	O
final	O
batch	O
of	O
"	O
333	O
MHz	O
"	O
CPUs	O
were	O
capable	O
of	O
speeds	O
much	O
higher	O
than	O
CPUs	O
sold	O
at	O
350	O
,	O
400	O
,	O
or	O
450MHz	O
.	O
</s>
<s>
Concurrent	O
with	O
the	O
release	O
of	O
Deschutes	O
cores	O
supporting	O
a	O
100MHz	O
front-side	B-Architecture
bus	I-Architecture
was	O
Intel	O
's	O
release	O
of	O
the	O
440BX	B-Device
Seattle	O
chipset	O
and	O
its	O
derivatives	O
,	O
the	O
440MX	O
,	O
450NX	O
,	O
and	O
440ZX	O
chipsets	O
.	O
</s>
<s>
Replacing	O
the	O
aged	O
66MHz	O
FSB	O
,	O
which	O
had	O
been	O
on	O
the	O
market	O
since	O
1993	O
,	O
the	O
100MHz	O
FSB	O
resulted	O
in	O
solid	O
performance	O
improvements	O
for	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
lineup	O
.	O
</s>
<s>
Pentium	B-General_Concept
II	I-General_Concept
chips	O
starting	O
with	O
350MHz	O
were	O
released	O
in	O
both	O
SECC	O
and	O
SECC2	O
form	O
factors	O
.	O
</s>
<s>
Late	O
Pentium	B-General_Concept
IIs	I-General_Concept
also	O
marked	O
the	O
switch	O
to	O
flip-chip	B-Device
based	O
packaging	O
with	O
direct	O
heatsink	O
contact	O
to	O
the	O
die	O
,	O
as	O
opposed	O
to	O
traditional	O
bonding	O
.	O
</s>
<s>
While	O
Klamath	O
features	O
4	O
cache	B-General_Concept
chips	O
and	O
simulates	O
dual-porting	O
through	O
interleaving	O
(	O
2x	O
64-bit	O
)	O
for	O
a	O
slight	O
performance	O
improvement	O
on	O
concurrent	O
accesses	O
,	O
Deschutes	O
only	O
sports	O
2	O
cache	B-General_Concept
chips	O
and	O
offers	O
slightly	O
lower	O
L2	B-General_Concept
cache	I-General_Concept
performance	O
at	O
the	O
same	O
clockspeed	O
.	O
</s>
<s>
Furthermore	O
,	O
Deschutes	O
always	O
features	O
ECC-enabled	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
was	O
a	O
high-end	O
version	O
of	O
Deschutes	O
core	O
intended	O
for	O
use	O
on	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
Principally	O
,	O
it	O
used	O
a	O
different	O
type	O
of	O
slot	B-Device
(	O
Slot	B-Device
2	I-Device
)	O
,	O
case	O
,	O
board	O
design	O
,	O
and	O
more	O
expensive	O
full-speed	O
custom	O
L2	B-General_Concept
cache	I-General_Concept
,	O
which	O
was	O
off-die	O
.	O
</s>
<s>
In	O
1998	O
,	O
the	O
0.25	O
μm	O
Deschutes	O
core	O
was	O
utilized	O
in	O
the	O
creation	O
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Overdrive	O
processor	O
,	O
which	O
was	O
aimed	O
at	O
allowing	O
corporate	O
Pentium	B-Device
Pro	I-Device
users	O
to	O
upgrade	O
their	O
aging	O
servers	O
.	O
</s>
<s>
Combining	O
the	O
Deschutes	O
core	O
in	O
a	O
flip-chip	B-Device
package	O
with	O
a	O
512KB	O
full-speed	O
L2	B-General_Concept
cache	I-General_Concept
chip	O
from	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
into	O
a	O
Socket	O
8-compatible	O
module	O
resulted	O
in	O
a	O
300	O
or	O
333MHz	O
processor	O
that	O
could	O
run	O
on	O
a	O
60	O
or	O
66MHz	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
This	O
combination	O
brought	O
together	O
some	O
of	O
the	O
more	O
attractive	O
aspects	O
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	O
:	O
MMX	B-Architecture
support/improved	O
16-bit	B-Device
performance	O
and	O
full-speed	O
L2	B-General_Concept
cache	I-General_Concept
,	O
respectively	O
.	O
</s>
<s>
The	O
later	O
"	O
Dixon	O
"	O
mobile	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
would	O
emulate	O
this	O
combination	O
with	O
256KB	O
of	O
full-speed	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
OverDrive	O
CPU	O
identifies	O
itself	O
as	O
family	O
6	O
,	O
model	O
3	O
,	O
though	O
this	O
is	O
misleading	O
,	O
as	O
it	O
is	O
not	O
based	O
on	O
the	O
family	O
6/model	O
3	O
Klamath	O
core	O
.	O
</s>
<s>
As	O
mentioned	O
in	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Processor	O
update	O
documentation	O
from	O
Intel	O
,	O
"	O
although	O
this	O
processor	O
has	O
a	O
CPUID	O
of	O
163xh	O
,	O
it	O
uses	O
a	O
Pentium	B-General_Concept
II	I-General_Concept
processor	O
CPUID	O
065xh	O
processor	O
core.	O
"	O
</s>
<s>
The	O
0.25μm	O
Tonga	O
core	O
was	O
the	O
first	O
mobile	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
and	O
had	O
all	O
of	O
the	O
features	O
of	O
the	O
desktop	O
models	O
.	O
</s>
<s>
Later	O
,	O
in	O
1999	O
,	O
the	O
0.25	O
;	O
0.18	O
(	O
400MHz	O
)	O
μm	O
Dixon	O
core	O
with	O
256KB	O
of	O
on-die	O
full	O
speed	O
cache	B-General_Concept
was	O
produced	O
for	O
the	O
mobile	O
market	O
.	O
</s>
<s>
Reviews	O
showed	O
that	O
the	O
Dixon	O
core	O
was	O
the	O
fastest	O
type	O
of	O
Pentium	B-General_Concept
II	I-General_Concept
produced	O
.	O
</s>
<s>
These	O
identifiers	O
are	O
shared	O
with	O
the	O
Mendocino	O
Celeron	B-Device
processors	O
.	O
</s>
<s>
L2	B-General_Concept
cache	I-General_Concept
:	O
512KB	O
,	O
as	O
external	O
chips	O
on	O
the	O
CPU	O
module	O
clocked	O
at	O
half	O
the	O
CPU	O
frequency	O
.	O
</s>
<s>
L2	B-General_Concept
cache	I-General_Concept
:	O
512KB	O
,	O
as	O
external	O
chips	O
on	O
the	O
CPU	O
module	O
clocked	O
at	O
half	O
the	O
CPU	O
frequency	O
.	O
</s>
<s>
The	O
sSpec	O
number	O
SL2KE	O
denotes	O
a	O
Pentium	B-General_Concept
II	I-General_Concept
Overdrive	O
sold	O
with	O
an	O
integrated	O
heatsink/fan	O
combination	O
for	O
Socket	B-Device
8	I-Device
.	O
</s>
<s>
[	O
Note	O
that	O
the	O
sSpec	O
number	O
SL2EA	O
denotes	O
a	O
Pentium	B-General_Concept
II	I-General_Concept
Overdrive	O
sold	O
with	O
an	O
integrated	O
heatsink	O
but	O
no	O
fan	O
for	O
Slot	O
1.	O
]	O
</s>
<s>
L2	B-General_Concept
cache	I-General_Concept
:	O
512KB	O
,	O
as	O
external	O
chips	O
on	O
the	O
CPU	O
module	O
clocked	O
at	O
half	O
the	O
CPU	O
frequency	O
.	O
</s>
<s>
L2	B-General_Concept
cache	I-General_Concept
:	O
256KB	O
,	O
on-die	O
,	O
full	O
speed	O
.	O
</s>
