<s>
Pentium	B-General_Concept
4	I-General_Concept
is	O
a	O
series	O
of	O
single-core	O
CPUs	O
for	O
desktops	O
,	O
laptops	B-Device
and	O
entry-level	O
servers	O
manufactured	O
by	O
Intel	O
.	O
</s>
<s>
All	O
Pentium	B-General_Concept
4	I-General_Concept
CPUs	O
are	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
4	I-General_Concept
Willamette	O
(	O
180nm	O
)	O
introduced	O
SSE2	B-General_Concept
,	O
while	O
the	O
Prescott	O
(	O
90nm	O
)	O
introduced	O
SSE3	B-General_Concept
.	O
</s>
<s>
Later	O
versions	O
introduced	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
(	O
HTT	O
)	O
.	O
</s>
<s>
The	O
first	O
Pentium	O
4-branded	O
processor	O
to	O
implement	O
64-bit	B-Device
was	O
the	O
Prescott	O
(	O
90nm	O
)	O
(	O
February	O
2004	O
)	O
,	O
but	O
this	O
feature	O
was	O
not	O
enabled	O
.	O
</s>
<s>
Intel	O
subsequently	O
began	O
selling	O
64-bit	B-Device
Pentium	B-General_Concept
4s	I-General_Concept
using	O
the	O
"	O
E0	O
"	O
revision	O
of	O
the	O
Prescotts	O
,	O
being	O
sold	O
on	O
the	O
OEM	O
market	O
as	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
model	O
F	O
.	O
The	O
E0	O
revision	O
also	O
adds	O
eXecute	O
Disable	O
(	O
XD	O
)	O
(	O
Intel	O
's	O
name	O
for	O
the	O
NX	B-General_Concept
bit	I-General_Concept
)	O
to	O
Intel64	B-Device
.	O
</s>
<s>
Intel	O
's	O
official	O
launch	O
of	O
Intel64	B-Device
(	O
under	O
the	O
name	O
EM64T	B-Device
at	O
that	O
time	O
)	O
in	O
mainstream	O
desktop	B-Device
processors	O
was	O
the	O
N0	O
stepping	O
Prescott-2M	O
.	O
</s>
<s>
Intel	O
also	O
marketed	O
a	O
version	O
of	O
their	O
low-end	O
Celeron	B-Device
processors	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
(	O
often	O
referred	O
to	O
as	O
Celeron	B-Device
4	O
)	O
,	O
and	O
a	O
high-end	O
derivative	O
,	O
Xeon	B-Device
,	O
intended	O
for	O
multi-socket	B-Operating_System
servers	O
and	O
workstations	B-Device
.	O
</s>
<s>
In	O
2005	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
complemented	O
by	O
the	O
dual-core-brands	O
Pentium	B-Device
D	I-Device
and	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
.	O
</s>
<s>
In	O
benchmark	O
evaluations	O
,	O
the	O
advantages	O
of	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
were	O
unclear	O
.	O
</s>
<s>
With	O
carefully	O
optimized	O
application	O
code	O
,	O
the	O
first	O
Pentium	B-General_Concept
4s	I-General_Concept
outperformed	O
Intel	O
's	O
fastest	O
Pentium	B-General_Concept
III	I-General_Concept
(	O
clocked	O
at	O
1.13GHz	O
at	O
the	O
time	O
)	O
,	O
as	O
expected	O
.	O
</s>
<s>
But	O
in	O
legacy	B-Device
applications	I-Device
with	O
many	O
branching	O
or	O
x87	B-Application
floating-point	B-Algorithm
instructions	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
would	O
merely	O
match	O
or	O
run	O
slower	O
than	O
its	O
predecessor	O
.	O
</s>
<s>
The	O
NetBurst	B-Device
microarchitecture	I-Device
consumed	O
more	O
power	O
and	O
emitted	O
more	O
heat	O
than	O
any	O
previous	O
Intel	O
or	O
AMD	O
microarchitectures	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
introduction	O
was	O
met	O
with	O
mixed	O
reviews	O
:	O
Developers	O
disliked	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
as	O
it	O
posed	O
a	O
new	O
set	O
of	O
code	O
optimization	O
rules	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
mathematical	O
applications	O
,	O
AMD	O
's	O
lower-clocked	O
Athlon	B-Architecture
(	O
the	O
fastest-clocked	O
model	O
was	O
clocked	O
at	O
1.2GHz	O
at	O
the	O
time	O
)	O
easily	O
outperformed	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
which	O
would	O
only	O
catch	O
up	O
if	O
software	O
was	O
re-compiled	O
with	O
SSE2	B-General_Concept
support	O
.	O
</s>
<s>
Tom	O
Yager	O
of	O
Infoworld	O
magazine	O
called	O
it	O
"	O
the	O
fastest	O
CPU	B-General_Concept
-	O
for	O
programs	O
that	O
fit	O
entirely	O
in	O
cache	O
"	O
.	O
</s>
<s>
Computer-savvy	O
buyers	O
avoided	O
Pentium	B-General_Concept
4	I-General_Concept
PCs	O
due	O
to	O
their	O
price	O
premium	O
,	O
questionable	O
benefit	O
,	O
and	O
initial	O
restriction	O
to	O
Rambus	O
 '	O
RDRAM	O
.	O
</s>
<s>
In	O
terms	O
of	O
product	O
marketing	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
singular	O
emphasis	O
on	O
clock	O
frequency	O
(	O
above	O
all	O
else	O
)	O
made	O
it	O
a	O
marketer	O
's	O
dream	O
.	O
</s>
<s>
The	O
result	O
of	O
this	O
was	O
that	O
the	O
NetBurst	B-Device
micro	O
architecture	O
was	O
often	O
referred	O
to	O
as	O
a	O
marchitecture	O
by	O
various	O
computing	O
websites	O
and	O
publications	O
during	O
the	O
life	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
The	O
two	O
classical	O
metrics	O
of	O
CPU	B-General_Concept
performance	O
are	O
IPC	O
(	O
instructions	O
per	O
cycle	O
)	O
and	O
clock	O
speed	O
.	O
</s>
<s>
Unsophisticated	O
buyers	O
would	O
simply	O
consider	O
the	O
processor	O
with	O
the	O
highest	O
clock	O
speed	O
to	O
be	O
the	O
best	O
product	O
,	O
and	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
had	O
the	O
fastest	O
clock	O
speed	O
.	O
</s>
<s>
At	O
the	O
launch	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
Intel	O
stated	O
that	O
NetBurst-based	O
processors	O
were	O
expected	O
to	O
scale	O
to	O
10GHz	O
after	O
several	O
fabrication	B-Architecture
process	I-Architecture
generations	O
.	O
</s>
<s>
However	O
,	O
the	O
clock	O
speed	O
of	O
processors	O
using	O
the	O
NetBurst	B-Device
micro	O
architecture	O
reached	O
a	O
maximum	O
of	O
3.8GHz	O
.	O
</s>
<s>
The	O
code	O
cache	O
was	O
replaced	O
by	O
a	O
trace	B-General_Concept
cache	I-General_Concept
which	O
contained	O
decoded	O
microoperations	O
rather	O
than	O
instructions	O
with	O
advantage	O
of	O
eliminating	O
instruction	O
decoding	O
bottleneck	O
so	O
that	O
the	O
design	O
can	O
use	O
RISC	O
technology	O
.	O
</s>
<s>
These	O
solutions	O
failed	O
,	O
and	O
from	O
2003	O
to	O
2005	O
,	O
Intel	O
shifted	O
development	O
away	O
from	O
NetBurst	B-Device
to	O
focus	O
on	O
the	O
cooler-running	O
Pentium	B-Architecture
M	I-Architecture
microarchitecture	O
.	O
</s>
<s>
The	O
final	O
NetBurst-derived	O
products	O
were	O
released	O
in	O
2007	O
,	O
with	O
all	O
subsequent	O
product	O
families	O
switching	O
exclusively	O
to	O
the	O
Core	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
According	O
to	O
Bob	O
Bentley	O
,	O
presenting	O
on	O
behalf	O
of	O
Intel	O
at	O
the	O
38th	O
annual	O
Design	O
Automation	O
Conference	O
,	O
"	O
The	O
microarchitecture	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
processor	O
is	O
significantly	O
more	O
complex	O
than	O
any	O
previous	O
IA-32	O
microprocessor	O
,	O
so	O
the	O
challenge	O
of	O
validating	O
the	O
logical	O
correctness	O
of	O
the	O
design	O
in	O
a	O
timely	O
fashion	O
was	O
indeed	O
a	O
daunting	O
one.	O
"	O
</s>
<s>
Pentium	B-General_Concept
4	I-General_Concept
processors	O
have	O
an	O
integrated	O
heat	O
spreader	O
(	O
IHS	O
)	O
that	O
prevents	O
the	O
die	O
from	O
accidentally	O
being	O
damaged	O
when	O
mounting	O
and	O
unmounting	O
cooling	O
solutions	O
.	O
</s>
<s>
Prior	O
to	O
the	O
IHS	O
,	O
a	O
CPU	B-Device
shim	I-Device
was	O
sometimes	O
used	O
by	O
people	O
worried	O
about	O
damaging	O
the	O
core	O
.	O
</s>
<s>
Overclockers	O
sometimes	O
removed	O
the	O
IHS	O
from	O
Socket	B-Device
423	I-Device
and	O
Socket	B-Device
478	I-Device
chips	O
to	O
allow	O
for	O
more	O
direct	O
heat	O
transfer	O
.	O
</s>
<s>
On	O
Socket	B-Device
478	I-Device
Prescott	O
processors	O
and	O
processors	O
using	O
the	O
Socket	O
LGA	B-Device
775	I-Device
(	O
Socket	B-Device
T	I-Device
)	O
interface	O
,	O
the	O
IHS	O
is	O
directly	O
soldered	O
to	O
the	O
die	O
or	O
dies	O
,	O
making	O
it	O
difficult	O
to	O
remove	O
.	O
</s>
<s>
Willamette	O
,	O
the	O
project	O
codename	O
for	O
the	O
first	O
NetBurst	B-Device
microarchitecture	I-Device
implementation	O
,	O
experienced	O
long	O
delays	O
in	O
the	O
completion	O
of	O
its	O
design	O
process	O
.	O
</s>
<s>
However	O
,	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
was	O
released	O
while	O
Willamette	O
was	O
still	O
being	O
finished	O
.	O
</s>
<s>
Due	O
to	O
the	O
radical	O
differences	O
between	O
the	O
P6	B-Device
and	O
NetBurst	B-Device
microarchitectures	O
,	O
Intel	O
could	O
not	O
market	O
Willamette	O
as	O
a	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
so	O
it	O
was	O
marketed	O
as	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
On	O
November	O
20	O
,	O
2000	O
,	O
Intel	O
released	O
the	O
Willamette-based	O
Pentium	B-General_Concept
4	I-General_Concept
clocked	O
at	O
1.4	O
and	O
1.5GHz	O
.	O
</s>
<s>
According	O
to	O
these	O
experts	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
released	O
because	O
the	O
competing	O
Thunderbird-based	O
AMD	B-Architecture
Athlon	I-Architecture
was	O
outperforming	O
the	O
aging	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
and	O
further	O
improvements	O
to	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
were	O
not	O
yet	O
possible	O
.	O
</s>
<s>
This	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
produced	O
using	O
a	O
180nm	O
process	O
and	O
initially	O
used	O
Socket	B-Device
423	I-Device
(	O
also	O
called	O
socket	O
W	O
,	O
for	O
"	O
Willamette	O
"	O
)	O
,	O
with	O
later	O
revisions	O
moving	O
to	O
Socket	B-Device
478	I-Device
(	O
socket	B-Device
N	I-Device
,	O
for	O
"	O
Northwood	O
"	O
)	O
.	O
</s>
<s>
On	O
the	O
test	O
bench	O
,	O
the	O
Willamette	O
was	O
somewhat	O
disappointing	O
to	O
analysts	O
in	O
that	O
not	O
only	O
was	O
it	O
unable	O
to	O
outperform	O
the	O
Athlon	B-Architecture
and	O
the	O
highest-clocked	O
Pentium	B-General_Concept
IIIs	I-General_Concept
in	O
all	O
testing	O
situations	O
,	O
but	O
it	O
was	O
not	O
superior	O
to	O
the	O
budget	O
segment	O
's	O
AMD	O
Duron	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
III	I-General_Concept
remained	O
Intel	O
's	O
top	O
selling	O
processor	O
line	O
,	O
with	O
the	O
Athlon	B-Architecture
also	O
selling	O
slightly	O
better	O
than	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
While	O
Intel	O
bundled	O
two	O
RDRAM	O
modules	O
with	O
each	O
boxed	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
it	O
did	O
not	O
facilitate	O
Pentium	B-General_Concept
4	I-General_Concept
sales	O
and	O
was	O
not	O
considered	O
a	O
true	O
solution	O
by	O
many	O
.	O
</s>
<s>
In	O
April	O
2001	O
a	O
1.7GHz	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
launched	O
,	O
the	O
first	O
model	O
to	O
provide	O
performance	O
clearly	O
superior	O
to	O
the	O
old	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
July	O
saw	O
1.6	O
and	O
1.8GHz	O
models	O
and	O
in	O
August	O
2001	O
,	O
Intel	O
released	O
1.9	O
and	O
2GHz	O
Pentium	B-General_Concept
4s	I-General_Concept
.	O
</s>
<s>
The	O
fact	O
that	O
SDRAM	O
was	O
so	O
much	O
cheaper	O
caused	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
sales	O
to	O
grow	O
considerably	O
.	O
</s>
<s>
The	O
new	O
chipset	O
allowed	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
to	O
quickly	O
replace	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
becoming	O
the	O
top-selling	O
mainstream	O
processor	O
on	O
the	O
market	O
.	O
</s>
<s>
In	O
January	O
2002	O
,	O
Intel	O
released	O
Pentium	B-General_Concept
4s	I-General_Concept
with	O
a	O
new	O
core	O
code	O
named	O
"	O
Northwood	O
"	O
at	O
speeds	O
of	O
1.6GHz	O
,	O
1.8GHz	O
,	O
2GHz	O
and	O
2.2GHz	O
.	O
</s>
<s>
Northwood	O
(	O
product	O
code	O
80532	O
)	O
combined	O
an	O
increase	O
in	O
the	O
L2cache	O
size	O
from	O
256KB	O
to	O
512KB	O
(	O
increasing	O
the	O
transistor	O
count	O
from	O
42	O
million	O
to	O
55	O
million	O
)	O
with	O
a	O
transition	O
to	O
a	O
new	O
130nm	O
fabrication	B-Architecture
process	I-Architecture
.	O
</s>
<s>
In	O
the	O
same	O
month	O
boards	O
utilizing	O
the	O
845	O
chipset	O
were	O
released	O
with	O
enabled	O
support	O
for	O
DDR	O
SDRAM	O
which	O
provided	O
double	O
the	O
bandwidth	O
of	O
PC133	O
SDRAM	O
,	O
and	O
alleviated	O
the	O
associated	O
high	O
costs	O
of	O
using	O
Rambus	O
RDRAM	O
for	O
maximal	O
performance	O
with	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
A	O
2.4GHz	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
released	O
on	O
April	O
2	O
,	O
2002	O
,	O
and	O
the	O
bus	O
speed	O
increased	O
from	O
400MT/s	O
to	O
533MT/s	O
(	O
133MHz	O
physical	O
clock	O
)	O
for	O
the	O
2.26GHz	O
,	O
2.4GHz	O
,	O
and	O
2.53GHz	O
models	O
in	O
May	O
,	O
2.66GHz	O
and	O
2.8GHz	O
models	O
in	O
August	O
,	O
and	O
3.06GHz	O
model	O
in	O
November	O
.	O
</s>
<s>
With	O
Northwood	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
came	O
of	O
age	O
.	O
</s>
<s>
The	O
battle	O
for	O
performance	O
leadership	O
remained	O
competitive	O
(	O
as	O
AMD	O
introduced	O
faster	O
versions	O
of	O
the	O
Athlon	B-Architecture
XP	O
)	O
but	O
most	O
observers	O
agreed	O
that	O
the	O
fastest-clocked	O
Northwood-based	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
usually	O
ahead	O
of	O
its	O
rival	O
.	O
</s>
<s>
This	O
was	O
particularly	O
so	O
in	O
mid-2002	O
,	O
when	O
AMD	O
's	O
changeover	O
to	O
its	O
130nm	O
production	O
process	O
did	O
not	O
help	O
the	O
initial	O
"	O
Thoroughbred	O
A	O
"	O
revision	O
Athlon	B-Architecture
XP	O
CPUs	O
to	O
clock	O
high	O
enough	O
to	O
overcome	O
the	O
advantages	O
of	O
Northwood	O
in	O
the	O
2.4	O
to	O
2.8GHz	O
range	O
.	O
</s>
<s>
The	O
3.06GHz	O
Pentium	B-General_Concept
4	I-General_Concept
enabled	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
that	O
was	O
first	O
supported	O
in	O
Foster-based	O
Xeons	B-Device
.	O
</s>
<s>
This	O
began	O
the	O
convention	O
of	O
virtual	O
processors	O
(	O
or	O
virtual	O
cores	O
)	O
under	O
x86	B-Operating_System
by	O
enabling	O
multiple	O
threads	O
to	O
be	O
run	O
at	O
the	O
same	O
time	O
on	O
the	O
same	O
physical	O
processor	O
.	O
</s>
<s>
This	O
initial	O
3.06GHz	O
533FSB	O
Pentium	B-General_Concept
4	I-General_Concept
Hyper-Threading	B-Operating_System
enabled	O
processor	O
was	O
known	O
as	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
and	O
was	O
introduced	O
to	O
mass	O
market	O
by	O
Gateway	O
in	O
November	O
2002	O
.	O
</s>
<s>
On	O
April	O
14	O
,	O
2003	O
,	O
Intel	O
officially	O
launched	O
the	O
new	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
processor	O
.	O
</s>
<s>
This	O
processor	O
used	O
an	O
800MT/s	O
FSB	O
(	O
200MHz	O
physical	O
clock	O
)	O
,	O
was	O
clocked	O
at	O
3GHz	O
,	O
and	O
had	O
Hyper-Threading	B-Operating_System
technology	I-Operating_System
.	O
</s>
<s>
This	O
was	O
meant	O
to	O
help	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
better	O
compete	O
with	O
AMD	O
's	O
Opteron	B-General_Concept
line	O
of	O
processors	O
.	O
</s>
<s>
The	O
server-oriented	O
Opteron	B-General_Concept
initially	O
did	O
not	O
share	O
a	O
common	O
socket	O
with	O
AMD	O
's	O
desktop	B-Device
processor	O
line	O
(	O
Socket	O
A	O
)	O
.	O
</s>
<s>
Because	O
of	O
this	O
,	O
motherboard	O
manufacturers	O
did	O
not	O
initially	O
build	O
motherboards	O
with	O
AGP	B-Architecture
for	O
Opterons	B-General_Concept
.	O
</s>
<s>
As	O
AGP	B-Architecture
was	O
the	O
primary	O
graphics	O
expansion	O
port	O
for	O
desktop	B-Device
use	O
,	O
this	O
oversight	O
prevented	O
the	O
Opteron	B-General_Concept
from	O
encroaching	O
from	O
the	O
server	B-Application
market	O
and	O
threatening	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
desktop	B-Device
market	O
.	O
</s>
<s>
Meanwhile	O
,	O
with	O
the	O
launch	O
of	O
the	O
Athlon	B-Architecture
XP	O
3200+	O
in	O
AMD	O
's	O
desktop	B-Device
line	O
,	O
AMD	O
increased	O
the	O
Athlon	B-Architecture
XP	O
's	O
FSB	O
speed	O
from	O
333MT/s	O
to	O
400MT/s	O
,	O
but	O
it	O
was	O
not	O
enough	O
to	O
hold	O
off	O
the	O
new	O
3GHz	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
's	O
increase	O
to	O
a	O
200MHz	O
quad-pumped	O
bus	O
(	O
200	O
x	O
4	O
=	O
800	O
MHz	O
effective	O
)	O
greatly	O
helped	O
to	O
satisfy	O
the	O
bandwidth	O
requirements	O
the	O
NetBurst	B-Device
architecture	O
desired	O
for	O
reaching	O
optimal	O
performance	O
.	O
</s>
<s>
While	O
the	O
Athlon	B-Architecture
XP	O
architecture	O
was	O
less	O
dependent	O
on	O
bandwidth	O
,	O
the	O
bandwidth	O
numbers	O
reached	O
by	O
Intel	O
were	O
well	O
out	O
of	O
range	O
for	O
the	O
Athlon	B-Architecture
's	O
EV6	O
bus	O
.	O
</s>
<s>
Intel	O
's	O
higher	O
bandwidth	O
proved	O
useful	O
in	O
benchmarks	O
for	O
streaming	O
operations	O
,	O
and	O
Intel	O
marketing	O
wisely	O
capitalized	O
on	O
this	O
as	O
a	O
tangible	O
improvement	O
over	O
AMD	O
's	O
desktop	B-Device
processors	O
.	O
</s>
<s>
Also	O
based	O
on	O
the	O
Northwood	O
core	O
,	O
the	O
Mobile	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
Processor	O
-	O
M	O
was	O
released	O
on	O
April	O
23	O
,	O
2002	O
and	O
included	O
Intel	O
's	O
SpeedStep	B-Device
and	O
Deeper	O
Sleep	O
technologies	O
.	O
</s>
<s>
There	O
was	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
mobile	O
chip	O
,	O
the	O
Mobile	B-Architecture
Pentium	I-Architecture
4-M	O
,	O
the	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
,	O
and	O
then	O
just	O
the	O
Pentium	B-Architecture
M	I-Architecture
which	O
itself	O
was	O
based	O
on	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
and	O
significantly	O
faster	O
than	O
the	O
former	O
three	O
.	O
</s>
<s>
Its	O
TDP	B-General_Concept
is	O
about	O
35	O
watts	O
in	O
most	O
applications	O
.	O
</s>
<s>
Unlike	O
the	O
desktop	B-Device
Pentium	B-General_Concept
4	I-General_Concept
,	O
the	O
Pentium	O
4-M	O
did	O
not	O
feature	O
an	O
integrated	O
heat	O
spreader	O
(	O
IHS	O
)	O
,	O
and	O
it	O
operates	O
at	O
a	O
lower	O
voltage	O
.	O
</s>
<s>
However	O
,	O
according	O
to	O
Intel	O
specifications	O
,	O
the	O
Pentium	O
4-M	O
had	O
a	O
maximum	O
thermal	O
junction	O
temperature	O
rating	O
of	O
100	O
degrees	O
C	O
,	O
approximately	O
40	O
degrees	O
higher	O
than	O
the	O
desktop	B-Device
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
The	O
Mobile	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
Processor	O
was	O
released	O
to	O
address	O
the	O
problem	O
of	O
putting	O
a	O
full	O
desktop	B-Device
Pentium	B-General_Concept
4	I-General_Concept
processor	O
into	O
a	O
laptop	B-Device
,	O
which	O
some	O
manufacturers	O
were	O
doing	O
.	O
</s>
<s>
The	O
Mobile	B-Architecture
Pentium	I-Architecture
4	I-General_Concept
used	O
a	O
533MT/s	O
FSB	O
,	O
following	O
the	O
desktop	B-Device
Pentium	B-General_Concept
4	I-General_Concept
's	O
evolution	O
.	O
</s>
<s>
Oddly	O
,	O
increasing	O
the	O
bus	O
speed	O
by	O
133MT/s	O
(	O
33MHz	O
)	O
caused	O
a	O
massive	O
increase	O
in	O
TDPs	O
,	O
as	O
mobile	B-Architecture
Pentium	I-Architecture
4	I-General_Concept
processors	O
emitted	O
59.8	O
–	O
70	O
W	O
of	O
heat	O
,	O
with	O
the	O
Hyper-Threading	B-Operating_System
variants	O
emitting	O
66.1	O
–	O
88	O
W	O
.	O
This	O
allowed	O
the	O
mobile	B-Architecture
Pentium	I-Architecture
4	I-General_Concept
to	O
bridge	O
the	O
gap	O
between	O
the	O
desktop	B-Device
Pentium	B-General_Concept
4	I-General_Concept
(	O
up	O
to	O
115	O
W	O
TDP	B-General_Concept
)	O
,	O
and	O
the	O
Pentium	O
4-M	O
(	O
up	O
to	O
35	O
W	O
TDP	B-General_Concept
)	O
.	O
</s>
<s>
In	O
September	O
2003	O
,	O
at	O
the	O
Intel	O
Developer	O
Forum	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
(	O
P4EE	O
)	O
was	O
announced	O
,	O
just	O
over	O
a	O
week	O
before	O
the	O
launch	O
of	O
Athlon	B-Architecture
64	O
and	O
Athlon	B-Architecture
64	O
FX	O
.	O
</s>
<s>
The	O
design	O
was	O
mostly	O
identical	O
to	O
Pentium	B-General_Concept
4	I-General_Concept
(	O
to	O
the	O
extent	O
that	O
it	O
would	O
run	O
in	O
the	O
same	O
motherboards	O
)	O
,	O
but	O
differed	O
by	O
an	O
added	O
2MB	O
of	O
level	O
3	O
cache	O
.	O
</s>
<s>
It	O
shared	O
the	O
same	O
Gallatin	O
core	O
as	O
the	O
Xeon	B-Device
MP	I-Device
,	O
though	O
in	O
a	O
Socket	B-Device
478	I-Device
form	O
factor	O
(	O
as	O
opposed	O
to	O
Socket	O
603	O
for	O
the	O
Xeon	B-Device
MP	I-Device
)	O
and	O
with	O
an	O
800MT/s	O
bus	O
,	O
twice	O
as	O
fast	O
as	O
that	O
of	O
the	O
Xeon	B-Device
MP	I-Device
.	O
</s>
<s>
While	O
Intel	O
maintained	O
that	O
the	O
Extreme	B-Device
Edition	I-Device
was	O
aimed	O
at	O
gamers	O
,	O
critics	O
viewed	O
it	O
as	O
an	O
attempt	O
to	O
steal	O
the	O
Athlon	B-Architecture
64	O
's	O
launch	O
thunder	O
,	O
nicknaming	O
it	O
the	O
"	O
Emergency	O
Edition	O
"	O
.	O
</s>
<s>
Multimedia	O
encoding	O
and	O
certain	O
games	O
benefited	O
the	O
most	O
,	O
with	O
the	O
Extreme	B-Device
Edition	I-Device
outperforming	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
and	O
even	O
the	O
two	O
Athlon	B-Architecture
64	O
variants	O
,	O
although	O
the	O
lower	O
price	O
and	O
more	O
balanced	O
performance	O
of	O
the	O
Athlon	B-Architecture
64	O
(	O
particularly	O
the	O
non-FX	O
version	O
)	O
led	O
to	O
it	O
usually	O
being	O
seen	O
as	O
the	O
better	O
value	O
proposition	O
.	O
</s>
<s>
Nonetheless	O
,	O
the	O
Extreme	B-Device
Edition	I-Device
did	O
achieve	O
Intel	O
's	O
apparent	O
aim	O
,	O
which	O
was	O
to	O
prevent	O
AMD	O
from	O
being	O
the	O
performance	O
champion	O
with	O
the	O
new	O
Athlon	B-Architecture
64	O
,	O
which	O
was	O
winning	O
every	O
single	O
major	O
benchmark	O
over	O
the	O
existing	O
Pentium	B-General_Concept
4s	I-General_Concept
.	O
</s>
<s>
In	O
January	O
2004	O
,	O
a	O
3.4GHz	O
version	O
was	O
released	O
for	O
Socket	B-Device
478	I-Device
,	O
and	O
in	O
Summer	O
2004	O
the	O
CPU	B-General_Concept
was	O
released	O
using	O
the	O
new	O
Socket	B-Device
775	I-Device
.	O
</s>
<s>
A	O
slight	O
performance	O
increase	O
was	O
achieved	O
in	O
late	O
2004	O
by	O
increasing	O
the	O
bus	O
speed	O
from	O
800MT/s	O
to	O
1066MT/s	O
,	O
resulting	O
in	O
a	O
3.46GHz	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
.	O
</s>
<s>
By	O
most	O
metrics	O
,	O
this	O
was	O
on	O
a	O
per-clock	O
basis	O
the	O
fastest	O
single-core	O
NetBurst	B-Device
processor	O
that	O
was	O
ever	O
produced	O
,	O
even	O
outperforming	O
many	O
of	O
its	O
successor	O
chips	O
(	O
not	O
counting	O
the	O
dual-core	B-Architecture
Pentium	B-Device
D	I-Device
)	O
.	O
</s>
<s>
Afterwards	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
was	O
migrated	O
to	O
the	O
Prescott	O
core	O
.	O
</s>
<s>
The	O
new	O
3.73GHz	O
Extreme	B-Device
Edition	I-Device
had	O
the	O
same	O
features	O
as	O
a	O
6x0-sequence	O
Prescott	O
2M	O
,	O
but	O
with	O
a	O
1066MT/s	O
bus	O
.	O
</s>
<s>
In	O
practice	O
however	O
,	O
the	O
3.73GHz	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
almost	O
always	O
proved	O
to	O
be	O
slower	O
than	O
the	O
3.46GHz	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
,	O
which	O
is	O
most	O
likely	O
due	O
to	O
the	O
lack	O
of	O
an	O
L3	O
cache	O
and	O
the	O
longer	O
instruction	O
pipeline	O
.	O
</s>
<s>
The	O
only	O
advantage	O
the	O
3.73GHz	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
had	O
over	O
the	O
3.46GHz	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
was	O
the	O
ability	O
to	O
run	O
64-bit	B-Device
applications	O
since	O
all	O
Gallatin-based	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
processors	O
lacked	O
the	O
Intel	O
64	O
instruction	O
set	O
.	O
</s>
<s>
Although	O
never	O
a	O
particularly	O
good	O
seller	O
,	O
especially	O
since	O
it	O
was	O
released	O
in	O
a	O
time	O
when	O
AMD	O
was	O
asserting	O
near	O
total	O
dominance	O
in	O
the	O
processor	O
performance	O
race	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
established	O
a	O
new	O
position	O
within	O
Intel	O
's	O
product	O
line	O
,	O
that	O
of	O
an	O
enthusiast	O
oriented	O
chip	O
with	O
the	O
highest-end	O
specifications	O
offered	O
by	O
Intel	O
chips	O
,	O
along	O
with	O
unlocked	O
multipliers	O
to	O
allow	O
for	O
easier	O
overclocking	O
.	O
</s>
<s>
In	O
this	O
role	O
it	O
has	O
since	O
been	O
succeeded	O
by	O
the	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
(	O
The	O
Extreme	O
version	O
of	O
the	O
dual-core	B-Architecture
Pentium	B-Device
D	I-Device
)	O
,	O
the	O
Core	B-Device
2	I-Device
Extreme	O
,	O
the	O
Core	B-Device
i7	I-Device
and	O
the	O
Core	B-Device
i9	I-Device
.	O
</s>
<s>
Contrary	O
to	O
popular	O
belief	O
,	O
however	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
for	O
Socket	B-Device
478	I-Device
has	O
a	O
locked	O
multiplier	O
,	O
meaning	O
that	O
these	O
are	O
not	O
overclockable	O
.	O
</s>
<s>
Only	O
the	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
(	O
Smithfield	B-Device
)	O
and	O
Engineering	O
Sample	O
CPUs	O
have	O
unlocked	O
multipliers	O
.	O
</s>
<s>
The	O
core	O
used	O
the	O
90	O
nm	O
process	O
for	O
the	O
first	O
time	O
,	O
which	O
one	O
analyst	O
described	O
as	O
"	O
a	O
major	O
reworking	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
microarchitecture.	O
"	O
</s>
<s>
Some	O
programs	O
benefited	O
from	O
Prescott	O
's	O
doubled	O
cache	O
and	O
SSE3	B-General_Concept
instructions	O
,	O
whereas	O
others	O
were	O
harmed	O
by	O
its	O
longer	O
pipeline	O
.	O
</s>
<s>
The	O
fastest	O
mass-produced	O
Prescott-based	O
Pentium	B-General_Concept
4s	I-General_Concept
were	O
clocked	O
at	O
3.8GHz	O
.	O
</s>
<s>
In	O
fact	O
,	O
Prescott	O
's	O
power	O
and	O
heat	O
characteristics	O
were	O
only	O
slightly	O
higher	O
than	O
those	O
of	O
Northwood	O
of	O
the	O
same	O
speed	O
and	O
nearly	O
equal	O
to	O
the	O
Gallatin-based	O
Extreme	B-Device
Editions	I-Device
,	O
but	O
since	O
those	O
processors	O
had	O
already	O
been	O
operating	O
near	O
the	O
limits	O
of	O
what	O
was	O
considered	O
thermally	O
acceptable	O
,	O
this	O
still	O
posed	O
a	O
major	O
issue	O
.	O
</s>
<s>
The	O
"	O
Prescott	O
"	O
Pentium	B-General_Concept
4	I-General_Concept
contains	O
125	O
million	O
transistors	O
and	O
has	O
a	O
die	O
area	O
of	O
112mm2	O
.	O
</s>
<s>
The	O
process	O
has	O
features	O
such	O
as	O
strained	O
silicon	O
transistors	O
and	O
Low-κ	B-Algorithm
carbon-doped	O
silicon	O
oxide	O
(	O
CDO	O
)	O
dielectric	O
,	O
which	O
is	O
also	O
known	O
as	O
organosilicate	O
glass	O
(	O
OSG	O
)	O
.	O
</s>
<s>
The	O
Prescott	O
was	O
first	O
fabricated	O
at	O
the	O
D1C	O
development	O
fab	B-Algorithm
and	O
was	O
later	O
moved	O
to	O
F11X	O
production	O
fab	B-Algorithm
.	O
</s>
<s>
Originally	O
,	O
Intel	O
released	O
two	O
Prescott	O
lines	O
on	O
Socket	B-Device
478	I-Device
:	O
the	O
E-series	O
,	O
with	O
an	O
800MT/s	O
FSB	O
and	O
Hyper-Threading	B-Operating_System
support	O
,	O
and	O
the	O
low-end	O
A-series	O
,	O
with	O
a	O
533MT/s	O
FSB	O
and	O
Hyper-Threading	B-Operating_System
disabled	O
.	O
</s>
<s>
LGA	B-Device
775	I-Device
Prescott	O
CPUs	O
use	O
a	O
rating	O
system	O
,	O
labeling	O
them	O
as	O
the	O
5xx	O
series	O
(	O
Celeron	B-Device
Ds	O
are	O
the	O
3xx	O
series	O
,	O
while	O
Pentium	B-Architecture
Ms	I-Architecture
are	O
the	O
7xx	O
series	O
)	O
.	O
</s>
<s>
The	O
LGA	B-Device
775	I-Device
version	O
of	O
the	O
E-series	O
uses	O
model	O
numbers	O
5x0	O
(	O
520	O
–	O
560	O
)	O
,	O
and	O
the	O
LGA	B-Device
775	I-Device
version	O
of	O
the	O
A-series	O
uses	O
model	O
numbers	O
5x5	O
and	O
5x9	O
(	O
505	O
–	O
519	O
)	O
.	O
</s>
<s>
Plans	O
to	O
mass-produce	O
a	O
4GHz	O
Pentium	B-General_Concept
4	I-General_Concept
were	O
cancelled	O
by	O
Intel	O
in	O
favor	O
of	O
dual	B-Architecture
core	I-Architecture
processors	I-Architecture
,	O
although	O
some	O
European	O
retailers	O
claimed	O
to	O
be	O
selling	O
a	O
Pentium	B-General_Concept
4	I-General_Concept
580	O
,	O
clocked	O
at	O
4GHz	O
.	O
</s>
<s>
The	O
E-series	O
Prescott	O
,	O
as	O
well	O
as	O
the	O
low-end	O
517	O
and	O
524	O
,	O
incorporates	O
Hyper-Threading	B-Operating_System
in	O
order	O
to	O
speed	O
up	O
some	O
processes	O
that	O
use	O
multithreaded	O
software	O
,	O
such	O
as	O
video	O
editing	O
.	O
</s>
<s>
The	O
Prescott	O
microarchitecture	O
was	O
designed	O
to	O
support	O
Intel	O
64	O
,	O
Intel	O
's	O
implementation	O
of	O
the	O
AMD-developed	O
x86-64	B-Device
64-bit	B-Device
extensions	O
to	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
but	O
the	O
initial	O
models	O
shipped	O
with	O
their	O
64-bit	B-Device
capability	O
disabled	O
.	O
</s>
<s>
Intel	O
stated	O
that	O
it	O
did	O
not	O
intend	O
to	O
release	O
64-bit	B-Device
CPUs	O
in	O
retail	O
channels	O
,	O
instead	O
releasing	O
the	O
64-bit	B-Device
capable	O
F-series	O
to	O
OEMs	O
only	O
.	O
</s>
<s>
The	O
E0	O
stepping	O
of	O
the	O
Prescott	O
series	O
introduced	O
the	O
XD	B-General_Concept
bit	I-General_Concept
feature	O
.	O
</s>
<s>
This	O
technology	O
,	O
introduced	O
to	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
by	O
AMD	O
as	O
NX	O
(	O
No	B-General_Concept
eXecute	I-General_Concept
)	O
,	O
can	O
help	O
prevent	O
certain	O
types	O
of	O
malicious	O
code	O
from	O
exploiting	O
a	O
buffer	B-General_Concept
overflow	I-General_Concept
to	O
get	O
executed	O
.	O
</s>
<s>
Models	O
supporting	O
XD	B-General_Concept
bit	I-General_Concept
include	O
the	O
5x0J	O
and	O
5x1	O
series	O
as	O
well	O
as	O
the	O
low-end	O
5x5J	O
and	O
5x6	O
.	O
</s>
<s>
Prescott	O
2M	O
is	O
also	O
sometimes	O
known	O
by	O
the	O
name	O
of	O
its	O
Xeon	B-Device
derivative	O
,	O
"	O
Irwindale	O
"	O
.	O
</s>
<s>
It	O
features	O
Hyper-Threading	B-Operating_System
,	O
Intel	O
64	O
,	O
the	O
XDbit	O
,	O
EIST	B-Device
(	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
)	O
,	O
Thermal	B-Device
Monitor	I-Device
2	I-Device
(	O
for	O
processors	O
at	O
3.6GHz	O
and	O
above	O
)	O
,	O
and	O
2MB	O
of	O
L2	O
cache	O
.	O
</s>
<s>
Rather	O
than	O
being	O
a	O
targeted	O
speed	O
boost	O
the	O
double	O
size	O
cache	O
was	O
intended	O
to	O
provide	O
the	O
same	O
space	O
and	O
hence	O
performance	O
for	O
64-bit	B-Device
mode	O
operations	O
,	O
due	O
to	O
the	O
doubled	O
word	O
size	O
compared	O
to	O
32-bit	O
mode	O
.	O
</s>
<s>
On	O
November	O
14	O
,	O
2005	O
,	O
Intel	O
released	O
Prescott	O
2M	O
processors	O
with	O
VT	O
(	O
Virtualization	B-General_Concept
Technology	O
,	O
codenamed	O
"	O
Vanderpool	O
"	O
)	O
enabled	O
.	O
</s>
<s>
The	O
final	O
revision	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
Cedar	O
Mill	O
,	O
released	O
on	O
January	O
5	O
,	O
2006	O
.	O
</s>
<s>
The	O
Cedar	O
Mill	O
is	O
closely	O
linked	O
to	O
the	O
Pentium	B-Device
D	I-Device
Presler	B-Device
revision	O
,	O
with	O
each	O
Presler	B-Device
CPU	B-General_Concept
consisting	O
of	O
two	O
Cedar	O
Mill	O
cores	O
on	O
the	O
same	O
chip	O
package	O
.	O
</s>
<s>
Cedar	O
Mill	O
had	O
a	O
lower	O
heat	O
output	O
than	O
Prescott	O
,	O
with	O
a	O
TDP	B-General_Concept
of	O
86W	O
.	O
</s>
<s>
It	O
has	O
a	O
65nm	O
core	O
and	O
features	O
the	O
same	O
31-stage	O
pipeline	O
as	O
Prescott	O
,	O
800MT/s	O
FSB	O
,	O
Intel	O
64	O
,	O
Hyper-Threading	B-Operating_System
,	O
but	O
no	O
Virtualization	B-General_Concept
Technology	O
.	O
</s>
<s>
The	O
original	O
successor	O
to	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
was	O
(	O
codenamed	O
)	O
Tejas	B-Device
,	O
which	O
was	O
scheduled	O
for	O
an	O
early-mid-2005	O
release	O
.	O
</s>
<s>
However	O
,	O
it	O
was	O
cancelled	O
a	O
few	O
months	O
after	O
the	O
release	O
of	O
Prescott	O
due	O
to	O
extremely	O
high	O
TDPs	O
(	O
a	O
2.8GHz	O
Tejas	B-Device
emitted	O
150	O
W	O
of	O
heat	O
,	O
compared	O
to	O
around	O
80	O
W	O
for	O
a	O
Northwood	O
of	O
the	O
same	O
speed	O
,	O
and	O
100	O
W	O
for	O
a	O
comparably	O
clocked	O
Prescott	O
)	O
and	O
development	O
on	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
as	O
a	O
whole	O
ceased	O
,	O
with	O
the	O
exception	O
of	O
the	O
dual-core	B-Architecture
Pentium	B-Device
D	I-Device
,	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
and	O
the	O
Cedar	O
Mill-based	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
.	O
</s>
<s>
In	O
May	O
2005	O
,	O
Intel	O
released	O
dual-core	B-Architecture
processors	I-Architecture
under	O
the	O
Pentium	B-Device
D	I-Device
and	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
brands	O
.	O
</s>
<s>
These	O
came	O
under	O
the	O
code	O
names	O
Smithfield	B-Device
and	O
Presler	B-Device
for	O
the	O
90nm	O
and	O
65nm	O
parts	O
respectively	O
.	O
</s>
<s>
The	O
real	O
successor	O
to	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
brand	O
is	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
brand	O
,	O
which	O
merged	O
with	O
Pentium	B-Device
D	I-Device
,	O
released	O
on	O
July	O
27	O
,	O
2006	O
.	O
</s>
<s>
The	O
underlying	O
microarchitecture	O
is	O
the	O
Core	B-Device
microarchitecture	I-Device
,	O
and	O
the	O
first	O
chips	O
implementing	O
it	O
(	O
in	O
65nm	O
)	O
are	O
called	O
"	O
Conroe	O
"	O
.	O
</s>
<s>
Intel	B-Device
Core	I-Device
2	I-Device
processors	O
were	O
released	O
as	O
single-	O
,	O
dual	O
-	O
and	O
quad-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Processors	O
implementing	O
the	O
Core	B-Device
microarchitecture	I-Device
were	O
marketed	O
under	O
the	O
"	O
Core	B-Device
2	I-Device
"	O
-brand	O
,	O
because	O
processors	O
based	O
on	O
the	O
Yonah-microarchitecture	O
had	O
already	O
been	O
marketed	O
under	O
the	O
Core-brand	O
.	O
</s>
