<s>
The	O
Pentium	B-General_Concept
(	O
also	O
referred	O
to	O
as	O
P5	B-General_Concept
,	O
its	O
microarchitecture	B-General_Concept
,	O
or	O
i586	B-General_Concept
)	O
is	O
a	O
fifth	O
generation	O
,	O
32-bit	B-Device
x86	I-Device
microprocessor	B-Architecture
that	O
was	O
introduced	O
by	O
Intel	O
on	O
March	O
22	O
,	O
1993	O
,	O
as	O
the	O
very	O
first	O
CPU	O
in	O
the	O
Pentium	B-General_Concept
brand	I-General_Concept
.	O
</s>
<s>
It	O
was	O
instruction	B-General_Concept
set	I-General_Concept
compatible	O
with	O
the	O
80486	B-General_Concept
but	O
was	O
a	O
new	O
and	O
very	O
different	O
microarchitecture	B-General_Concept
design	O
from	O
previous	O
iterations	O
.	O
</s>
<s>
The	O
P5	B-General_Concept
Pentium	B-General_Concept
was	O
the	O
first	O
superscalar	B-General_Concept
x86	B-Operating_System
microarchitecture	B-General_Concept
and	O
the	O
world	O
's	O
first	O
superscalar	B-General_Concept
microprocessor	B-Architecture
to	O
be	O
in	O
mass	O
productionmeaning	O
it	O
generally	O
executes	O
at	O
least	O
2	O
instructions	O
per	O
clock	O
mainly	O
because	O
of	O
a	O
design-first	O
dual	O
integer	O
pipeline	B-General_Concept
design	I-General_Concept
previously	O
thought	O
impossible	O
to	O
implement	O
on	O
a	O
CISC	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
Additional	O
features	O
include	O
a	O
faster	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
wider	O
data	B-General_Concept
bus	I-General_Concept
,	O
separate	O
code	O
and	O
data	B-General_Concept
caches	I-General_Concept
,	O
and	O
many	O
other	O
techniques	O
and	O
features	O
to	O
enhance	O
performance	O
and	O
support	O
security	O
,	O
encryption	O
,	O
and	O
multiprocessing	O
,	O
for	O
workstations	O
and	O
servers	O
when	O
compared	O
to	O
the	O
next	O
best	O
previous	O
industry	O
standard	O
processor	O
implementation	O
before	O
it	O
,	O
the	O
Intel	B-General_Concept
80486	I-General_Concept
.	O
</s>
<s>
Considered	O
the	O
fifth	O
main	O
generation	O
in	O
the	O
8086	O
compatible	O
line	O
of	O
processors	O
,	O
its	O
implementation	O
and	O
microarchitecture	B-General_Concept
was	O
called	O
P5	B-General_Concept
.	O
</s>
<s>
As	O
with	O
all	O
new	O
processors	O
from	O
Intel	O
since	O
the	O
Pentium	B-General_Concept
,	O
some	O
new	O
instructions	O
were	O
added	O
to	O
enhance	O
performance	O
for	O
specific	O
types	O
of	O
workloads	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
was	O
the	O
first	O
Intel	B-Operating_System
x86	I-Operating_System
to	O
build	O
in	O
robust	O
hardware	O
support	O
for	O
multiprocessing	O
similar	O
to	O
that	O
of	O
large	O
IBM	O
mainframe	O
computers	O
.	O
</s>
<s>
Intel	O
worked	O
closely	O
with	O
IBM	O
to	O
define	O
this	O
ability	O
and	O
then	O
Intel	O
designed	O
it	O
into	O
the	O
P5	B-General_Concept
microarchitecture	B-General_Concept
.	O
</s>
<s>
This	O
new	O
ability	O
was	O
absent	O
in	O
prior	O
x86	B-Operating_System
generations	O
and	O
x86	B-Operating_System
copies	O
from	O
competitors	O
.	O
</s>
<s>
To	O
realize	O
its	O
greatest	O
potential	O
,	O
compilers	O
had	O
to	O
be	O
optimized	O
to	O
exploit	O
the	O
instruction	O
level	O
parallelism	O
provided	O
by	O
the	O
new	O
superscalar	B-General_Concept
dual	O
pipelines	B-General_Concept
and	O
applications	O
needed	O
to	O
be	O
recompiled	O
.	O
</s>
<s>
Intel	O
spent	O
substantial	O
effort	O
and	O
resources	O
working	O
with	O
development	O
tool	O
vendors	O
,	O
and	O
major	O
independent	B-Application
software	I-Application
vendor	I-Application
(	O
ISV	O
)	O
and	O
operating	B-General_Concept
system	I-General_Concept
(	O
OS	O
)	O
companies	O
to	O
optimize	O
their	O
products	O
for	O
Pentium	B-General_Concept
before	O
product	O
launch	O
.	O
</s>
<s>
In	O
October	O
1996	O
,	O
the	O
similar	O
Pentium	B-General_Concept
MMX	B-Architecture
was	O
introduced	O
,	O
complementing	O
the	O
same	O
basic	O
microarchitecture	B-General_Concept
with	O
the	O
MMX	B-Architecture
instruction	I-Architecture
set	I-Architecture
,	O
larger	O
caches	O
,	O
and	O
some	O
other	O
enhancements	O
.	O
</s>
<s>
Competitors	O
included	O
the	O
Motorola	B-Device
68040	I-Device
,	O
Motorola	B-General_Concept
68060	I-General_Concept
,	O
PowerPC	O
601	O
,	O
and	O
the	O
SPARC	B-Architecture
,	O
MIPS	B-Device
,	O
Alpha	B-Device
families	O
,	O
most	O
of	O
which	O
also	O
used	O
a	O
superscalar	B-General_Concept
in-order	O
dual	O
instruction	O
pipeline	B-General_Concept
configuration	O
at	O
some	O
time	O
.	O
</s>
<s>
Intel	O
discontinued	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
processors	O
(	O
sold	O
as	O
a	O
cheaper	O
product	O
since	O
the	O
release	O
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
in	O
1997	O
)	O
in	O
early	O
2000	O
in	O
favor	O
of	O
the	O
Celeron	B-Device
processor	O
,	O
which	O
had	O
also	O
replaced	O
the	O
80486	B-General_Concept
brand	O
.	O
</s>
<s>
The	O
P5	B-General_Concept
microarchitecture	B-General_Concept
was	O
designed	O
by	O
the	O
same	O
Santa	O
Clara	O
team	O
which	O
designed	O
the	O
386	O
and	O
486	B-General_Concept
.	O
</s>
<s>
Design	O
work	O
started	O
in	O
1989	O
;	O
the	O
team	O
decided	O
to	O
use	O
a	O
superscalar	B-General_Concept
architecture	I-General_Concept
,	O
with	O
on-chip	B-General_Concept
cache	I-General_Concept
,	O
floating-point	O
,	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
By	O
mid-1992	O
,	O
the	O
P5	B-General_Concept
team	O
had	O
200	O
engineers	O
.	O
</s>
<s>
Intel	O
at	O
first	O
planned	O
to	O
demonstrate	O
the	O
P5	B-General_Concept
in	O
June	O
1992	O
at	O
the	O
trade	O
show	O
PC	O
Expo	O
,	O
and	O
to	O
formally	O
announce	O
the	O
processor	O
in	O
September	O
1992	O
,	O
but	O
design	O
problems	O
forced	O
the	O
demo	O
to	O
be	O
cancelled	O
,	O
and	O
the	O
official	O
introduction	O
of	O
the	O
chip	O
was	O
delayed	O
until	O
the	O
spring	O
of	O
1993	O
.	O
</s>
<s>
John	O
H	O
.	O
Crawford	O
,	O
chief	O
architect	O
of	O
the	O
original	O
386	O
,	O
co-managed	O
the	O
design	O
of	O
the	O
P5	B-General_Concept
,	O
along	O
with	O
Donald	O
Alpert	O
,	O
who	O
managed	O
the	O
architectural	O
team	O
.	O
</s>
<s>
Dror	O
Avnon	O
managed	O
the	O
design	O
of	O
the	O
FPU	B-General_Concept
.	O
</s>
<s>
Vinod	O
K	O
.	O
Dham	O
was	O
general	O
manager	O
of	O
the	O
P5	B-General_Concept
group	O
.	O
</s>
<s>
Intel	O
's	O
Larrabee	B-Architecture
multicore	O
architecture	O
project	O
uses	O
a	O
processor	O
core	O
derived	O
from	O
a	O
P5	B-General_Concept
core	O
(	O
P54C	O
)	O
,	O
augmented	O
by	O
multithreading	B-General_Concept
,	O
64-bit	B-Device
instructions	O
,	O
and	O
a	O
16-wide	O
vector	B-Operating_System
processing	I-Operating_System
unit	I-Operating_System
.	O
</s>
<s>
Intel	O
's	O
low-powered	O
Bonnell	B-Device
microarchitecture	I-Device
employed	O
in	O
early	O
Atom	B-Device
processor	I-Device
cores	O
also	O
uses	O
an	O
in-order	O
dual	O
pipeline	B-General_Concept
similar	O
to	O
P5	B-General_Concept
.	O
</s>
<s>
Intel	O
used	O
the	O
Pentium	B-General_Concept
name	O
instead	O
of	O
80586	O
,	O
because	O
it	O
discovered	O
that	O
numbers	O
cannot	O
be	O
trademarked	O
.	O
</s>
<s>
The	O
P5	B-General_Concept
microarchitecture	B-General_Concept
brings	O
several	O
important	O
advances	O
over	O
the	O
prior	O
i486	B-General_Concept
architecture	O
.	O
</s>
<s>
Superscalar	B-General_Concept
architecture	I-General_Concept
–	O
The	O
Pentium	B-General_Concept
has	O
two	O
datapaths	O
(	O
pipelines	B-General_Concept
)	O
that	O
allow	O
it	O
to	O
complete	O
two	O
instructions	O
per	O
clock	O
cycle	O
in	O
many	O
cases	O
.	O
</s>
<s>
Some	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
proponents	O
had	O
argued	O
that	O
the	O
"	O
complicated	O
"	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
would	O
probably	O
never	O
be	O
implemented	O
by	O
a	O
tightly	O
pipelined	O
microarchitecture	B-General_Concept
,	O
much	O
less	O
by	O
a	O
dual-pipeline	O
design	O
.	O
</s>
<s>
The	O
486	B-General_Concept
and	O
the	O
Pentium	B-General_Concept
demonstrated	O
that	O
this	O
was	O
indeed	O
possible	O
and	O
feasible	O
.	O
</s>
<s>
64-bit	B-Device
external	O
databus	O
doubles	O
the	O
amount	O
of	O
information	O
possible	O
to	O
read	O
or	O
write	O
on	O
each	O
memory	O
access	O
and	O
therefore	O
allows	O
the	O
Pentium	B-General_Concept
to	O
load	O
its	O
code	O
cache	O
faster	O
than	O
the	O
80486	B-General_Concept
;	O
it	O
also	O
allows	O
faster	O
access	O
and	O
storage	O
of	O
64-bit	B-Device
and	O
80-bit	O
x87	B-Application
FPU	I-Application
data	O
.	O
</s>
<s>
Separation	O
of	O
code	O
and	O
data	B-General_Concept
caches	I-General_Concept
lessens	O
the	O
fetch	O
and	O
operand	O
read/write	O
conflicts	O
compared	O
to	O
the	O
486	B-General_Concept
.	O
</s>
<s>
To	O
reduce	O
access	O
time	O
and	O
implementation	O
cost	O
,	O
both	O
of	O
them	O
are	O
2-way	O
associative	O
,	O
instead	O
of	O
the	O
single	O
4-way	O
cache	O
of	O
the	O
486	B-General_Concept
.	O
</s>
<s>
A	O
related	O
enhancement	O
in	O
the	O
Pentium	B-General_Concept
is	I-General_Concept
the	O
ability	O
to	O
read	O
a	O
contiguous	O
block	O
from	O
the	O
code	O
cache	O
even	O
when	O
it	O
is	O
split	O
between	O
two	O
cache	O
lines	O
(	O
at	O
least	O
17	O
bytes	O
in	O
worst	O
case	O
)	O
.	O
</s>
<s>
Much	O
faster	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Some	O
instructions	O
showed	O
an	O
enormous	O
improvement	O
,	O
most	O
notably	O
FMUL	O
,	O
with	O
up	O
to	O
15	O
times	O
higher	O
throughput	O
than	O
in	O
the	O
80486	B-General_Concept
FPU	B-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
is	I-General_Concept
also	O
able	O
to	O
execute	O
a	O
FXCH	O
ST(x )	O
instruction	O
in	O
parallel	O
with	O
an	O
ordinary	O
(	O
arithmetical	O
or	O
load/store	O
)	O
FPU	B-General_Concept
instruction	O
.	O
</s>
<s>
Four-input	O
address	O
adders	O
enables	O
the	O
Pentium	B-General_Concept
to	O
further	O
reduce	O
the	O
address	O
calculation	O
latency	O
compared	O
to	O
the	O
80486	B-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
can	O
calculate	O
full	O
addressing	O
modes	O
with	O
segment-base	O
+	O
base-register	O
+	O
scaled	O
register	O
+	O
immediate	O
offset	O
in	O
a	O
single	O
cycle	O
;	O
the	O
486	B-General_Concept
has	O
a	O
three-input	O
address	O
adder	O
only	O
,	O
and	O
must	O
therefore	O
divide	O
such	O
calculations	O
between	O
two	O
cycles	O
.	O
</s>
<s>
The	O
microcode	B-Device
can	O
employ	O
both	O
pipelines	B-General_Concept
to	O
enable	O
auto-repeating	O
instructions	O
such	O
as	O
REP	O
MOVSW	O
perform	O
one	O
iteration	O
every	O
clock	O
cycle	O
,	O
while	O
the	O
80486	B-General_Concept
needed	O
three	O
clocks	O
per	O
iteration	O
(	O
and	O
the	O
earliest	O
x86	B-Operating_System
chips	O
significantly	O
more	O
than	O
the	O
486	B-General_Concept
)	O
.	O
</s>
<s>
Also	O
,	O
optimization	O
of	O
the	O
access	O
to	O
the	O
first	O
microcode	B-Device
words	O
during	O
the	O
decode	O
stages	O
helps	O
in	O
making	O
several	O
frequent	O
instructions	O
execute	O
significantly	O
more	O
quickly	O
,	O
especially	O
in	O
their	O
most	O
common	O
forms	O
and	O
in	O
typical	O
cases	O
.	O
</s>
<s>
Some	O
examples	O
are	O
(	O
486	B-General_Concept
→	O
Pentium	B-General_Concept
,	O
in	O
clock	O
cycles	O
)	O
:	O
CALL	O
(	O
3	B-General_Concept
→	O
1	O
)	O
,	O
RET	O
(	O
5	O
→	O
2	O
)	O
,	O
shifts/rotates	O
(	O
2	O
–	O
3	B-General_Concept
→	O
1	O
)	O
.	O
</s>
<s>
A	O
faster	O
,	O
fully	O
hardware-based	O
multiplier	O
makes	O
instructions	O
such	O
as	O
MUL	O
and	O
IMUL	O
several	O
times	O
faster	O
(	O
and	O
more	O
predictable	O
)	O
than	O
in	O
the	O
80486	B-General_Concept
;	O
the	O
execution	O
time	O
is	O
reduced	O
from	O
13	O
to	O
42	O
clock	O
cycles	O
down	O
to	O
10	O
–	O
11	O
for	O
32-bit	O
operands	O
.	O
</s>
<s>
Virtualized	O
interrupt	O
to	O
speed	O
up	O
virtual	B-Application
8086	I-Application
mode	I-Application
.	O
</s>
<s>
Enhanced	O
debug	O
features	O
with	O
the	O
introduction	O
of	O
the	O
Processor-based	O
debug	O
port	O
(	O
see	O
Pentium	B-General_Concept
Processor	O
Debugging	O
in	O
the	O
Developers	O
Manual	O
,	O
Vol	O
1	O
)	O
.	O
</s>
<s>
The	O
later	O
Pentium	B-General_Concept
MMX	B-Architecture
also	O
added	O
the	O
MMX	B-Architecture
instruction	I-Architecture
set	I-Architecture
,	O
a	O
basic	O
integer	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
marketed	O
for	O
use	O
in	O
multimedia	O
applications	O
.	O
</s>
<s>
MMX	B-Architecture
could	O
not	O
be	O
used	O
simultaneously	O
with	O
the	O
x87	B-Application
FPU	I-Application
instructions	O
because	O
the	O
registers	O
were	O
reused	O
(	O
to	O
allow	O
fast	O
context	O
switches	O
)	O
.	O
</s>
<s>
More	O
important	O
enhancements	O
were	O
the	O
doubling	O
of	O
the	O
instruction	O
and	O
data	B-General_Concept
cache	I-General_Concept
sizes	O
and	O
a	O
few	O
microarchitectural	B-General_Concept
changes	O
for	O
better	O
performance	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
was	O
designed	O
to	O
execute	O
over	O
100	O
million	O
instructions	O
per	O
second	O
(	O
MIPS	B-Device
)	O
,	O
and	O
the	O
75MHz	O
model	O
was	O
able	O
to	O
reach	O
126.5	O
MIPS	B-Device
in	O
certain	O
benchmarks	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
architecture	O
typically	O
offered	O
just	O
under	O
twice	O
the	O
performance	O
of	O
a	O
486	B-General_Concept
processor	I-General_Concept
per	O
clock	O
cycle	O
in	O
common	O
benchmarks	O
.	O
</s>
<s>
The	O
fastest	O
80486	B-General_Concept
parts	O
(	O
with	O
slightly	O
improved	O
microarchitecture	B-General_Concept
and	O
100MHz	O
operation	O
)	O
were	O
almost	O
as	O
powerful	O
as	O
the	O
first-generation	O
Pentiums	B-General_Concept
,	O
and	O
the	O
AMD	B-Device
Am5x86	I-Device
,	O
which	O
despite	O
its	O
name	O
is	O
actually	O
a	O
486-class	O
CPU	O
,	O
was	O
roughly	O
equal	O
to	O
the	O
Pentium	B-General_Concept
75	O
regarding	O
pure	O
ALU	O
performance	O
.	O
</s>
<s>
The	O
early	O
versions	O
of	O
60	O
–	O
100MHz	O
P5	B-General_Concept
Pentiums	B-General_Concept
had	O
a	O
problem	O
in	O
the	O
floating-point	B-General_Concept
unit	I-General_Concept
that	O
resulted	O
in	O
incorrect	O
(	O
but	O
predictable	O
)	O
results	O
from	O
some	O
division	O
operations	O
.	O
</s>
<s>
This	O
flaw	O
,	O
discovered	O
in	O
1994	O
by	O
professor	O
Thomas	B-Device
Nicely	I-Device
at	O
Lynchburg	O
College	O
,	O
Virginia	O
,	O
became	O
widely	O
known	O
as	O
the	O
Pentium	B-Device
FDIV	I-Device
bug	I-Device
and	O
caused	O
embarrassment	O
for	O
Intel	O
,	O
which	O
created	O
an	O
exchange	O
program	O
to	O
replace	O
the	O
faulty	O
processors	O
.	O
</s>
<s>
In	O
1997	O
,	O
another	O
erratum	O
was	O
discovered	O
that	O
could	O
allow	O
a	O
malicious	O
program	O
to	O
crash	O
a	O
system	O
without	O
any	O
special	O
privileges	O
,	O
the	O
"	O
F00F	B-Error_Name
bug	I-Error_Name
"	O
.	O
</s>
<s>
All	O
P5	B-General_Concept
series	O
processors	O
were	O
affected	O
and	O
no	O
fixed	O
steppings	B-General_Concept
were	O
ever	O
released	O
,	O
however	O
contemporary	O
operating	B-General_Concept
systems	I-General_Concept
were	O
patched	O
with	O
workarounds	O
to	O
prevent	O
crashes	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
was	O
Intel	O
's	O
primary	O
microprocessor	B-Architecture
for	O
personal	O
computers	O
during	O
the	O
mid-1990s	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
there	O
were	O
several	O
variants	O
of	O
the	O
P5	B-General_Concept
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
first	O
Pentium	B-General_Concept
microprocessor	B-Architecture
core	O
was	O
code-named	O
"	O
P5	B-General_Concept
"	O
.	O
</s>
<s>
Its	O
product	O
code	O
was	O
80501	O
(	O
80500	O
for	O
the	O
earliest	O
steppings	B-General_Concept
Q0399	O
)	O
.	O
</s>
<s>
There	O
were	O
two	O
versions	O
,	O
specified	O
to	O
operate	O
at	O
60MHz	O
and	O
66MHz	O
respectively	O
,	O
using	O
Socket	B-Device
4	I-Device
.	O
</s>
<s>
This	O
first	O
implementation	O
of	O
the	O
Pentium	B-General_Concept
used	O
a	O
traditional	O
5-volt	O
power	O
supply	O
(	O
descended	O
from	O
the	O
usual	O
transistor-transistor	B-General_Concept
logic	I-General_Concept
(	O
TTL	B-General_Concept
)	O
compatibility	O
requirements	O
)	O
.	O
</s>
<s>
It	O
contained	O
3.1	O
million	O
transistors	B-Application
and	O
measured	O
16.7mm	O
by	O
17.6mm	O
for	O
an	O
area	O
of	O
293.92mm2	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
0.8	O
μm	B-Algorithm
bipolar	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
BiCMOS	B-General_Concept
)	O
process	O
.	O
</s>
<s>
The	O
P5	B-General_Concept
was	O
followed	O
by	O
the	O
P54C	O
(	O
80502	O
)	O
in	O
1994	O
,	O
with	O
versions	O
specified	O
to	O
operate	O
at	O
75	O
,	O
90	O
,	O
or	O
100MHz	O
using	O
a	O
3.3	O
volt	O
power	O
supply	O
.	O
</s>
<s>
Marking	O
the	O
switch	O
to	O
Socket	B-General_Concept
5	I-General_Concept
,	O
this	O
was	O
the	O
first	O
Pentium	B-General_Concept
processor	O
to	O
operate	O
at	O
3.3	O
volts	O
,	O
reducing	O
energy	O
consumption	O
,	O
but	O
necessitating	O
voltage	O
regulation	O
on	O
mainboards	O
.	O
</s>
<s>
As	O
with	O
higher-clocked	O
486	B-General_Concept
processors	I-General_Concept
,	O
an	O
internal	O
clock	O
multiplier	O
was	O
employed	O
from	O
here	O
on	O
to	O
let	O
the	O
internal	O
circuitry	O
work	O
at	O
a	O
higher	O
frequency	O
than	O
the	O
external	O
address	O
and	O
data	B-General_Concept
buses	I-General_Concept
,	O
as	O
it	O
is	O
more	O
complicated	O
and	O
cumbersome	O
to	O
increase	O
the	O
external	O
frequency	O
,	O
due	O
to	O
physical	O
constraints	O
.	O
</s>
<s>
It	O
also	O
allowed	O
two-way	O
multiprocessing	O
,	O
and	O
had	O
an	O
integrated	O
local	B-Device
APIC	I-Device
and	O
new	O
power	O
management	O
features	O
.	O
</s>
<s>
It	O
contained	O
3.3	O
million	O
transistors	B-Application
and	O
measured	O
163mm2	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
BiCMOS	B-General_Concept
process	O
which	O
has	O
been	O
described	O
as	O
both	O
0.5μm	O
and	O
0.6	B-Algorithm
μm	I-Algorithm
due	O
to	O
differing	O
definitions	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
0.35	O
μm	B-Algorithm
BiCMOS	B-General_Concept
process	O
and	O
was	O
the	O
first	O
commercial	O
microprocessor	B-Architecture
to	O
be	O
fabricated	O
in	O
a	O
0.35μm	O
process	O
.	O
</s>
<s>
Its	O
transistor	B-Application
count	O
is	O
identical	O
to	O
the	O
P54C	O
and	O
,	O
despite	O
the	O
newer	O
process	O
,	O
it	O
had	O
an	O
identical	O
die	O
area	O
as	O
well	O
.	O
</s>
<s>
The	O
chip	O
was	O
connected	O
to	O
the	O
package	O
using	O
wire	B-Algorithm
bonding	I-Algorithm
,	O
which	O
only	O
allows	O
connections	O
along	O
the	O
edges	O
of	O
the	O
chip	O
.	O
</s>
<s>
The	O
solution	O
was	O
to	O
keep	O
the	O
chip	O
the	O
same	O
size	O
,	O
retain	O
the	O
existing	O
pad-ring	O
,	O
and	O
only	O
reduce	O
the	O
size	O
of	O
the	O
Pentium	B-General_Concept
's	O
logic	O
circuitry	O
to	O
enable	O
it	O
to	O
achieve	O
higher	O
clock	O
frequencies	O
.	O
</s>
<s>
The	O
P54CQS	O
was	O
quickly	O
followed	O
by	O
the	O
P54CS	O
,	O
which	O
operated	O
at	O
133	O
,	O
150	O
,	O
166	O
and	O
200MHz	O
,	O
and	O
introduced	O
Socket	B-General_Concept
7	I-General_Concept
.	O
</s>
<s>
It	O
contained	O
3.3	O
million	O
transistors	B-Application
,	O
measured	O
90mm2	O
and	O
was	O
fabricated	O
in	O
a	O
0.35μm	O
BiCMOS	B-General_Concept
process	O
with	O
four	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
P24T	O
Pentium	B-Device
OverDrive	I-Device
for	O
486	B-General_Concept
systems	O
were	O
released	O
in	O
1995	O
,	O
which	O
were	O
based	O
on	O
3.3V	O
0.6μm	O
versions	O
using	O
a	O
63	O
or	O
83MHz	O
clock	O
.	O
</s>
<s>
Since	O
these	O
used	O
Socket	O
2/3	O
,	O
some	O
modifications	O
had	O
to	O
be	O
made	O
to	O
compensate	O
for	O
the	O
32-bit	O
data	B-General_Concept
bus	I-General_Concept
and	O
slower	O
on-board	O
L2	O
cache	O
of	O
486	B-General_Concept
motherboards	O
.	O
</s>
<s>
They	O
were	O
therefore	O
equipped	O
with	O
a	O
32KB	O
L1	O
cache	O
(	O
double	O
that	O
of	O
pre-P55C	O
Pentium	B-General_Concept
CPUs	O
)	O
.	O
</s>
<s>
The	O
P55C	O
(	O
or	O
80503	O
)	O
was	O
developed	O
by	O
Intel	O
's	O
Research	O
&	O
Development	O
Center	O
in	O
Haifa	B-Algorithm
,	I-Algorithm
Israel	I-Algorithm
.	O
</s>
<s>
It	O
was	O
sold	O
as	O
Pentium	B-General_Concept
with	O
MMX	B-Architecture
Technology	O
(	O
usually	O
just	O
called	O
Pentium	B-General_Concept
MMX	B-Architecture
)	O
;	O
although	O
it	O
was	O
based	O
on	O
the	O
P5	B-General_Concept
core	O
,	O
it	O
featured	O
a	O
new	O
set	O
of	O
57	O
"	O
MMX	B-Architecture
"	O
instructions	O
intended	O
to	O
improve	O
performance	O
on	O
multimedia	O
tasks	O
,	O
such	O
as	O
encoding	O
and	O
decoding	O
digital	O
media	O
data	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
MMX	B-Architecture
line	O
was	O
introduced	O
on	O
October	O
22	O
,	O
1996	O
,	O
and	O
released	O
in	O
January	O
1997	O
.	O
</s>
<s>
The	O
new	O
instructions	O
worked	O
on	O
new	O
data	O
types	O
:	O
64-bit	B-Device
packed	O
vectors	O
of	O
either	O
eight	O
8-bit	O
integers	O
,	O
four	O
16-bit	O
integers	O
,	O
two	O
32-bit	O
integers	O
,	O
or	O
one	O
64-bit	B-Device
integer	O
.	O
</s>
<s>
So	O
,	O
for	O
example	O
,	O
the	O
PADDUSB	O
(	O
Packed	O
ADD	O
Unsigned	O
Saturated	O
Byte	O
)	O
instruction	O
adds	O
two	O
vectors	O
,	O
each	O
containing	O
eight	O
8-bit	O
unsigned	O
integers	O
together	O
,	O
elementwise	O
;	O
each	O
addition	O
that	O
would	O
overflow	B-Algorithm
saturates	O
,	O
yielding	O
255	O
,	O
the	O
maximal	O
unsigned	O
value	O
that	O
can	O
be	O
represented	O
in	O
a	O
byte	O
.	O
</s>
<s>
Other	O
changes	O
to	O
the	O
core	O
include	O
a	O
6-stage	O
pipeline	B-General_Concept
(	O
vs	O
.	O
5	O
on	O
P5	B-General_Concept
)	O
with	O
a	O
return	O
stack	O
(	O
first	O
done	O
on	O
Cyrix	B-General_Concept
6x86	I-General_Concept
)	O
and	O
better	O
parallelism	O
,	O
an	O
improved	O
instruction	O
decoder	O
,	O
16KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
+	O
16KB	O
L1	O
instruction	O
cache	O
with	O
Both	O
4-way	O
associativity	O
(	O
vs	O
.	O
8KB	O
L1	O
Data/instruction	O
with	O
2-way	O
on	O
P5	B-General_Concept
)	O
,	O
4	O
write	O
buffers	O
that	O
could	O
now	O
be	O
used	O
by	O
either	O
pipeline	B-General_Concept
(	O
vs	O
.	O
one	O
corresponding	O
to	O
each	O
pipeline	B-General_Concept
on	O
P5	B-General_Concept
)	O
and	O
an	O
improved	O
branch	B-General_Concept
predictor	I-General_Concept
taken	O
from	O
the	O
Pentium	B-General_Concept
Pro	O
,	O
with	O
a	O
512-entry	O
buffer	O
(	O
vs	O
.	O
256	O
on	O
P5	B-General_Concept
)	O
.	O
</s>
<s>
It	O
contained	O
4.5	O
million	O
transistors	B-Application
and	O
had	O
an	O
area	O
of	O
140mm2	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
in	O
a	O
0.28μm	O
CMOS	O
process	O
with	O
the	O
same	O
metal	O
pitches	O
as	O
the	O
previous	O
0.35μm	O
BiCMOS	B-General_Concept
process	O
,	O
so	O
Intel	O
described	O
it	O
as	O
"	O
0.35μm	O
"	O
because	O
of	O
its	O
similar	O
transistor	B-Application
density	O
.	O
</s>
<s>
The	O
process	O
has	O
four	O
levels	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
While	O
the	O
P55C	O
remained	O
compatible	O
with	O
Socket	B-General_Concept
7	I-General_Concept
,	O
the	O
voltage	O
requirements	O
for	O
powering	O
the	O
chip	O
differ	O
from	O
the	O
standard	O
Socket	B-General_Concept
7	I-General_Concept
specifications	O
.	O
</s>
<s>
Most	O
motherboards	O
manufactured	O
for	O
Socket	B-General_Concept
7	I-General_Concept
before	O
the	O
establishment	O
of	O
the	O
P55C	O
standard	O
are	O
not	O
compliant	O
with	O
the	O
dual	O
voltage	O
rail	O
required	O
for	O
proper	O
operation	O
of	O
this	O
CPU	O
(	O
2.8	O
volt	O
core	O
voltage	O
,	O
3.3	O
volt	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
voltage	O
)	O
.	O
</s>
<s>
Pentium	B-General_Concept
MMX	B-Architecture
notebook	B-Device
CPUs	O
used	O
a	O
mobile	O
module	O
that	O
held	O
the	O
CPU	O
.	O
</s>
<s>
The	O
module	O
snapped	O
to	O
the	O
notebook	B-Device
motherboard	O
,	O
and	O
typically	O
a	O
heat	O
spreader	O
was	O
installed	O
and	O
made	O
contact	O
with	O
the	O
module	O
.	O
</s>
<s>
However	O
,	O
with	O
the	O
0.25μm	O
Tillamook	O
Mobile	O
Pentium	B-General_Concept
MMX	B-Architecture
(	O
named	O
after	O
a	O
city	O
in	O
Oregon	O
)	O
,	O
the	O
module	O
also	O
held	O
the	O
430TX	O
chipset	O
along	O
with	O
the	O
system	O
's	O
512	O
KB	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
cache	O
memory	O
.	O
</s>
<s>
+Pentium	O
and	O
Pentium	B-General_Concept
with	O
MMX	B-Architecture
Technology	O
center|80px	O
center|80px	O
80px	O
80px	O
80px	O
80px	O
80px	O
80px	O
80px	O
80px	O
80px	O
center|80px	O
Code	O
name	O
P5	B-General_Concept
P54C	O
P54C/P54CQS	O
P54CS	O
P55C	O
Tillamook	O
Product	O
code	O
80501	O
80502	O
80503	O
Process	O
size	O
( μm	O
)	O
0.80	O
0.60	O
or	O
0.35*	O
0.35	O
0.35	O
(	O
later	O
0.28	O
)	O
0.25	O
Die	O
area	O
(	O
mm2	O
)	O
293.92	O
(	O
16.7	O
x	O
17.6	O
mm	O
)	O
148	O
@	O
0	O
,	O
6	O
μm	B-Algorithm
/	O
91	O
(	O
later	O
83	O
)	O
@	O
0	O
,	O
35	O
μm	B-Algorithm
91	O
(	O
later	O
83	O
)	O
141	O
@	O
0	O
,	O
35	O
μm	B-Algorithm
/	O
128	O
@	O
0	O
,	O
28	O
μm	B-Algorithm
94.47	O
(	O
9.06272	O
x	O
10.42416	O
mm	O
)	O
Number	O
of	O
transistors	B-Application
(	O
millions	O
)	O
3.10	O
3.20	O
3.30	O
4.50	O
Socket	O
Socket	B-Device
4	I-Device
Socket	O
5/7	O
Socket	B-General_Concept
7	I-General_Concept
Package	O
CPGA/CPGA	O
+IHS	O
CPGA/CPGA	O
+	O
IHS/TCP	O
*	O
CPGA/TCP	O
*	O
CPGA/TCP	O
*	O
CPGA/PPGA	O
PPGA	B-Algorithm
TCP*	O
CPGA/PPGA/TCP	O
*	O
PPGA/TCP	O
*	O
TCP/TCP	O
on	O
MMC-1	B-Device
Clock	O
speed	O
(	O
MHz	O
)	O
60	O
66	O
75	O
90	O
100	O
120	O
133	O
150	O
166	O
200	O
120*	O
133*	O
150*	O
166	O
200	O
233	O
166	O
200	O
233	O
266	O
300	O
Bus	O
speed	O
(	O
MHz	O
)	O
60	O
66	O
50	O
60	O
50	O
66	O
60	O
66	O
60	O
66	O
60	O
66	O
60	O
66	O
Core	O
Voltage	O
5.0	O
5.15	O
3.3	O
2	O
,	O
9*	O
3.3	O
2.9*	O
3.3	O
3.1*	O
2.9*	O
3.3	O
3.1*	O
2.9*	O
3.3	O
3.1*	O
2.9*	O
3.3	O
3.1*	O
2.9*	O
3.3	O
3.3	O
2.2*	O
2.45*	O
2.45*	O
2.8	O
2.45*	O
2.8	O
2.8	O
1.9	O
1.8*	O
1.8*	O
1.8*	O
1.9	O
2.0*	O
2.0*	O
I/O	B-General_Concept
Voltage	O
5.0	O
5.15	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
3.3	O
2.5	O
2.5	O
2.5	O
2.5	O
2.5	O
TDP	B-General_Concept
(	O
max	O
.	O
</s>
<s>
W	O
)	O
14.6	O
(	O
15.3	O
)	O
16.0	O
(	O
17.3	O
)	O
8.0	O
(	O
9.5	O
)	O
6.0*	O
(	O
7.3*	O
)	O
9.0	O
(	O
10.6	O
)	O
7.3*	O
(	O
8.8*	O
)	O
10.1	O
(	O
11.7	O
)	O
8.0	O
at	O
0.6μ*	O
(	O
9.8	O
at	O
0.6μ*	O
)	O
5.9	O
at	O
0.35μ*	O
(	O
7.6	O
at	O
0.35μ*	O
)	O
12.8	O
(	O
13.4	O
)	O
7.1*	O
(	O
8.8*	O
)	O
11.2	O
(	O
12.2	O
)	O
7.9*	O
(	O
9.8*	O
)	O
11.6	O
(	O
13.9	O
)	O
10.0*	O
(	O
12.0*	O
)	O
14.5	O
(	O
15.3	O
)	O
15.5	O
(	O
16.6	O
)	O
4.2*	O
7.8*	O
(	O
11.8*	O
)	O
8.6*	O
(	O
12.7*	O
)	O
13.1	O
(	O
15.7	O
)	O
9.0*	O
(	O
13.7*	O
)	O
15.7	O
(	O
18.9	O
)	O
17.0	O
(	O
21.5	O
)	O
4.5	O
(	O
7.4	O
)	O
4.1*	O
(	O
5.4*	O
)	O
5.0*	O
(	O
6.1*	O
)	O
5.5*	O
(	O
7.0*	O
)	O
7.6	O
(	O
9.2	O
)	O
7.6*	O
(	O
9.6*	O
)	O
8.0*	O
Introduced	O
1993-03-22	O
1994-10-10	O
1994-03-07	O
1995-03-27	O
1995-06-12	O
1996-01-04	O
1996-06-10	O
1997-10-20	O
1997-05-19	O
1997-01-08	O
1997-06-02	O
1997-08	O
1998-01	O
1999-01	O
*	O
An	O
asterisk	O
indicates	O
that	O
these	O
were	O
only	O
available	O
as	O
Mobile	O
Pentium	B-General_Concept
or	O
Mobile	O
Pentium	B-General_Concept
MMX	B-Architecture
chips	O
for	O
laptops	B-Device
.	O
</s>
<s>
+Pentium	O
OverDrive	O
with	O
MMX	B-Architecture
Technology	O
center|80px	O
Code	O
name	O
P54CTB	O
Product	O
code	O
PODPMT60X150	O
PODPMT66X166	O
PODPMT60X180	O
PODPMT66X200	O
Process	O
size	O
( μm	O
)	O
0.35	O
Socket	O
Socket	O
5/7	O
Package	O
CPGA	B-Algorithm
with	O
heatsink	O
,	O
fan	O
and	O
voltage	O
regulator	O
Clock	O
speed	O
(	O
MHz	O
)	O
125	O
150	O
166	O
150	O
180	O
200	O
Bus	O
speed	O
(	O
MHz	O
)	O
50	O
60	O
66	O
50	O
60	O
66	O
Upgrade	O
for	O
Pentium	B-General_Concept
75	O
Pentium	B-General_Concept
90	O
Pentium	B-General_Concept
100	O
and	O
133	O
Pentium	B-General_Concept
75	O
Pentium	B-General_Concept
90	O
,	O
120	O
and	O
150	O
Pentium	B-General_Concept
100	O
,	O
133	O
and	O
166	O
TDP	B-General_Concept
(	O
max	O
.	O
</s>
<s>
+Embedded	O
versions	O
of	O
Pentium	B-General_Concept
with	O
MMX	B-Architecture
Technology	O
center|80px	O
center|80px	O
Code	O
name	O
P55C	O
Tillamook	O
Product	O
code	O
FV8050366200	O
FV8050366233	O
FV80503CSM66166	O
GC80503CSM66166	O
GC80503CS166EXT	O
FV80503CSM66266	O
GC80503CSM66266	O
Process	O
size	O
( μm	O
)	O
0.35	O
0.25	O
Clock	O
speed	O
(	O
MHz	O
)	O
200	O
233	O
166	O
166	O
166	O
266	O
266	O
Bus	O
speed	O
(	O
MHz	O
)	O
66	O
66	O
66	O
66	O
66	O
66	O
66	O
Package	O
PPGA	B-Algorithm
PPGA	B-Algorithm
PPGA	B-Algorithm
BGA	B-Algorithm
BGA	B-Algorithm
PPGA	B-Algorithm
BGA	B-Algorithm
TDP	B-General_Concept
(	O
max	O
.	O
</s>
<s>
After	O
the	O
introduction	O
of	O
the	O
Pentium	B-General_Concept
,	O
competitors	O
such	O
as	O
NexGen	O
,	O
AMD	O
,	O
Cyrix	O
,	O
and	O
Texas	O
Instruments	O
announced	O
Pentium-compatible	O
processors	O
in	O
1994	O
.	O
</s>
<s>
CIO	O
magazine	O
identified	O
NexGen	O
's	O
Nx586	B-Device
as	O
the	O
first	O
Pentium-compatible	O
CPU	O
,	O
while	O
PC	O
Magazine	O
described	O
the	O
Cyrix	B-General_Concept
6x86	I-General_Concept
as	O
the	O
first	O
.	O
</s>
<s>
AMD	O
later	O
bought	O
NexGen	O
to	O
help	O
design	O
the	O
AMD	B-Architecture
K6	I-Architecture
,	O
and	O
Cyrix	O
was	O
bought	O
by	O
National	O
Semiconductor	O
.	O
</s>
<s>
Later	O
processors	O
from	O
AMD	O
and	O
Intel	O
retain	O
compatibility	O
with	O
the	O
original	B-General_Concept
Pentium	I-General_Concept
.	O
</s>
